AIDA FMC Mini-TLU
Firmware for FMC-based mini-TLU (Trigger/Timing/Tagging Logic Unit) for AIDA
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Design Unit Hierarchy

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This inheritance list is sorted roughly, but not completely, alphabetically:
[detail level 1234]
oCfmc_tlu_sp601_tb
|oCfmc_tlu_sp601
||\Cpulse_shaperOutput goes high when input goes high ( asyncnronous to system clock). Output goes low again a controllable number of clock cycles later, synchronous with the rising edge of the clock. Gap of at least one clock cycle before output goes high again
|| oCdtype_fdpe
|| oCdtype_fdr(2)Aims to be the same as the Xilinx "FD" primitive - D-Type flip-flop
|| oCdtype_fds(2)Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
|| \Cdtype_fd
|\Cpulse_shaper_scorerChecks that pulse_shaper is behaving correctly. Check for Output goes high when input goes high ( asyncnronous to system clock). Output goes low again a controllable number of clock cycles later, synchronous with the rising edge of the clock. Gap of at least one clock cycle before output goes high again
oCfmc_tlu_top
oCFmcTluI2c
oCobject
|\CI2cBusPropertiesI2cBusProperties - simple encapsulation of all items required to control an I2C bus
oCpulse_shaper_async_dtypes
|\Cdtype_fdpe(3)
oCpulseClockDomainCrossing
oCRawI2cAccess
oCserdes_1_to_n_SDR
oCslaves
|\Cipbus_ver
\Ctop_extphy
 oCDUTInterfaces
 oCIPBusInterface
 |oCclocks_s6_extphy
 |\Cipbus_ver
 oCeventBuffer
 |\CregisterCounter
 oCeventFormatter
 oCi2c_master
 oClogic_clocks
 oCtriggerInputs
 |oCdualSERDES_1to4(2)
 |\CarrivalTimeLUT(2)
 \CtriggerLogic
  \Csync_reg(3)
   \CReg_2clks