Output goes high when input goes high ( asyncnronous to system clock). Output goes low again a controllable number of clock cycles later, synchronous with the rising edge of the clock. Gap of at least one clock cycle before output goes high again.
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|
D_a_i | in |
| Input pulse.
|
Q_a_o | out |
| output pulse
|
CLK_i | in |
| Clock , rising edge active.
|
RST_i | in |
| Hold high for PULSE_LENGTH+4.
|
PULSE_LENGTH_i | in ( 3 downto 0 ) |
| length of output pulse
|
Output goes high when input goes high ( asyncnronous to system clock). Output goes low again a controllable number of clock cycles later, synchronous with the rising edge of the clock. Gap of at least one clock cycle before output goes high again.
Input pulse.
- Todo:
- Broaden pulse fed into set/reset flip-flop
The documentation for this class was generated from the following file:
- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/pulse_shaper.vhdl