<?xml version="1.0" encoding="UTF-8"?>
<probeData version="2" minor="0">
  <probeset name="EDA_PROBESET" active="true">
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="0"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="1"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
      </probeOptions>
      <nets>
        <net name="I5/s_deserialized_threshold_data[0][7]"/>
        <net name="I5/s_deserialized_threshold_data[0][6]"/>
        <net name="I5/s_deserialized_threshold_data[0][5]"/>
        <net name="I5/s_deserialized_threshold_data[0][4]"/>
        <net name="I5/s_deserialized_threshold_data[0][3]"/>
        <net name="I5/s_deserialized_threshold_data[0][2]"/>
        <net name="I5/s_deserialized_threshold_data[0][1]"/>
        <net name="I5/s_deserialized_threshold_data[0][0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="2"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="I5/s_threshold_previous_late_bit[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="3"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
      </probeOptions>
      <nets>
        <net name="I5/trigger_o[5]"/>
        <net name="I5/trigger_o[4]"/>
        <net name="I5/trigger_o[3]"/>
        <net name="I5/trigger_o[2]"/>
        <net name="I5/trigger_o[1]"/>
        <net name="I5/trigger_o[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="4"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="5"/>
      </probeOptions>
      <nets>
        <net name="I5/trigger_times_o[0][4]"/>
        <net name="I5/trigger_times_o[0][3]"/>
        <net name="I5/trigger_times_o[0][2]"/>
        <net name="I5/trigger_times_o[0][1]"/>
        <net name="I5/trigger_times_o[0][0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="5"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
      </probeOptions>
      <nets>
        <net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
        <net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
        <net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
        <net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
        <net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
        <net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="6"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
      </probeOptions>
      <nets>
        <net name="I10/trigger_i[5]"/>
        <net name="I10/trigger_i[4]"/>
        <net name="I10/trigger_i[3]"/>
        <net name="I10/trigger_i[2]"/>
        <net name="I10/trigger_i[1]"/>
        <net name="I10/trigger_i[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="7"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
      </probeOptions>
      <nets>
        <net name="postVetotrigger[5]"/>
        <net name="postVetotrigger[4]"/>
        <net name="postVetotrigger[3]"/>
        <net name="postVetotrigger[2]"/>
        <net name="postVetotrigger[1]"/>
        <net name="postVetotrigger[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="8"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
      </probeOptions>
      <nets>
        <net name="triggers[5]"/>
        <net name="triggers[4]"/>
        <net name="triggers[3]"/>
        <net name="triggers[2]"/>
        <net name="triggers[1]"/>
        <net name="triggers[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="9"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="clk_ipb"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="10"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="11"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="I10/s_external_trigger_l"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="12"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="I10/s_external_trigger_p"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="13"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="sysclk_40"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="u_ila_0"/>
        <Option Id="PROBE_PORT" value="14"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="clk_8x_logic"/>
      </nets>
    </probe>
  </probeset>
</probeData>
