Skip to content

A
AIDA-2020 TLU - Software
Commit c1d1ccb3 authored by Paolo Baesso's avatar Paolo Baesso
Browse files
Options

Merge branch 'master' into documentation

parents 1cb4fbb5 5a108069
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 143418 additions and 229 deletions
EUDETdummy/constraints/EUDET_dummy_constr.xdc
View file @ c1d1ccb3
......@@ -28,8 +28,8 @@ set_property PACKAGE_PIN F6 [get_ports gpio]
## Crystal clock
set_property IOSTANDARD LVDS_25 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN T4 [get_ports sysclk_40_i_n]
set_property PACKAGE_PIN T5 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN T4 [get_ports sysclk_40_i_n]
## Output clock (currently not working so set to 0)
set_property IOSTANDARD LVCMOS33 [get_ports sysclk_50_o_p]
......@@ -106,3 +106,35 @@ set_property PACKAGE_PIN G3 [get_ports {dut_clk_i[3]}]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list sysclk_40_BUFG]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {TrigNArray[0][0]} {TrigNArray[0][1]} {TrigNArray[0][2]} {TrigNArray[0][3]} {TrigNArray[0][4]} {TrigNArray[0][5]} {TrigNArray[0][6]} {TrigNArray[0][7]} {TrigNArray[0][8]} {TrigNArray[0][9]} {TrigNArray[0][10]} {TrigNArray[0][11]} {TrigNArray[0][12]} {TrigNArray[0][13]} {TrigNArray[0][14]} {TrigNArray[0][15]} {TrigNArray[0][16]} {TrigNArray[0][17]} {TrigNArray[0][18]} {TrigNArray[0][19]} {TrigNArray[0][20]} {TrigNArray[0][21]} {TrigNArray[0][22]} {TrigNArray[0][23]} {TrigNArray[0][24]} {TrigNArray[0][25]} {TrigNArray[0][26]} {TrigNArray[0][27]} {TrigNArray[0][28]} {TrigNArray[0][29]} {TrigNArray[0][30]} {TrigNArray[0][31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {busy_o_OBUF[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {dut_clk_o_OBUF[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list TriggerNumberStrobe6_out]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets sysclk_40_BUFG]
EUDETdummy/hdl/Dummy_DUT.vhd
View file @ c1d1ccb3
......@@ -39,9 +39,10 @@ entity Dummy_DUT is
CLK : in STD_LOGIC; --! this is the USB clock.
RST : in STD_LOGIC; --! Synchronous clock
Trigger : in STD_LOGIC; --! Trigger from TLU
stretchBusy: in STD_LOGIC; -- flag: if 1, then we want to extend the BUSY signal
Busy : out STD_LOGIC; --! Busy to TLU
DUTClk : out STD_LOGIC; --! clock from DUT
TriggerNumber : out STD_LOGIC_VECTOR(15 downto 0);
TriggerNumber : out STD_LOGIC_VECTOR(31 downto 0);
TriggerNumberStrobe : out STD_LOGIC;
FSM_Error : out STD_LOGIC
);
......@@ -63,12 +64,12 @@ architecture RTL of Dummy_DUT is
signal Registered_Trigger , Registered_RST : std_logic; -- trigger and reset signals after being registered to suppress meta-stability.
signal TriggerShiftRegister : STD_LOGIC_VECTOR (15 downto 0); --! register
signal TriggerShiftRegister : STD_LOGIC_VECTOR (31 downto 0); --! register
--to accept
--incoming
--trigger number
type state_type is (IDLE , WAIT_FOR_TRIGGER_LOW , CLOCKING , OUTPUT_TRIGGER_NUMBER);
type state_type is (IDLE , WAIT_FOR_TRIGGER_LOW , CLOCKING , OUTPUT_TRIGGER_NUMBER, BUSYDELAY);
signal state : state_type := IDLE;
signal next_state : state_type := IDLE;
......@@ -81,6 +82,8 @@ architecture RTL of Dummy_DUT is
constant TriggerBitCounterLimit : unsigned(4 downto 0) := to_unsigned(16,5);
signal DUTClockCounter : unsigned(4 downto 0) := ( others => '0');
signal s_busySR : unsigned( 14 downto 0) := ( others => '0' ); -- --! Shift register to generate stretch
begin
......@@ -111,6 +114,30 @@ begin
end if;
end if;
end process busy_control;
-- busy_control: process (clk , state)
-- begin -- process busy_control
-- if rising_edge(clk) then
-- if (stretchBusy ='1') then
-- if ((state = IDLE) and (s_busySR=0)) then
-- busy <= '0';
-- s_busySR <= ( others => '1' );
-- elsif ( (state = IDLE) and (s_busySR /= 0) ) then
-- busy <= '1';
-- s_busySR <= s_busySR -1;
-- else
-- busy <= '1';
-- s_busySR <= s_busySR -1;
-- end if;
-- else
-- if state = IDLE then
-- busy <= '0';
-- else
-- busy <= '1';
-- end if;
-- end if;
-- end if;
-- end process busy_control;
clock_control: process (clk , state , TriggerBitCounter )
begin -- process busy_control
......@@ -153,7 +180,7 @@ begin
elsif state = CLOCKING then
if (InternalDUTClk = '1') and (DUTClockCounter=to_unsigned(1,4 )) then
-- if (InternalDUTClk = '1') and (DUTClockCounter=to_unsigned(1,DUTClockCounter'length )) then
TriggerShiftRegister <= trigger & TriggerShiftRegister( 15 downto 1) ;
TriggerShiftRegister <= trigger & TriggerShiftRegister( 31 downto 1) ;
-- TriggerShiftRegister <= trigger & TriggerShiftRegister( TriggerShiftRegister'high downto 1) ;
else
TriggerShiftRegister <= TriggerShiftRegister;
......@@ -174,11 +201,22 @@ begin
end if;
end process strobe_control;
busy_delay_control: process(clk, state)
begin
if rising_edge(clk) then
if state= BUSYDELAY then
s_busySR <= s_busySR -1;
elsif state= WAIT_FOR_TRIGGER_LOW then
s_busySR <= ( others => '1' );
end if;
end if;
end process busy_delay_control;
--! @brief controls the next state in the state machine
-- type : combinational
-- inputs : pattern_we, mask_we , beam_state_counter
-- outputs: state , beam_state_counter
state_logic: process (state, TriggerBitCounter , registered_trigger ,InternalDUTClk )
state_logic: process (state, TriggerBitCounter , registered_trigger ,InternalDUTClk, stretchBusy, s_busySR )
begin -- process state_logic
case state is
......@@ -187,7 +225,7 @@ begin
next_state <= WAIT_FOR_TRIGGER_LOW;
else
next_state <= IDLE;
end if;
end if;
when WAIT_FOR_TRIGGER_LOW =>
if ( registered_trigger = '0' ) then
......@@ -204,7 +242,18 @@ begin
end if;
when OUTPUT_TRIGGER_NUMBER =>
next_state <= IDLE;
if (stretchBusy ='1') then
next_state <= BUSYDELAY;
else
next_state <= IDLE;
end if;
when BUSYDELAY =>
if (s_busySR /= 0) then
next_state <= BUSYDELAY;
else
next_state <= IDLE;
end if;
when others =>
next_state <= IDLE;
......
EUDETdummy/hdl/dummyEventBuffer_rtl.vhd 0 → 100644
View file @ c1d1ccb3
--=============================================================================
--! @file eventBuffer_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.eventBuffer.rtl
--
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
--! @brief Stores input words (64bits) for readout over IPBus.
--! Uses a FIFO ( 64bits at input, 32 bits at output )
--
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:24:50 11/13/12
--
--! @version v0.1
--
--! @details
--! \n\nIPBus Address map:
--! \li 0x0000 - FIFO data
--! \li 0x0001 - FIFO fill level
--! \li 0x0010 - FIFO status/control: (Writing Bit-0 resets pointers, Reading bit-1 returns "prog_full" flag)
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--------------------------------------------------------------------------------
ENTITY eventBuffer IS
GENERIC(
g_EVENT_DATA_WIDTH : positive := 32;
g_IPBUS_WIDTH : positive := 32;
g_READ_COUNTER_WIDTH : positive := 13
);
PORT(
clk_4x_logic_i : IN std_logic;
data_strobe_i : IN std_logic; -- Indicates data to transfer
event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic;
--trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
rst_fifo_o : OUT std_logic; --! rst signal to first level fifos
buffer_full_o : OUT std_logic; --! Goes high when event buffer almost full
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
);
-- Declarations
END ENTITY eventBuffer ;
--
ARCHITECTURE rtl OF eventBuffer IS
signal s_rd_data_count : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_write_strobe : std_logic := '0';
signal s_rst_fifo, s_rst_fifo_ipb : std_logic := '0'; -- ! Take high to reset FIFO pointers.
signal s_fifo_prog_full : std_logic := '0'; -- ! Controlled by programmable-full flag of FIFO core
signal s_fifo_rd_en : std_logic := '0'; -- ! Take high to clock data out of FIFO
signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- ! Output from FIFO ( fall-through mode)
signal s_fifo_valid : std_logic := '1'; -- ! High when data in FIFO
signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
signal s_fifo_status_ipb , s_fifo_fill_level_d1 : std_logic_vector(ipbus_o.ipb_rdata'range) := (others => '0'); -- data registered onto IPBus clock
signal s_ack : std_logic := '0'; -- -- IPBus ACK signal
COMPONENT dummy_event_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
prog_full : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
-----------------------------------------------------------------------------
-- IPBus IO
-----------------------------------------------------------------------------
--! Generate IPBus ACK
ipbus_ack: process(ipbus_clk_i)
begin
if rising_edge(ipbus_clk_i) then
s_ack <= ipbus_i.ipb_strobe and not s_ack;
end if;
end process ipbus_ack;
ipbus_o.ipb_ack <= s_ack;
--! Generate FIFO read enable
--! take high for one cycle ( when ipb_strobe goes high but before ACK goes
--high to follow it
s_fifo_rd_en <= '1' when
ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '0' and ipbus_i.ipb_addr(1 downto 0) = "00" and s_ack = '0'
else '0';
ipbus_o.ipb_err <= '0';
--! Multiplex output data.
with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
s_fifo_dout when "00",
s_fifo_fill_level when "01",
s_fifo_status_ipb when "10",
(others => '1') when others;
ipbus_write: process (ipbus_clk_i)
begin -- process ipbus_write
if rising_edge(ipbus_clk_i) then
s_rst_fifo_ipb <= '0';
if ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_addr(1 downto 0) = "10" and ipbus_i.ipb_write = '1' then
s_rst_fifo_ipb <= '1';
end if;
-- Register data onto IPBus clock domain to ease timing closure.
s_fifo_status_ipb <= X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
s_fifo_fill_level <= X"0000" & "000" & s_rd_data_count;
end if;
end process ipbus_write;
rst_fifo_o <= s_rst_fifo_ipb;
s_rst_fifo <= s_rst_fifo_ipb or logic_reset_i;
-----------------------------------------------------------------------------
-- FIFO and fill-level calculation
-----------------------------------------------------------------------------
-- Instantiate a buffer to store the data. 64-bit on input, 32-bit on output.
--event_fifo : entity work.tlu_event_fifo
event_fifo : dummy_event_fifo
PORT MAP (
rst => s_rst_fifo,
wr_clk => clk_4x_logic_i,
rd_clk => ipbus_clk_i,
--din => event_data_i,
din => event_data_i,
wr_en => data_strobe_i,
rd_en => s_fifo_rd_en,
dout => s_fifo_dout,
full => s_fifo_full,
almost_full => s_fifo_almost_full,
empty => s_fifo_empty,
almost_empty => s_fifo_almost_empty,
rd_data_count => s_rd_data_count,
prog_full => s_fifo_prog_full
);
buffer_full_o <= s_fifo_prog_full;
END ARCHITECTURE rtl;
EUDETdummy/hdl/top_EUDET_dummy.vhd
View file @ c1d1ccb3
This diff is collapsed.
EUDETdummy/scripts/EUDETdummy.py
View file @ c1d1ccb3
......@@ -46,11 +46,11 @@ class EUDETdummy:
self.IC6=PCA9539PW(self.TLU_I2C, 0x74)
self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
self.IC6.setIOReg(0, 0x00)# 0= output, 1= input
self.IC6.setOutputs(0, 0xAA)# If output, set to XX
self.IC6.setOutputs(0, 0x88)# If output, set to XX
self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
self.IC6.setIOReg(1, 0x00)# 0= output, 1= input
self.IC6.setOutputs(1, 0xAA)# If output, set to XX
self.IC6.setOutputs(1, 0x88)# If output, set to XX
self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
self.IC7.setInvertReg(0, 0x00)# 0= normal, 1= inverted
......
EUDETdummy/scripts/EUDETdummyaddrmap.xml
View file @ c1d1ccb3
......@@ -32,14 +32,14 @@
<node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
</node>
<!-- Not sure about the FillLevelFlags register -->
<!--
<node id="eventBuffer" address="0x4000" description="Event buffer">
<node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
<node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
<node id="EventFifoCSR" address="0x2" permission="rw" description="" />
<node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
</node>
-->
<!-- Event formatter registers. Should be ok -->
<!--
<node id="Event_Formatter" address="0x5000" description="Event formatter configuration">
......
EUDETdummy/scripts/startEUDETdummy.py
View file @ c1d1ccb3
......@@ -66,6 +66,12 @@ if __name__ == "__main__":
logdata= True
EUDummy.start(logdata)
time.sleep(0.2)
nwords= int( EUDummy.getFifoLevel() )
print nwords
myarray= EUDummy.getFifoData(nwords)
for iel in myarray:
print iel >> 16
EUDummy.stop()
# prompt = MyPrompt()
# prompt.prompt = '>> '
......
TLU_v1e/constraints/TLU_enclustra_v1e.xdc
View file @ c1d1ccb3
......@@ -105,5 +105,18 @@ set_property PACKAGE_PIN G3 [get_ports {dut_clk_i[3]}]
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -max 0.400 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
# Input timing ignored
create_clock -name virtualclk -period 10.000 -waveform {0.000 5.00}
set_clock_groups -name async_clk -asynchronous -group [get_clocks -include_generated_clocks s_clk320] -group {virtualclk}
set input_list "[get_ports {threshold_discr_n_i[*]}] [get_ports {threshold_discr_p_i[*]}]"
set_input_delay -clock virtualclk -rise -2 $input_list
set_input_delay -clock virtualclk -fall 2 $input_list
set_input_delay -clock virtualclk -rise -2 $input_list -clock_fall -add_delay
set_input_delay -clock virtualclk -fall 2 $input_list -clock_fall -add_delay
#set_input_delay 1.6ns -clock [get_clocks s_clk320][get_ports threshold_discr_p_i[2]]
#set_false_path -from [get_ports threshold_discr_p_i[2]] -to [get_pins I5/trigger_input_loop[2]/thresholdDeserializer/ISERDES2_Delayed/DDLY]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
TLU_v1e/hdl/dut/DUTInterface_AIDA_rtl.vhd
View file @ c1d1ccb3
......@@ -39,7 +39,7 @@ ENTITY DUTInterface_AIDA IS
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. DUTs report busy unless ignore_shutter_veto flag is set high
ignore_shutter_veto_i : in std_logic;
ignore_dut_busy_i : in std_logic;
dut_mask_i : in std_logic; --! Set high if DUT is active.
--dut_mask_i : in std_logic; --! Set high if DUT is active. Moved one level up
busy_o : OUT std_logic; --! goes high when DUT is busy or vetoed by shutter
-- Signals to/from DUT
......@@ -138,11 +138,12 @@ BEGIN
--busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
-- ((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) );
busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
( (dut_busy_i and DUT_mask_i ) );
--busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or ( (dut_busy_i and DUT_mask_i ) );
busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or ( dut_busy_i );
dut_clk_o <= s_dut_clk ;
dut_trigger_o <= DUT_mask_i and s_trigger_out;
--dut_trigger_o <= DUT_mask_i and s_trigger_out;
dut_trigger_o <= s_trigger_out;
end if;
end process register_signals;
......
TLU_v1e/hdl/dut/DUTInterface_EUDET_rtl.vhd
View file @ c1d1ccb3
......@@ -132,9 +132,13 @@ end process;
elsif (state = WAIT_FOR_BUSY_HIGH ) then
-- only clock out bottom 15 bits of data.
-- (replace fixed width with a mask at some stage ?)
trig_shift_reg <= "00000000000000000" & trigger_counter_copy(14 downto 0);
trig_shift_reg <= "00000000000000000" & trigger_counter_copy(14 downto 0);
serial_trig_data <= '0';
end if;
if ( state = IDLE ) and ( trigger_i = '1') then
trigger_counter_copy <= trigger_counter_i; -- register the trigger number to shift it out
end if;
end if;
......@@ -151,7 +155,7 @@ end process;
when IDLE =>
if ( trigger_i = '1') then -- respond to trigger going high
next_state <= WAIT_FOR_BUSY_HIGH; -- wait for DUT to respond to busy
trigger_counter_copy <= trigger_counter_i; -- register the trigger number to shift it out
--trigger_counter_copy <= trigger_counter_i; -- register the trigger number to shift it out
elsif ( (dut_clk_r2 = '1') and (enable_dut_veto_i = '1') ) then -- If DUT asserts DUT_CLK_I then veto triggers
next_state <= DUT_INITIATED_VETO;
......
TLU_v1e/hdl/dut/DUTInterfaces_rtl.vhd
View file @ c1d1ccb3
......@@ -291,7 +291,7 @@ BEGIN
shutter_to_dut_i => shutter_to_dut_i ,
ignore_shutter_veto_i => s_IgnoreShutterVeto ,
ignore_dut_busy_i => s_DUT_ignore_busy(dut),
dut_mask_i => s_DUT_mask(dut),
--dut_mask_i => s_DUT_mask(dut),
busy_o => s_dut_veto_aida(dut),
-- Signals to/from DUT
......@@ -346,8 +346,8 @@ BEGIN
p_signal_mux: process (clk_4x_logic_i ) is
begin -- process p_signal_mux
if rising_edge(clk_4x_logic_i) then
s_trigger_to_dut <= ( s_trigger_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_trigger_to_dut_aida and s_DUT_aida_eudet_mode) ;
s_dut_veto <= ( s_dut_veto_eudet and (not s_DUT_aida_eudet_mode)) or ( s_dut_veto_aida and s_DUT_aida_eudet_mode) ;
s_trigger_to_dut <= (( s_trigger_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_trigger_to_dut_aida and s_DUT_aida_eudet_mode)) and s_DUT_mask ; -- move DutMask one level up to affect both AIDA and EUDET modes
s_dut_veto <= (( s_dut_veto_eudet and (not s_DUT_aida_eudet_mode)) or ( s_dut_veto_aida and s_DUT_aida_eudet_mode)) and s_DUT_mask ; -- move DutMask one level up to affect both AIDA and EUDET modes
s_shutter_to_dut <= ( s_shutter_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_shutter_to_dut_aida and s_DUT_aida_eudet_mode) ;
s_reset_or_clk_to_dut <= ( s_reset_or_clk_to_dut_aida and s_DUT_aida_eudet_mode) ; --! reset_or_clk line stays low if in EUDET mode
......
TLU_v1e/hdl/top_enclustra_tlu_v1e.vhd
View file @ c1d1ccb3
......@@ -23,7 +23,7 @@ use work.ipbus.ALL;
entity top_tlu_v1e is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000008"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"1e00000a"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......
TLU_v1e/scripts/AIDA_testPower.py 0 → 100644
View file @ c1d1ccb3
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tlu")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "CHECK REG= ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
#
# #######################################
enableCore= False #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
#DAC CONFIGURATION BEGIN
if (False):
zeDAC1=AD5665R(master_I2C, 0x1C)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
if (True):
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x76)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(0, 0x00)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(1, 0x00)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x77)
#BANK 0
IC7.setInvertReg(0, 0x00)# 0= normal
IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(0, 0x00)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(1, 0x00)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
TLU_v1e/scripts/AIDA_testScript.py
View file @ c1d1ccb3
......@@ -96,7 +96,7 @@ zeClock.checkDesignID()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
#zeClock.writeConfiguration(clkRegList)######
zeClock.writeConfiguration(clkRegList)######
zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
......
TLU_v1e/scripts/TLU_v1e.py
View file @ c1d1ccb3
......@@ -12,6 +12,9 @@ from I2CuHal import I2CCore
from si5345 import si5345 # Library for clock chip
from AD5665R import AD5665R # Library for DAC
from PCA9539PW import PCA9539PW # Library for serial line expander
from I2CDISP import CFA632 #Library for display
from I2CDISP import LCD09052 #Library for display
from TLU_powermodule import PWRLED
class TLU:
"""docstring for TLU"""
......@@ -101,6 +104,44 @@ class TLU:
self.IC7.setIOReg(1, 0x00)# 0= output, 1= input
self.IC7.setOutputs(1, 0xB0)# If output, set to XX
#Instantiate Display
#self.DISP=CFA632(self.TLU_I2C, 0x2A) #
self.DISP=LCD09052(self.TLU_I2C, 0x3A) #
#Instantiate Power/Led Module
dac_addr_module= int(parsed_cfg.get(section_name, "I2C_DACModule_Addr"), 16)
exp1_addr= int(parsed_cfg.get(section_name, "I2C_EXP1Module_Addr"), 16)
exp2_addr= int(parsed_cfg.get(section_name, "I2C_EXP2Module_Addr"), 16)
self.pwdled= PWRLED(self.TLU_I2C, dac_addr_module, exp1_addr, exp2_addr)
self.pwdled.setVch(0, 1, True)
self.pwdled.setVch(1, 0.9, True)
self.pwdled.setVch(2, 0.8, True)
self.pwdled.setVch(3, 0.1, True)
self.pwdled.setIndicatorRGB(1, [0, 0, 1])
self.pwdled.setIndicatorRGB(2, [0, 0, 1])
self.pwdled.setIndicatorRGB(3, [0, 0, 1])
self.pwdled.setIndicatorRGB(4, [0, 0, 1])
self.pwdled.setIndicatorRGB(5, [0, 0, 1])
self.pwdled.setIndicatorRGB(6, [0, 0, 1])
self.pwdled.setIndicatorRGB(7, [0, 0, 1])
self.pwdled.setIndicatorRGB(8, [0, 0, 1])
self.pwdled.setIndicatorRGB(9, [0, 0, 1])
self.pwdled.setIndicatorRGB(10, [0, 0, 1])
self.pwdled.setIndicatorRGB(11, [0, 0, 1])
self.pwdled.allGreen()
#time.sleep(0.5)
#self.pwdled.allRed()
#time.sleep(0.5)
self.pwdled.allBlue()
#time.sleep(0.5)
self.pwdled.allBlack()
#self.pwdled.allWhite()
#time.sleep(0.5)
#self.pwdled.kitt()
self.pwdled.kitt()
self.pwdled.allBlack()
##################################################################################################################################
##################################################################################################################################
......
TLU_v1e/scripts/localConf.conf
View file @ c1d1ccb3
......@@ -45,10 +45,10 @@ DACThreshold4 = -0.12
DACThreshold5 = -0.12
# Define which DUTs are ON
DutMask = 0
DUTMask = 1
# Define mode of DUT (00 EUDET, 11 AIDA)
DUTMaskMode= 0xFF
DUTMaskMode= 0xFC
# Allow asynchronous veto
DUTMaskModeModifier= 0x0
......
TLU_v1e/scripts/localIni.ini
View file @ c1d1ccb3
......@@ -25,6 +25,13 @@ I2C_ID_Addr = 0x50
I2C_EXP1_Addr = 0x74
#I2C address of 2st expander PCA9539PW
I2C_EXP2_Addr = 0x75
#I2C address of AD5665R on powermodule
I2C_DACModule_Addr = 0x1C
#I2C address of 1st expander PCA9539PW on powermodule
I2C_EXP1Module_Addr = 0x76
#I2C address of 2nd expander PCA9539PW on powermodule
I2C_EXP2Module_Addr = 0x77
##CONFCLOCK 0= skip clock configuration, 1= configure si5345
CONFCLOCK= 0
......
TLU_v1e/scripts/startTLU_v1e.py
View file @ c1d1ccb3
......@@ -60,6 +60,17 @@ class MyPrompt(cmd.Cmd):
print "\t Could not retrieve CONF data."
return
def do_i2c(self, args):
arglist = args.split()
if len(arglist) == 0:
print "\tno command specified"
else:
i2ccmd= arglist[0]
results = list(map(int, arglist))
TLU.DISP.writeSomething(results)
print "Sending i2c command to display"
return
def do_id(self, args):
"""Interrogates the TLU and prints it unique ID on screen"""
TLU.getSN()
......@@ -229,7 +240,7 @@ if __name__ == "__main__":
###TLU.stop(False, False)
# Start interactive prompt
print "=+=================================================================="
print "===================================================================="
print "==========================TLU TEST CONSOLE=========================="
print "+==================================================================="
print "===================================================================="
prompt.cmdloop("Type 'help' for a list of commands.")
bitFiles/dummyflash.mcs 0 → 100644
View file @ c1d1ccb3
This diff is collapsed.
bitFiles/v1e_memoryConf_0x1e00000a.mcs 0 → 100644
View file @ c1d1ccb3
This diff is collapsed.
packages/AD5665R.py
View file @ c1d1ccb3
......@@ -20,7 +20,8 @@ class AD5665R:
cmdDAC= [0x38,0x00,0x00]
self.i2c.write( self.slaveaddr, cmdDAC, mystop)
if verbose:
print "DAC int ref:", intRef
print " AD5665R"
print "\tDAC int ref:", intRef
def writeDAC(self, dacCode, channel, verbose=False):
......
packages/I2CDISP.py 0 → 100644
View file @ c1d1ccb3
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class CFA632:
#Class to configure the CFA632 display
def __init__(self, i2c, slaveaddr=0x2A):
self.i2c = i2c
self.slaveaddr = slaveaddr
def test(self):
print "Testing the display"
return
def writeSomething(self, i2ccmd):
mystop= True
print "Write random stuff"
print i2ccmd
#myaddr= [int(i2ccmd)]
self.i2c.write( self.slaveaddr, i2ccmd, mystop)
return
class LCD09052:
#Class to configure the LCD09052 display
def __init__(self, i2c, slaveaddr=0x3A):
self.i2c = i2c
self.slaveaddr = slaveaddr
def test(self):
print "Testing the display"
return
def writeSomething(self, i2ccmd):
mystop= True
print "Write random stuff"
print i2ccmd
#myaddr= [int(i2ccmd)]
self.i2c.write( self.slaveaddr, i2ccmd, mystop)
return
packages/I2CuHal.py
View file @ c1d1ccb3
......@@ -77,8 +77,8 @@ class I2CCore:
self.target.dispatch()
#Write pre-scale register
#prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
#prescale = int(self.wishboneclock / (5.0 * self.i2cclock))
prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
#prescale = 0x2710 #FOR NOW HARDWIRED, TO BE MODIFIED
self.prescale_low.write(prescale & 0xff)
self.prescale_high.write((prescale & 0xff00) >> 8)
#Enable core
......
packages/NHDC0220Biz.py 0 → 100644
View file @ c1d1ccb3
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class NHDC0220Biz:
#Class to configure the EEPROM
def __init__(self, i2c, slaveaddr=0x3c):
self.i2c = i2c
self.slaveaddr = 0x2a#slaveaddr
def test(self):
print "Testing the display"
return
def writeSomething(self):
mystop= True
print "Write random stuff"
myaddr= [0x08, 0x38]
self.i2c.write( self.slaveaddr, myaddr, mystop)
return
packages/TLU_powermodule.py 0 → 100644
View file @ c1d1ccb3
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment