@@ -27,9 +27,13 @@ Not all parameters are needed; if one of the parameters is not present in the fi
\item[I2C\_CLK\_Addr]\verb|[positive int, 0x68]|\gls{i2c} address of Si5345 clock generator installed on the \gls{tlu}.
\item[I2C\_DAC1\_Addr]\verb|[positive int, 0x13]|\gls{i2c} address of \gls{dac} installed on the \gls{tlu}. The \gls{dac} is used to configure the threshold of the trigger inputs.
\item[I2C\_DAC2\_Addr]\verb|[positive int, 0x1F]|\gls{i2c} address of \gls{dac} installed on the \gls{tlu}. The \gls{dac} is used to configure the threshold of the trigger inputs.
\item[I2C\_ID\_Addr]\verb|[positive int, 0x50]|\gls{i2c} address the unique ID \gls{eeprom} installed on the \gls{tlu}. The chip is used to provide a unique identifier to each kit.
\item[I2C\_EXP1\_Addr]\verb|[positive int, 0x74]|\gls{i2c} address the bus expander used to select the direction of the \gls{hdmi} pins on the board.
\item[I2C\_EXP2\_Addr]\verb|[positive int, 0x75]|\gls{i2c} address the bus expander used to select the direction of the \gls{hdmi} pins on the board.
\item[I2C\_ID\_Addr]\verb|[positive int, 0x50]|\gls{i2c} address of the unique ID \gls{eeprom} installed on the \gls{tlu}. The chip is used to provide a unique identifier to each kit.
\item[I2C\_EXP1\_Addr]\verb|[positive int, 0x74]|\gls{i2c} address of the bus expander used to select the direction of the \gls{hdmi} pins on the board.
\item[I2C\_EXP2\_Addr]\verb|[positive int, 0x75]|\gls{i2c} address of the bus expander used to select the direction of the \gls{hdmi} pins on the board.
\item[I2C\_DACModule\_Addr]\verb|[positive int, 0x1C]|\gls{i2c} address of the \gls{dac} installed on the power module and used to control the \gls{pmt} outputs.
\item[PMT\_vCtrlMax]\verb|[float, 1]| value, in volts, of the maximum control voltage for the \gls{pmt}s. For EUDET telescopes this should normally be left to 1~V. If the \gls{tlu} is going to be used with different \gls{pmt}s, then a new value can be used but the hardware must be tweaked accordingly by changing the voltagi divider on the power module.
\item[I2C\_EXP1Module\_Addr]\verb|[positive int, 0x76]|\gls{i2c} address of the first expander used to control the indicators on the power module.
\item[I2C\_EXP2Module\_Addr]\verb|[positive int, 0x77]|\gls{i2c} address of the second expander used to control the indicators on the power module.
\item[intRefOn]\verb|[boolean, false]| If true, the \gls{dac}s installed on the \gls{tlu} will use their internal voltage reference rather than the one provide externally.
\item[VRefInt]\verb|[float, 2.5]| Value in volts for the internal reference voltage of the \gls{dac}s. The voltage is chosen by the chip manufacturer. This is only used if \verb|intRefOn= true|.
\item[VRefExt]\verb|[float, 1.3]| Value in volts for the external reference voltage of the \gls{dac}s. The voltage is determined by a circuit on the \gls{tlu} and the value of this parameter must reflect such voltage. This is only used if \verb|intRefOn= false|.
@@ -8,7 +8,7 @@ The board must be plugged onto a \gls{fmc} carrier board with an \gls{fpga} in o
\subsubsection{Device under test}\label{ch:dut}
The \gls{dut}s are connected to the \gls{tlu} using standard size \gls{hdmi} connectors\footnote{In the miniTLU hardware these were mini \gls{hdmi} connectors.}.\\
In the current version of the hardware, up to four \gls{dut}s can be connected to the board. In this document the connectors will be referred to as \verb|HDMI1|, \verb|HDMI2|, \verb|HDMI3| and \verb|HDMI4|.\\
The connectors expect 3.3~V \gls{lvds} signals and are bi-directional, i.e. any differential pair can be configured to be an output (signal from the TLU to the DUT) or an input (signals from the DUT to the TLU) by using half-duplex line transceivers. Figure~\ref{fig:LVDSTransceiver} illustrates how the differential pairs are connected to the transceivers.
The connectors operate with 3.3~V \gls{lvds} signals and are bi-directional, i.e. any differential pair can be configured to be an output (signal from the TLU to the DUT) or an input (signals from the DUT to the TLU) by using half-duplex line transceivers. Figure~\ref{fig:LVDSTransceiver} illustrates how the differential pairs are connected to the transceivers.
\begin{alertinfo}{Note}
The input part of the transceiver is configured to be always on. This means that signals going \emph{into} the \gls{tlu} are always routed to the logic (\gls{fpga}). By contrast, the output transceivers have to be enabled and are off by default: signal sent from the logic to the \gls{dut}s cannot reach the devices unless the corresponding enable signal is active.
\end{alertinfo}
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@@ -140,8 +140,12 @@ Is the \gls{tlu} is controlled using EUDAQ, the \gls{dac} can be steered by mean
Three green \gls{led} on the front panel are used to indicate the presence of power (+12 V) and the correct functioning of the +5 V and -5 V voltage regulators. Further indicators are assigned to the \gls{hdmi} and trigger inputs to provide information on their status. These indicators are \gls{rgb}. At the moment there is not defined scheme to assign a meaning to each colour.\\
The LEMO connectors used to power the \gls{pmt}s are wired according to the following scheme, inherited from what already in use in beam telescopes (FIX THIS):
\begin{enumerate}
\itemVcc
\itemVcc
\itemVcc
\itemVcc
\itemPOWER: +12~V
\itemnot connected
\itemCONTROL, voltage signal from 0 to +1~V
\itemGND
\end{enumerate}
\begin{alertinfo}{\gls{tlu} Control voltage on modified units}
Some users requested the possibility to use different types of \gls{pmt}s. To enable this, a few power modules have been modified to provide +5~V (instead of +12~V) and to have a maximum control voltage of 1.1~V (instead of 1~V).\\
The modified units are clearly labelled and use different style of \gls{pmt} connectors, so that confusion should be minimized.
This manual describes the AIDA \gls{tlu} designed for the \href{http://aida2020.web.cern.ch/}{AIDA-2020 project} by David Cussans\footnote{University of Bristol, Particle Physics group} and Paolo Baesso\footnote{University of Bristol, Particle Physics group}.\\
Congratulations on acquiring an AIDA2020 \gls{tlu}. We hope that the unit will help you to collect lots of useful data during your hardware tests.\\
This manual describes the \gls{tlu} designed for the \href{http://aida2020.web.cern.ch/}{AIDA-2020 project} by David Cussans\footnote{University of Bristol, Particle Physics group} and Paolo Baesso\footnote{University of Bristol, Particle Physics group}.\\
The unit is designed to be used in High Energy Physics beam-tests and provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope.\\
The current version of the hardware is an evolution of the \href{https://twiki.cern.ch/twiki/bin/view/MimosaTelescope/TLU}{EUDET-TLU} and the \href{https://www.ohwr.org/projects/fmc-mtlu/wiki}{miniTLU} and is shipped in a metal enclosure that includes an \gls{fpga} board, the \gls{tlu}\gls{pcb} and an additional power module: the \gls{fpga} is responsible for all the logic functions of the unit, while the \gls{pcb} contains the clock chip, discriminator and interface blocks needed to communicate with other devices. The power module contains programmable \gls{dac} to power photomultipliers and \gls{led} indicators.\\
The current version of the \gls{pcb} is \brd and is designed to plug onto a carrier \gls{fpga} board like any other \gls{fmc} mezzanine board, although its form factor does not comply with the ANSI-VITA-57-1 standard.\\
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@@ -78,7 +79,7 @@ Once these prerequisites are met, the procedure is as follows:
\item Open the Vivado tools and select "Hardware manager", figure\ref{fig:hw_open}
\item Select open target
\item Identify the cable corresponding to the unit to be written and click open. The cable identifier is generally written on the back panel of the \gls{tlu}. If only one programming cable is connected to the computer, it is possible to use the auto-connect option.\\
Once done, the Vivado window will be populated, showing the cable and the \gls{fpga} attached to it.
Once done, the Vivado window will be populated, showing the cable and the \gls{fpga} attached to it.
\item Right click on the \gls{fpga} (typically xc7...) and select \verb"Program device" (see figure~\ref{fig:hw_addMemory})
\item Locate the \verb".bit" file to be used and program
\end{enumerate}
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@@ -92,7 +93,7 @@ Once these prerequisites are met, the procedure is as follows:
The procedure to write a permanent program in the \gls{eeprom} is very similar to the one followed to write a bit stream file, with the exception that the user should select \verb"Add configuration memory device" in the options, as shown in figure~\ref{fig:hw_addMemory}.
This will open a new window, shown in figure~\ref{fig:hw_eeprom}, from which it is possible to indicate the file to use (with extension \verb".mcr").
