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AIDA-2020 TLU - Software
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\chapter{DUT signals}\label{ch:DUTsignals}
In the old firmware the clock signals (\verb|dut_clk_n_o, dut_clk_p_o|) were configured as input/output. The new hardware has the lines separated so \verb|dut_clk_p_i| is the input vector and \verb|dut_clk_p_o| the output one.\\
\ No newline at end of file
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\documentclass[10pt,twoside, fleqn]{memoir}
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\makeatother
\author{Paolo Baesso}
\title{AIDA Trigger logic unit (TLU)}
\date{\today}
%\date{23 February 2015}
\loadglsentries{O:/LatexFiles/Glossary/myGlossary.tex}
%\input{O:/LatexFiles/Glossary/myGlossary.tex}
%\makeglossaries
%%% BEGIN DOCUMENT
\makeindex
\begin{document}
\let\cleardoublepage\clearpage
\maketitle
\frontmatter
\null\vfill
\begin{flushleft}
\textit{Board fmc\_tlu\_v1d.}\newline
\newline
Paolo Baesso - 2016\newline paolo.baesso@bristol.ac.uk
\bigskip
\end{flushleft}
\let\cleardoublepage\clearpage
\newpage
\tableofcontents
\mainmatter
\sloppy
\newenvironment{SpecialPar}
{\begin{shaded}\noindent}
{\end{shaded}}
%%% INCLUDE CHAPTERS
\def\brd{FMC\_TLU\_v1d }
%\include{ch_Introduction}
\include{ch_TLU_Preparation}
\include{ch_TLU_Hardware}
\include{ch_TLU_clock}
\include{DUT_signals}
\include{ch_TLU_triggerInputs}
\include{ch_EventBuffer}
\include{ch_TLU_Appendix}
\include{ch_TLU_Functions}
\include{ch_TLU_IPBusRegs}
%\begin{figure}[h]
% \centering
% \includegraphics[width=1.62\textwidth, angle=90]{./Images/protoDUNE_fmc_sfp_to_slave_v0-7.pdf}
% \caption{Sketch of the connections and signal names between the elements of the board.}\label{fig:Connections}
%\end{figure}
%\section{Schematic}
%\includepdf[pages={1-},scale=0.99, landscape=true]{./Images/PC053A.pdf}
%%\includepdf[pages={1-},scale=0.99, landscape=true]{./Images/PC053A_TOPLEVEL.pdf}
%%% GLOSSARY
\printglossaries
%\printglossary[type=\acronymtype]
\printglossary[type=\acronymtype,title=Abbreviations]
%%% BIBLIOGRAPHY
%\bibliographystyle{unsrt}
%\bibliography{./../../Bibliography/myBibliography}
\end{document}
\ No newline at end of file
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\section{Event buffer}\label{ch:eventBuffer}
The event buffer IPBus slave has four registers.
Writing to \verb|EventFifoCSR| will reset the \gls{fifo}. Reading from either of the register will put their data on the IPBus data line.\\
Reading from \verb|EventFifoCSR| returns the following:
\begin{itemize}
\item bit 0: \gls{fifo} empty flag
\item bit 1: \gls{fifo} almost empty flag
\item bit 2: \gls{fifo} almost full flag
\item bit 3: \gls{fifo} full flag
\item bit 4: \gls{fifo} programmable full flag
\item other bits: 0
\end{itemize}
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\chapter{Appendix}\label{ch:appendix}
\includepdf[link,pages={1}]{./Docs/PM3TopView.pdf}
\includepdf[link,pages=-, angle=90]{./Docs/Connections.pdf}
\ No newline at end of file
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\chapter{Functions}\label{ch:functions}
The following is a list of files containing the code for the \gls{tlu}:
\begin{itemize}
\item \verb|./eudaq2/user/eudet/misc/fmctlu_runcontrol.ini|:\newline initialization file for the hardware. The location of the file can be passed to the EUDAQ code in the \gls{gui}.
\item \verb|./eudaq2/user/eudet/misc/fmctlu_runcontrol.conf|:\newline configuration file. It contains all the parameters to be loaded in the \gls{tlu} at the beginning of the run. If this file is not found, EUDAQ will use a list of default settings. The location of the file (and its name) can be passed to the EUDAQ code in the \gls{gui}.
\item \verb|./eudaq2/user/eudet/misc/fmctlu_connection.xml|:\newline define the IP address and address map of the \gls{tlu}. The one listed is the default location for the file. A different location can be specified with the \verb|ConnectionFile| option in the \emph{conf} file for the \gls{tlu}.
\item \verb|./eudaq2/user/eudet/misc/fmctlu_address.xml|:\newline address map for the \gls{tlu}. The location of the file is specified in the \verb|fmctlu_connection.xml| file.
\item \verb|./eudaq2/user/eudet/misc/fmctlu_clock_config.txt|:\newline configuration for the Si5345 clock chip. In order for the hardware to work a configuration file must be present. Those listed are the default name and location for the file; a different file can be specified with the \verb|CLOCK_CFG_FILE| option in the \emph{conf} file for the \gls{tlu}.
\item \verb|./eudaq2/user/eudet/module/src/FMCTLU_Producer.cc|:\newline eudaq producer for the \gls{tlu}. Contains the methods to initialize, configure, start, stop the \gls{tlu} producer.
\item \verb|./eudaq2/user/eudet/hardware/src/FmctluController.cc|:\newline Contains the definition of the hardware class for the \gls{tlu} and the methods to set and read from its hardware, such as clock chip, DAC, etc. This lever is abstract with respect to the actual hardware, so that if a future version of the board uses different components it should be possible to re-use this code.
\item \verb|./eudaq2/user/eudet/hardware/include/FmctluController.hh|:\newline Headers for the controller.
\item \verb|./eudaq2/user/eudet/hardware/src/FmctluController.cxx|:\newline Executable for the controller.
\item \verb|./eudaq2/user/eudet/hardware/src/FmctluHardware.cc|:\newline This is the code that deals with the actual hardware on the \gls{tlu}, and contains specific instructions for the chips mounted in the current version. It contains several classes for the ADC, the clock chip, the I/O expanders etc.
\item \verb|./eudaq2/user/eudet/hardware/include/FmctluHardware.hh|:\newline Header for the hardware.
\item \verb|./eudaq2/user/eudet/hardware/src/FmctluI2c.cc|:\newline core functions used to read and write from \gls{i2c} compatible slaves.
\item \verb|./eudaq2/user/eudet/hardware/include/FmctluI2c.hh|:\newline Headers for the \gls{i2c} core.
\end{itemize}
\section{Functions}
\begin{description}
\item[enableClkLEMO] Enable or disable the output clock to the differential LEMO connector.
\item[enableHDMI] Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.\\ In the configuration file use \verb|HDMIx_on = 0| to disable a channel and \verb|HDMI1_on = 1| to enable it (x can be 1, 2, 3, 4).\\
NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.\\
NOTE: Clock source must be defined separately using SetDutClkSrc (DUTClkSrc in python script).\\
NOTE: this is called \verb|DUTOutputs| on the python scripts.
\item[GetFW] dsds
\item[getSN] dsd
\item[I2C\_enable] dsd
\item[InitializeClkChip]
\item[InitializeDAC]
\item[InitializeIOexp]
\item[InitializeI2C]
\item[PopFrontEvent]
\item[ReadRRegister]
\item[ReceiveEvents]
\item[ResetEventsBuffer]
\item[SetDutClkSrc] Set the clock source for a specific \gls{hdmi} connector. The source can be set to 0 (no clock), 1 (Si5345) or 2 (FPGA). In the configuration file use \verb|HDMIx_on = N| to select the source (x can be 1, 2, 3, 4, N is the clock source).\\
NOTE: this is called \verb|DUTClkSrc| on python scripts.
\item[SetPulseStretchPk] Takes a vector of six numbers, packs them (5-bits each) and sends them to the PulseStretch register.
\item[SetThresholdValue]
\item[setTrgPattern] Writes two 32-bit words to define the trigger pattern for the inputs. See section~\ref{ch:triggerinputs} for details.
\item[SetWRegister]
\item[SetUhalLogLevel]
\end{description}
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\chapter{Preparation}\label{ch:preparation}
Before powering the \gls{tlu} it is necessary to follow a few steps to ensure the board and the \gls{fpga} work correctly.\\
The \brd is designed to plug onto a carrier \gls{fpga} board like any other \gls{fmc} mezzanine board, although its form factor does not comply with the ANSI-VITA-57-1 standard.\\
The firmware developed at University of Bristol is targeted to work with the Enclustra AX3 board, which must be plugged onto a PM3 base, also produced by \href{http://www.enclustra.com/en/home/}{Enclustra}. The firmware is written on the \gls{fpga} using a \gls{jtag} interface. Typically a breakout board will be required to connect the Xilinx programming cable to the Enclustra PM3.\\
Currently, it is recommended to use the following:
\begin{itemize}
\item MA-PM3-W-R5: Mars PM3 base board
\item MA-AX3-35-1I-D8-R3: Marx AX3 module (hosts a Xilinx XC7A35T-1CSG324I )
\item MA-PM3-ACC-BASE: Accessory kit, including a \gls{jtag} breakout board to connect Xilinx programming cables. Also includes a 12~V power supply to power the PM3.
\end{itemize}
\section{I/O voltage setting}
The I/O pins of the PM3 can be configured to operate at 2.5~V or 3.3~V; the factory default is 2.5~V but the \brd requires 3.3~V logic. The user should make sure to select the appropriate voltage by operating on DIP-switch CFG-A/S1200 (pin 1 set to ON).\\For reference, a top view of the board is provided in the appendix at page~\pageref{ch:appendix}.\\
\begin{alertinfo}{Warning}
Please double check the PM3 board manual for the correct way to change the I/O voltage setting. Enclustra has been changing their hardware recently.
\end{alertinfo}
\section{Xilinx programming cable}
The \gls{jtag} pins on the PM3 are located on the header J800 (20-way, 2.54~mm pitch). The breakout board provided by Enclustra sits on top of the header and connects the pins to a 14-way Molex milli-grid header so that it is possible to plug the Xiling programming cable directly onto it. However, when the \brd is mounted on a base plate as shown in figure~\ref{fig:TLUplate}, the breakout board has to be detached from the PM3 because it interferes with the mounting screws.\\
The connection between J800 and the breakout can be achieved by using two standard 20-way \gls{idc} cables as shown in figure~\ref{fig:XilinxCable}.
\begin{figure}[h]
\centering
\includegraphics[width=.50\textwidth]{./Images/TLU_plate.jpg}
\caption{\brd and PM3 mounted on a base plate: in this configuration it is not possible to install the breakout board on the PM3 because the mountings screws are in the way.}\label{fig:TLUplate}
\end{figure}
\begin{figure}
\centering
\includegraphics[width=.80\textwidth]{./Images/XilinxCable.jpg}
\caption{Connecting the Xilinx programming cable to the PM3 in an ugly (but effective) way.}\label{fig:XilinxCable}
\end{figure}
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\chapter{Clock}\label{ch:clock}
The \gls{tlu} can use various sources to produce a stable 40~MHz clock\footnote{For some applications a 50~MHz clock will be required instead}. A \gls{lvpecl} crystal provides the reference 50~MHz clock for a Si5345A jitter attenuator. The Si5345A can accept up to four clock sources and use them to generate the required output clocks.\\
In the \gls{tlu} the possible sources are: pair of external pins LK4\_9 and LK3\_9, differential LEMO connector LM1\_9, \gls{fpga} pins (\verb|CLK_FROM_FPGA|) and one of the four \gls{hdmi} connectors (\verb|HDMI_DUT_4|).\\
The low-jitter clock generated by the Si5345A can be distributed to up to ten recipients. In the \gls{tlu} these are: the four \gls{dut}s via \gls{hdmi} connectors, the differential LEMO cable, the \gls{fpga}, connector J1 as a differential pair (pins 4 and 6) and as a single ended signal (pin 8), two test resistors R24\_9 and R54\_9.\\
The \gls{dut}s can receive the clock either from the Si5435A or directly from the \gls{fpga}: when provided by the clock generator, the signal name is \verb|CLK\_TO\_DUT| and is enabled by signal \verb|ENABLE_CLK_TO_DUT|; when the signal is provided directly from the \gls{fpga} the line used is \verb|DUT_CLK_FROM_FPGA| and is enabled by \verb|ENABLE_DUT_CLK_FROM_FPGA|.\\
The firmware uses the clock generated by the Si5345A except for the block \verb|enclustra_ax3_pm3_infra| which relies on a crystal mounted on the Enclustra board to provide the IPBus functionalities (in this way, at power up the board can communicate via IPBus even if the Si5345A is not configured).
\section{Input selection}
The Si5345 has four inputs that can be selected to provide the clock alignment; the selection can be automatic or user-defined.
\begin{table}[]
\centering
\caption{Si5345 Input Selection Configuration.}
\label{tab:si5345inputs}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Register Name} & \textbf{Hex Address {[}Bit Field{]}} & \textbf{Function} \\ \hline
CLK\_SWITCH\_MODE & 0x0536{[}1:0{]} & \begin{tabular}[c]{@{}l@{}}Selects manual or automatic switching modes.\\ Automatic mode can be revertive or non-revertive.\\ Selections are the following:\\00 Manual\\01 Automatic non-revertive\\02 Automatic revertive\\03 Reserved\end{tabular} \\ \hline
IN\_SEL\_REGCTRL & 0x052A {[}0{]} & \begin{tabular}[c]{@{}l@{}}0 for pin controlled clock selection\\ 1 for register controlled clock selection\end{tabular} \\ \hline
IN\_SEL & 0x052A {[}2:1{]} & \begin{tabular}[c]{@{}l@{}}0 for IN0\\ 1 for IN1\\ 2 for IN2\\ 3 for IN3 (or FB\_IN)\end{tabular} \\ \hline
\end{tabular}
\end{table}
\section{Logic clocks registers}\label{ch:logicClock}
LogicClocksCSR: in the new TLU the selection of the clock source is done by programming the Si5345. As a consequence, there is no reason to write to this register. Reading it back returns the status of the PLL on bit 0, so this should read 0x1.
\ No newline at end of file
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--=============================================================================
--! @file DUTInterface_AIDA_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterface_AIDA.rtl
--
--------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--! @brief "AIDA Style" Interface to a Device Under Test (DUT) connector.
--! factorized from original DUTInterfaces_rtl.vhd firmware.
--!
--! @author David Cussans , David.Cussans@bristol.ac.uk
--!
--! @date 1/Sept/2015
--!
--! @version v0.1
--!
--! @details
--
ENTITY DUTInterface_AIDA IS
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_4x_logic_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; --! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
trigger_i : IN std_logic; --! goes high when trigger logic issues a trigger
reset_or_clk_to_dut_i : IN std_logic; --! Synchronization signal. Passed to DUT pins
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. DUTs report busy unless ignore_shutter_veto flag is set high
ignore_shutter_veto_i : in std_logic;
ignore_dut_busy_i : in std_logic;
dut_mask_i : in std_logic; --! Set high if DUT is active.
busy_o : OUT std_logic; --! goes high when DUT is busy or vetoed by shutter
-- Signals to/from DUT
dut_busy_i : IN std_logic; --! BUSY input from DUTs
dut_clk_o : OUT std_logic; --! clocks trigger data when in EUDET mode
dut_reset_or_clk_o : OUT std_logic; --! Either reset line or trigger
dut_shutter_o : OUT std_logic; --! Shutter output. Output 0 (RJ45) has no shutter signal
dut_trigger_o : OUT std_logic --! Trigger output
);
-- Declarations
END ENTITY DUTInterface_AIDA ;
--
ARCHITECTURE rtl OF DUTInterface_AIDA IS
signal s_strobe_4x_logic_d1 : std_logic;
signal s_dut_clk : std_logic := '0'; -- Clock to be sent to DUT connectors ( before final register )
signal s_dut_clk_sr : std_logic_vector(2 downto 0) := "001"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
signal s_stretch_trig_in : std_logic := '0'; -- ! stretched version of trigger_i
signal s_stretch_trig_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by trigger_i
signal s_trigger_out : std_logic := '0'; -- ! trigger shifted to start on strobe_4x_logic
-- Set length of output trigger here ( output length = length of this vector + 1 )
signal s_trigger_out_sr : std_logic_vector(2 downto 0) := ( others => '1'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
BEGIN
-- Copy reset/clk signal straight through
dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
dut_shutter_o <= shutter_to_dut_i;
-- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
-- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_i
-- outputs: s_dut_clk
p_dut_clk_gen: process (clk_4x_logic_i , strobe_4x_logic_i) is
begin -- process p_dut_clk_gen
if rising_edge(clk_4x_logic_i) then
if (strobe_4x_logic_i = '1') then
s_dut_clk <= '1';
s_dut_clk_sr <= "001";
else
s_dut_clk <= s_dut_clk_sr(0);
s_dut_clk_sr <= '0' & s_dut_clk_sr(s_dut_clk_sr'left downto 1);
end if;
end if;
end process p_dut_clk_gen;
-- purpose: re-times a single cycle pulse on trigger on clk_4x_logic onto clk_logic
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , trigger_i
-- outputs: s_premask_trigger_to_dut
p_dut_trig_retime: process (clk_4x_logic_i , strobe_4x_logic_i , trigger_i) is
begin -- process p_dut_trig_retime
if rising_edge(clk_4x_logic_i) then
-- Stretch trigger_i pulse to 4 clock cycles on clk4x
if trigger_i = '1' then
s_stretch_trig_in <= '1';
s_stretch_trig_in_sr <= ( others => '1' );
else
s_stretch_trig_in <= s_stretch_trig_in_sr(0);
s_stretch_trig_in_sr <= '0' & s_stretch_trig_in_sr(s_stretch_trig_in_sr'left downto 1);
end if;
--
if (strobe_4x_logic_i = '1') and ( s_stretch_trig_in = '1' ) then
s_trigger_out <= '1';
s_trigger_out_sr <= ( others => '1' );
else
s_trigger_out <= s_trigger_out_sr(0);
s_trigger_out_sr <= '0' & s_trigger_out_sr(s_trigger_out_sr'left downto 1);
end if;
end if;
end process p_dut_trig_retime;
-- purpose: register for internal signals and output signals
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
-- outputs: busy_o
register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) );
dut_clk_o <= s_dut_clk ;
dut_trigger_o <= DUT_mask_i and s_trigger_out;
end if;
end process register_signals;
END ARCHITECTURE rtl;
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--! @file
-------------------------------------------------------------------------------
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! @brief "EUDET style" interfaces to a DUT connection. Outputs TRIGGER and receives DUT_CLK and BUSY
--! lines. Adapted from Trigger_Signal_Controller from EUDET TLU firmware.
--!
--! @author David.Cussans@bristol.ac.uk
--! @date 1/Sept/2015
------------------------------------------------------------------------------------
entity DUTInterface_EUDET is
GENERIC(
g_TRIGGER_DATA_WIDTH : positive := 32 -- was32
);
port (
rst_i : in std_logic; --! asynchronous reset. Active high
busy_o : out std_logic; --! low if FSM is in IDLE state, high otherwise
fsm_state_value_o : out std_logic_vector(3 downto 0); --! detailed status of FSM.
trigger_i : in std_logic; --! Trigger retimed onto system clock.active high.
trigger_counter_i : in std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0); --! event number
system_clk_i : in std_logic; --! rising edge active clock from TLU
reset_or_clk_to_dut_i : IN std_logic; --! Synchronization signal. Passed to DUT pins
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto flag set high
ignore_shutter_veto_i : in std_logic;
enable_dut_veto_i : in std_logic; --! If high: if DUT raises dut_busy_i, then busy_o is raised
-- Connections to DUT:
dut_clk_i : in std_logic; --! rising edge active clock from DUT
dut_busy_i : in std_logic; --! from DUT
dut_shutter_o : OUT std_logic; --! Shutter output.
dut_trigger_o : out std_logic --! trigger to DUT
);
end DUTInterface_EUDET;
architecture rtl of DUTInterface_EUDET is
-----------------------------------------------------------------------------
-- Declarations for state machine
type state_type is (IDLE , WAIT_FOR_BUSY_HIGH , TRIGGER_DEGLITCH_DELAY1 ,
TRIGGER_DEGLITCH_DELAY2 , WAIT_FOR_BUSY_LOW
, DUT_INITIATED_VETO );
-- );
signal state , next_state : state_type;
-- Xilinx Voodoo for state machine
attribute SAFE_IMPLEMENTATION : string;
attribute SAFE_IMPLEMENTATION of state : signal is "yes";
-- End of Xilinx Voodoo
-----------------------------------------------------------------------------
-- signal internal_clk : std_logic;
signal serial_trig_data : std_logic;
signal trig_shift_reg : std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0);
-- shift register storing parallel trigger data
-- signal d1_output : std_logic;
-- signal d2_output : std_logic;
signal dut_rising_edge : std_logic;
signal shift_reg_ce : std_logic;
signal dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2 : std_logic; -- ! registered values
begin -- rtl
dut_shutter_o <= shutter_to_dut_i ; -- for now just pass through.
-- purpose: suppress meta-stability by registering input signals.
-- type : combinational
-- inputs : dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2
-- outputs: dut_busy_r2 , dut_clk_r2
register_signals: process ( dut_busy_r1 , dut_clk_r1 , system_clk_i )
begin -- process register_signals
if rising_edge(system_clk_i) then
dut_busy_r2 <= dut_busy_r1 ;
dut_clk_r2 <= dut_clk_r1;
dut_busy_r1 <= dut_busy_i ;
dut_clk_r1 <= dut_clk_i;
end if;
end process register_signals;
rising_edge_pulse: entity work.single_pulse
port map (
level => dut_clk_i,
clk => system_clk_i,
pulse => dut_rising_edge);
-- look for the rising edge of DUT clock and enable CE for one cycle.
-- I have a nasty suspicion that meta-stability issues may make this
-- go horribly wrong .
-- Need to add timing constraint that shift_reg_ce must arrive before clock at trig_data_driver
-- also WAIT_FOR_BUSY_LOW must not mess things up.
clk_enable_select: process (state, dut_rising_edge)
begin -- process
if (state=WAIT_FOR_BUSY_LOW) then
shift_reg_ce <= dut_rising_edge;
else
shift_reg_ce <= '0';
end if;
end process;
-- purpose: controls the serial_trig_data line
-- type : combinational
-- inputs : system_clk_i , trigger_counter_i
-- outputs: serial_trig_data
trig_data_driver: process (system_clk_i , trigger_counter_i , shift_reg_ce , trig_shift_reg , state)
begin
if rising_edge( system_clk_i ) then
-- if busy is high in response to a trigger shift data out of
-- register on rising edge of DUT clock . This is done by having a slow
-- DUT clock and setting shift_reg_ce for one cycle of system_clk_i when
-- the DUT clock rising edge comes by.
if (shift_reg_ce ='1' ) then
trig_shift_reg <= '0' & trig_shift_reg(g_TRIGGER_DATA_WIDTH-1 downto 1);
serial_trig_data <= trig_shift_reg(0);
-- otherwise load shift register if we have just had a trigger.
elsif (state = WAIT_FOR_BUSY_HIGH ) then
-- only clock out bottom 15 bits of data.
-- (replace fixed width with a mask at some stage ?)
trig_shift_reg <= "00000000000000000" & trigger_counter_i(14 downto 0);
serial_trig_data <= '0';
end if;
end if;
end process trig_data_driver;
-- purpose: Determine the next state
-- type : combinational
-- inputs : state,Dut_Busy_r2, trigger_i
state_logic: process (state, trigger_i , enable_dut_veto_i , dut_clk_r2, dut_busy_r2 )
begin -- process state_logic
case state is
when IDLE =>
if ( trigger_i = '1') then -- respond to trigger going high
next_state <= WAIT_FOR_BUSY_HIGH; -- wait for DUT to respond to busy
elsif ( (dut_clk_r2 = '1') and (enable_dut_veto_i = '1') ) then -- If DUT asserts DUT_CLK_I then veto triggers
next_state <= DUT_INITIATED_VETO;
else
next_state <= IDLE;
end if;
when WAIT_FOR_BUSY_HIGH =>
if (DUT_Busy_r2 = '1') then
next_state <= TRIGGER_DEGLITCH_DELAY1;
else
next_state <= WAIT_FOR_BUSY_HIGH;
end if;
-- put in a pause to supress glitch in output trigger
-- this is an inelegant (to say the least ) way of doing it.
when TRIGGER_DEGLITCH_DELAY1 =>
next_state <= TRIGGER_DEGLITCH_DELAY2;
-- delay for two clock cycles.
when TRIGGER_DEGLITCH_DELAY2 =>
next_state <= WAIT_FOR_BUSY_LOW;
when WAIT_FOR_BUSY_LOW =>
if (DUT_Busy_r2 = '1') then
next_state <= WAIT_FOR_BUSY_LOW;
else
next_state <= IDLE;
end if;
when DUT_INITIATED_VETO =>
if (( dut_clk_r2 = '0' ) or ( enable_dut_veto_i = '0')) then
next_state <= IDLE;
else
next_state <= DUT_INITIATED_VETO;
end if;
end case;
end process state_logic;
-- determine clock select and trigger_mux from FSM state
-- purpose: Determines the state of the dut_trigger_o output based on the state of the FSM
-- type : combinational
-- inputs : state
-- outputs: dut_trigger_o
output_logic: process (state,serial_trig_data)
begin -- process output_logic
if ( state = IDLE ) then
-- waiting for external trigger to arrive...
dut_trigger_o <= '0';
elsif ((state = WAIT_FOR_BUSY_HIGH) or ( state=TRIGGER_DEGLITCH_DELAY1) or (state=TRIGGER_DEGLITCH_DELAY2) ) then
-- wait until the BUSY line goes high, then continue to hold TRIGGER high for two clock cycles.
dut_trigger_o <= '1';
elsif (state = WAIT_FOR_BUSY_LOW) then
-- if BUSY is high then connect TRIGGER to serial trigger number register.
dut_trigger_o <= serial_trig_data;
else
dut_trigger_o <= '0';
end if;
end process output_logic;
-- purpose: Register that holds the current state of the FSM
-- type : combinational
-- inputs : system_clk_i , rst_i
-- outputs: state
state_register: process (system_clk_i , rst_i)
begin -- process state_register
if (rst_i = '1') then
state <= IDLE;
elsif rising_edge(system_clk_i) then
state <= next_state;
end if;
end process state_register;
-- purpose: sets the value of clock_select based on FSM state
-- type : combinational
-- inputs : state
-- outputs: clock_select , trigger_muxsel , fsm_state
set_busy: process (system_clk_i , state)
begin -- process set_muxsel
if rising_edge(system_clk_i) then
if (state = IDLE) then
busy_o <= '0';
else
busy_o <= '1';
end if;
end if;
end process set_busy;
-- purpose: Sets the fsm_state_value_o vector to a number representing the current state
-- type : combinational
-- inputs : system_clk_i , state
-- outputs: fsm_state_value_o
store_state: process (system_clk_i , state)
begin -- process store_state
case state is
when IDLE =>
fsm_state_value_o <= "0000";
when WAIT_FOR_BUSY_HIGH =>
fsm_state_value_o <= "0001";
when TRIGGER_DEGLITCH_DELAY1 =>
fsm_state_value_o <= "0010";
when TRIGGER_DEGLITCH_DELAY2 =>
fsm_state_value_o <= "0011";
when WAIT_FOR_BUSY_LOW =>
fsm_state_value_o <= "0100";
when DUT_INITIATED_VETO =>
fsm_state_value_o <= "0101";
when others =>
fsm_state_value_o <= "1111";
end case;
end process store_state;
end rtl;
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15.02.2017 13:17:26
-- Design Name:
-- Module Name: DUTs_outputs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DUTs_outputs is
Port ( clk_in : in STD_LOGIC;
d_clk_o : out STD_LOGIC_VECTOR (3 downto 0);
d_trg_o : out STD_LOGIC_VECTOR (3 downto 0);
d_busy_o : out STD_LOGIC_VECTOR (3 downto 0);
d_cont_o : out STD_LOGIC_VECTOR (3 downto 0);
d_spare_o : out STD_LOGIC_VECTOR (3 downto 0));
end DUTs_outputs;
architecture Behavioral of DUTs_outputs is
signal toggleme : std_logic := '0';
begin
gen_clk : process (clk_in)
begin -- process gen_clk
if rising_edge(clk_in) then -- rising clock edge
toggleme <= not toggleme;
d_clk_o(1) <= toggleme;
d_clk_o(2) <= '0';
d_clk_o(3) <= '0';
d_trg_o <= ('0' & '0' & '0' & '0');
d_busy_o <= ('0' & '0' & '0' & '0');
d_cont_o <= ('0' & '0' & '0' & '0');
d_spare_o <=('0' & '0' & '0' & '0');
end if;
d_clk_o(0) <= clk_in;
end process gen_clk;
end Behavioral;
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--! @file dtype_fds.vhdl
--
-------------------------------------------------------------------------------
-- --
-- (c) University of Bristol, High Energy Physics Group --
-- --
-------------------------------------------------------------------------------
--
--
-- This file is part of IPBus.
--
-- IPBus is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- IPBus is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with IPBus. If not, see <http://www.gnu.org/licenses/>.
--
-- IPBus is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- IPBus is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with IPBus. If not, see <http://www.gnu.org/licenses/>.
--
--
--! Standard library
library IEEE;
-- Standard logic defintions.
use IEEE.STD_LOGIC_1164.all;
--
-- unit name: dtype_fds
--
--! @brief Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
--
--
--! @author David.Cussans@bristol.ac.uk
--
--! @date 7/May/2011
--
--! @version 0.1
--
--! @details -- Modified from D-type example in VHDL book.
--! See Xilinx spartan6_scm.pdf
--! Output goes high when input goes high ( asyncnronous to system clock).
--
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--! <reference one> \n
--! <reference two>
--!
--! <b>Modified by:</b>\n
--! Author: <name>
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! <date> <initials> <log>\n
--! <extended description>
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
-------------------------------------------------------------------------------
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-- Behavioural model of clocks for ipbus testing
--
-- The clock edges are *not* delta cycle accurate
-- Do not assume any phase relationship between clk125, clk25
--
-- Dave Newbold, March 2011
library ieee;
use ieee.std_logic_1164.all;
entity clock_sim is
port(
clko125: out std_logic;
clko25: out std_logic;
clko40: out std_logic;
nuke: in std_logic;
rsto: out std_logic
);
end clock_sim;
architecture behavioural of clock_sim is
signal clk125, clk25, clk40, nuke_del: std_logic := '0';
signal reset_vec: std_logic_vector(3 downto 0) := X"f";
begin
clk125 <= not clk125 after 4 ns;
clk25 <= not clk25 after 20 ns;
clk40 <= not clk40 after 12.5ns;
clko125 <= clk125;
clko25 <= clk25;
clko40 <= clk40;
process(clk25)
begin
if rising_edge(clk25) then
reset_vec <= '0' & reset_vec(3 downto 1);
end if;
end process;
nuke_del <= nuke after 50us;
rsto <= reset_vec(0) or nuke_del;
end behavioural;
\ No newline at end of file
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