Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
A
AIDA-2020 TLU - Software
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
AIDA-2020 TLU - Software
Commits
4fb85eef
Commit
4fb85eef
authored
Jun 13, 2018
by
Paolo Baesso
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Minor tweaks
parent
1357467e
Show whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
29 additions
and
18 deletions
+29
-18
AIDA_testScript.py
TLU_v1e/scripts/AIDA_testScript.py
+14
-12
TLU_v1e.py
TLU_v1e/scripts/TLU_v1e.py
+8
-2
localConf.conf
TLU_v1e/scripts/localConf.conf
+1
-1
TLU_powermodule.py
packages/TLU_powermodule.py
+6
-3
No files found.
TLU_v1e/scripts/AIDA_testScript.py
View file @
4fb85eef
...
...
@@ -95,11 +95,13 @@ res= zeClock.getDeviceVersion()
zeClock
.
checkDesignID
()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
clkRegList
=
zeClock
.
parse_clk
(
"./../../bitFiles/TLU_CLK_Config_v1e.txt"
)
zeClock
.
writeConfiguration
(
clkRegList
)
######
zeClock
.
writeRegister
(
0x0536
,
[
0x0A
])
#Configures manual switch of inputs
zeClock
.
writeRegister
(
0x0949
,
[
0x0F
])
#Enable all inputs
zeClock
.
writeRegister
(
0x052A
,
[
0x05
])
#Configures source of input
doClock
=
False
if
(
doClock
):
clkRegList
=
zeClock
.
parse_clk
(
"./../../bitFiles/TLU_CLK_Config_v1e.txt"
)
zeClock
.
writeConfiguration
(
clkRegList
)
######
zeClock
.
writeRegister
(
0x0536
,
[
0x0A
])
#Configures manual switch of inputs
zeClock
.
writeRegister
(
0x0949
,
[
0x0F
])
#Enable all inputs
zeClock
.
writeRegister
(
0x052A
,
[
0x05
])
#Configures source of input
iopower
=
zeClock
.
readRegister
(
0x0949
,
1
)
print
" Clock IO power: 0x
%
X"
%
iopower
[
0
]
lol
=
zeClock
.
readRegister
(
0x000E
,
1
)
...
...
@@ -132,32 +134,32 @@ IC6=PCA9539PW(master_I2C, 0x74)
#BANK 0
IC6
.
setInvertReg
(
0
,
0x00
)
# 0= normal
IC6
.
setIOReg
(
0
,
0x00
)
# 0= output <<<<<<<<<<<<<<<<<<<
IC6
.
setOutputs
(
0
,
0x77
)
IC6
.
setOutputs
(
0
,
0x77
)
#77
res
=
IC6
.
getInputs
(
0
)
print
"IC6 read back bank 0: 0x
%
X"
%
res
[
0
]
print
"
\t
IC6 read back bank 0: 0x
%
X"
%
res
[
0
]
#
#BANK 1
IC6
.
setInvertReg
(
1
,
0x00
)
# 0= normal
IC6
.
setIOReg
(
1
,
0x00
)
# 0= output <<<<<<<<<<<<<<<<<<<
IC6
.
setOutputs
(
1
,
0x77
)
IC6
.
setOutputs
(
1
,
0x77
)
#77
res
=
IC6
.
getInputs
(
1
)
print
"IC6 read back bank 1: 0x
%
X"
%
res
[
0
]
print
"
\t
IC6 read back bank 1: 0x
%
X"
%
res
[
0
]
# # #
IC7
=
PCA9539PW
(
master_I2C
,
0x75
)
#BANK 0
IC7
.
setInvertReg
(
0
,
0x00
)
# 0= normal
IC7
.
setIOReg
(
0
,
0x00
)
# 0= output <<<<<<<<<<<<<<<<<<<
IC7
.
setOutputs
(
0
,
0x
0
0
)
IC7
.
setOutputs
(
0
,
0x
F
0
)
res
=
IC7
.
getInputs
(
0
)
print
"IC7 read back bank 0: 0x
%
X"
%
res
[
0
]
print
"
\t
IC7 read back bank 0: 0x
%
X"
%
res
[
0
]
#
#BANK 1
IC7
.
setInvertReg
(
1
,
0x00
)
# 0= normal
IC7
.
setIOReg
(
1
,
0x00
)
# 0= output <<<<<<<<<<<<<<<<<<<
IC7
.
setOutputs
(
1
,
0xB0
)
res
=
IC7
.
getInputs
(
1
)
print
"IC7 read back bank 1: 0x
%
X"
%
res
[
0
]
print
"
\t
IC7 read back bank 1: 0x
%
X"
%
res
[
0
]
# #I2C EXPANDER CONFIGURATION END
...
...
TLU_v1e/scripts/TLU_v1e.py
View file @
4fb85eef
...
...
@@ -20,6 +20,7 @@ class TLU:
"""docstring for TLU"""
def
__init__
(
self
,
dev_name
,
man_file
,
parsed_cfg
):
uhal
.
setLogLevelTo
(
uhal
.
LogLevel
.
NOTICE
)
## Get rid of initial flood of IPBUS messages
self
.
isRunning
=
False
section_name
=
"Producer.fmctlu"
...
...
@@ -137,11 +138,16 @@ class TLU:
#self.pwdled.setIndicatorRGB(11, [0, 0, 1])
self
.
pwdled
.
allGreen
()
time
.
sleep
(
0.1
)
self
.
pwdled
.
allBlue
()
time
.
sleep
(
0.1
)
self
.
pwdled
.
allBlack
()
time
.
sleep
(
0.1
)
#self.pwdled.kitt()
self
.
pwdled
.
allBlack
()
self
.
pwdled
.
allRed
()
time
.
sleep
(
0.1
)
#self.pwdled.allBlack()
#self.pwdled.allRed()
#time.sleep(0.1)
self
.
pwdled
.
allWhite
()
...
...
TLU_v1e/scripts/localConf.conf
View file @
4fb85eef
...
...
@@ -51,7 +51,7 @@ DACThreshold4 = -0.12
DACThreshold5
= -
0
.
12
# Define which DUTs are ON
DUTMask
=
1
DUTMask
=
0
x
1
# Define mode of DUT (00 EUDET, 11 AIDA)
DUTMaskMode
=
0
xFC
...
...
packages/TLU_powermodule.py
View file @
4fb85eef
...
...
@@ -89,7 +89,7 @@ class PWRLED:
for
iComp
in
range
(
0
,
3
):
indexComp
=
self
.
indicatorXYZ
[
indicator
-
1
][
iComp
]
valueComp
=
not
bool
(
RGB
[
iComp
])
nextWrd
=
self
.
_set_bit
(
nextWrd
,
indexComp
,
int
(
valueComp
))
nextWrd
=
self
.
_set_bit
(
nextWrd
,
indexComp
,
int
(
valueComp
)
,
False
)
if
verbose
:
print
"n="
,
iComp
,
"INDEX="
,
indexComp
,
"VALUE="
,
int
(
valueComp
),
"NEXTWORD="
,
bin
(
nextWrd
)
if
verbose
:
...
...
@@ -110,9 +110,10 @@ class PWRLED:
return
def
_set_bit
(
self
,
v
,
index
,
x
):
def
_set_bit
(
self
,
v
,
index
,
x
,
verbose
=
False
):
"""Set the index:th bit of v to 1 if x is truthy, else to 0, and return the new value."""
if
(
index
==
-
1
):
if
(
verbose
):
print
" SETBIT: Index= -1 will be ignored"
else
:
mask
=
1
<<
index
# Compute mask, an integer with just bit 'index' set.
...
...
@@ -164,6 +165,7 @@ class PWRLED:
def
kitt
(
self
):
#self.allBlack()
print
"
\t
Wait while LEDs are tested..."
self
.
setIndicatorRGB
(
1
,
[
1
,
0
,
0
])
self
.
setIndicatorRGB
(
2
,
[
0
,
0
,
0
])
self
.
setIndicatorRGB
(
3
,
[
0
,
0
,
0
])
...
...
@@ -476,3 +478,4 @@ class PWRLED:
self
.
setIndicatorRGB
(
9
,
[
0
,
0
,
0
])
self
.
setIndicatorRGB
(
10
,
[
0
,
0
,
0
])
self
.
setIndicatorRGB
(
11
,
[
0
,
0
,
0
])
print
"
\t
LED test completed"
\ No newline at end of file
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment