N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH) port map( ipb_in => ipb_in, ipb_out => ipb_out, sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr), ipb_to_slaves => ipbw, ipb_from_slaves => ipbr ); -- Slave 0: id / rst reg slave0: entity work.ipbus_ctrlreg_v port map( clk => ipb_clk, reset => ipb_rst, ipbus_in => ipbw(N_SLV_CTRL_REG), ipbus_out => ipbr(N_SLV_CTRL_REG), d => stat, q => ctrl ); stat(0) <= X"abcdfedc"; soft_rst <= ctrl(0)(0); nuke <= ctrl(0)(1); -- Slave 1: register slave1: entity work.ipbus_reg_v port map( clk => ipb_clk, reset => ipb_rst, ipbus_in => ipbw(N_SLV_REG), ipbus_out => ipbr(N_SLV_REG), q => open ); -- Slave 2: 1kword RAM slave4: entity work.ipbus_ram generic map(ADDR_WIDTH => 10) port map( clk => ipb_clk, reset => ipb_rst, ipbus_in => ipbw(N_SLV_RAM), ipbus_out => ipbr(N_SLV_RAM) ); -- Slave 3: peephole RAM slave5: entity work.ipbus_peephole_ram generic map(ADDR_WIDTH => 10) port map( clk => ipb_clk, reset => ipb_rst, ipbus_in => ipbw(N_SLV_PRAM), ipbus_out => ipbr(N_SLV_PRAM) ); -- slave6 : i2c_master -- PORT MAP ( -- i2c_scl_i => i2c_scl_b, -- i2c_sda_i => i2c_sda_b, -- ipbus_clk_i => ipb_clk, -- ipbus_i => ipbw(N_SLV_I2C), -- ipbus_reset_i => ipb_rst, -- i2c_scl_enb_o => s_i2c_scl_enb, -- i2c_sda_enb_o => s_i2c_sda_enb, -- ipbus_o => ipbr(N_SLV_I2C) -- ); -- Instantiate a I2C core for the EEPROM slave6 : i2c_master PORT MAP ( i2c_scl_i => i2c_scl_i(0), i2c_sda_i => i2c_sda_i(0), ipbus_clk_i => ipb_clk, ipbus_i => ipbw(N_SLV_I2C_0), ipbus_reset_i => ipb_rst, i2c_scl_enb_o => i2c_scl_enb_o(0), i2c_sda_enb_o => i2c_sda_enb_o(0), ipbus_o => ipbr(N_SLV_I2C_0) ); slave7 : i2c_master PORT MAP ( i2c_scl_i => i2c_scl_i(1), i2c_sda_i => i2c_sda_i(1), ipbus_clk_i => ipb_clk, ipbus_i => ipbw(N_SLV_I2C_1), ipbus_reset_i => ipb_rst, i2c_scl_enb_o => i2c_scl_enb_o(1), i2c_sda_enb_o => i2c_sda_enb_o(1), ipbus_o => ipbr(N_SLV_I2C_1) ); slave8 : i2c_master PORT MAP ( i2c_scl_i => i2c_scl_i(2), i2c_sda_i => i2c_sda_i(2), ipbus_clk_i => ipb_clk, ipbus_i => ipbw(N_SLV_I2C_2), ipbus_reset_i => ipb_rst, i2c_scl_enb_o => i2c_scl_enb_o(2), i2c_sda_enb_o => i2c_sda_enb_o(2), ipbus_o => ipbr(N_SLV_I2C_2) ); end rtl; fmc-mtlu-sw-master/EUDETdummy/hdl/ipbus_fabric_sel.vhd 0000664 0000000 0000000 00000003211 14436063765 0023224 0 ustar 00root root 0000000 0000000 -- The ipbus bus fabric, address select logic, data multiplexers -- -- This version selects the addressed slave depending on the state -- of incoming control lines -- -- Dave Newbold, February 2011 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use work.ipbus.ALL; entity ipbus_fabric_sel is generic( NSLV: positive; STROBE_GAP: boolean := false; SEL_WIDTH: positive ); port( sel: in std_logic_vector(SEL_WIDTH - 1 downto 0); ipb_in: in ipb_wbus; ipb_out: out ipb_rbus; ipb_to_slaves: out ipb_wbus_array(NSLV - 1 downto 0); ipb_from_slaves: in ipb_rbus_array(NSLV - 1 downto 0) := (others => IPB_RBUS_NULL) ); end ipbus_fabric_sel; architecture rtl of ipbus_fabric_sel is signal sel_i: integer range 0 to NSLV := 0; signal ored_ack, ored_err: std_logic_vector(NSLV downto 0); signal qstrobe: std_logic; begin sel_i <= to_integer(unsigned(sel)); ored_ack(NSLV) <= '0'; ored_err(NSLV) <= '0'; qstrobe <= ipb_in.ipb_strobe when STROBE_GAP = false else ipb_in.ipb_strobe and not (ored_ack(0) or ored_err(0)); busgen: for i in NSLV-1 downto 0 generate begin ipb_to_slaves(i).ipb_addr <= ipb_in.ipb_addr; ipb_to_slaves(i).ipb_wdata <= ipb_in.ipb_wdata; ipb_to_slaves(i).ipb_strobe <= qstrobe when sel_i = i else '0'; ipb_to_slaves(i).ipb_write <= ipb_in.ipb_write; ored_ack(i) <= ored_ack(i+1) or ipb_from_slaves(i).ipb_ack; ored_err(i) <= ored_err(i+1) or ipb_from_slaves(i).ipb_err; end generate; ipb_out.ipb_rdata <= ipb_from_slaves(sel_i).ipb_rdata when sel_i /= NSLV else (others => '0'); ipb_out.ipb_ack <= ored_ack(0); ipb_out.ipb_err <= ored_err(0); end rtl; fmc-mtlu-sw-master/EUDETdummy/hdl/ipbus_slaves.vhd 0000664 0000000 0000000 00000011335 14436063765 0022436 0 ustar 00root root 0000000 0000000 -- ipbus_example -- -- selection of different IPBus slaves without actual function, -- just for performance evaluation of the IPbus/uhal system -- -- Kristian Harder, March 2014 -- based on code by Dave Newbold, February 2011 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.ipbus.all; use work.ipbus_reg_types.all; use work.ipbus_decode_ipbus_example.all; entity ipbus_slaves is port( ipb_clk: in std_logic; ipb_rst: in std_logic; ipb_in: in ipb_wbus; ipb_out: out ipb_rbus; nuke: out std_logic; soft_rst: out std_logic; --i2c_scl_b: INOUT std_logic; --i2c_sda_b: INOUT std_logic; --i2c_sda_i: IN std_logic; --i2c_scl_i: IN std_logic; --i2c_scl_enb_o: OUT std_logic; --i2c_sda_enb_o: OUT std_logic; i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0); i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0); i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0); i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0); userled: out std_logic ); end ipbus_slaves; architecture rtl of ipbus_slaves is signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0); signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0); signal ctrl, stat: ipb_reg_v(0 downto 0); --SIGNAL s_i2c_scl_enb : std_logic; --SIGNAL s_i2c_sda_enb : std_logic; -->P COMPONENT i2c_master PORT ( i2c_scl_i : IN std_logic; i2c_sda_i : IN std_logic; ipbus_clk_i : IN std_logic; ipbus_i : IN ipb_wbus; ipbus_reset_i : IN std_logic; i2c_scl_enb_o : OUT std_logic; i2c_sda_enb_o : OUT std_logic; ipbus_o : OUT ipb_rbus ); END COMPONENT i2c_master; FOR ALL : i2c_master USE ENTITY work.i2c_master;--
N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH) port map( ipb_in => ipb_in, ipb_out => ipb_out, sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr), ipb_to_slaves => ipbw, ipb_from_slaves => ipbr ); -- Slave 0: id / rst reg slave0: entity work.ipbus_ctrlreg_v port map( clk => ipb_clk, reset => ipb_rst, ipbus_in => ipbw(N_SLV_CTRL_REG), ipbus_out => ipbr(N_SLV_CTRL_REG), d => stat, q => ctrl ); stat(0) <= X"abcdfedc"; soft_rst <= ctrl(0)(0); nuke <= ctrl(0)(1); -- Slave 1: register slave1: entity work.ipbus_reg_v port map( clk => ipb_clk, reset => ipb_rst, ipbus_in => ipbw(N_SLV_REG), ipbus_out => ipbr(N_SLV_REG), q => open ); -- Slave 2: 1kword RAM -- slave4: entity work.ipbus_ram -- generic map(ADDR_WIDTH => 10) -- port map( -- clk => ipb_clk, -- reset => ipb_rst, -- ipbus_in => ipbw(N_SLV_RAM), -- ipbus_out => ipbr(N_SLV_RAM) -- ); -- Slave 3: peephole RAM -- slave5: entity work.ipbus_peephole_ram -- generic map(ADDR_WIDTH => 10) -- port map( -- clk => ipb_clk, -- reset => ipb_rst, -- ipbus_in => ipbw(N_SLV_PRAM), -- ipbus_out => ipbr(N_SLV_PRAM) -- ); -- slave6 : i2c_master -- PORT MAP ( -- i2c_scl_i => i2c_scl_b, -- i2c_sda_i => i2c_sda_b, -- ipbus_clk_i => ipb_clk, -- ipbus_i => ipbw(N_SLV_I2C), -- ipbus_reset_i => ipb_rst, -- i2c_scl_enb_o => s_i2c_scl_enb, -- i2c_sda_enb_o => s_i2c_sda_enb, -- ipbus_o => ipbr(N_SLV_I2C) -- ); -- Instantiate a I2C core for the EEPROM slave6 : i2c_master PORT MAP ( i2c_scl_i => i2c_scl_i(0), i2c_sda_i => i2c_sda_i(0), ipbus_clk_i => ipb_clk, ipbus_i => ipbw(N_SLV_I2C_0), ipbus_reset_i => ipb_rst, i2c_scl_enb_o => i2c_scl_enb_o(0), i2c_sda_enb_o => i2c_sda_enb_o(0), ipbus_o => ipbr(N_SLV_I2C_0) ); slave7 : i2c_master PORT MAP ( i2c_scl_i => i2c_scl_i(1), i2c_sda_i => i2c_sda_i(1), ipbus_clk_i => ipb_clk, ipbus_i => ipbw(N_SLV_I2C_1), ipbus_reset_i => ipb_rst, i2c_scl_enb_o => i2c_scl_enb_o(1), i2c_sda_enb_o => i2c_sda_enb_o(1), ipbus_o => ipbr(N_SLV_I2C_1) ); slave8 : i2c_master PORT MAP ( i2c_scl_i => i2c_scl_i(2), i2c_sda_i => i2c_sda_i(2), ipbus_clk_i => ipb_clk, ipbus_i => ipbw(N_SLV_I2C_2), ipbus_reset_i => ipb_rst, i2c_scl_enb_o => i2c_scl_enb_o(2), i2c_sda_enb_o => i2c_sda_enb_o(2), ipbus_o => ipbr(N_SLV_I2C_2) ); end rtl; fmc-mtlu-sw-master/EUDETdummy/hdl/ipbus_ver.vhd 0000664 0000000 0000000 00000002467 14436063765 0021743 0 ustar 00root root 0000000 0000000 --============================================================================= --! @file ipbus_ver.vhd --============================================================================= -- Version register, returns a fixed value -- -- To be replaced by a more coherent versioning mechanism later -- -- Dave Newbold, August 2011 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.ipbus.all; --! @brief IPBus fixed register returning Firmware version number entity ipbus_ver is port( ipbus_in: in ipb_wbus; ipbus_out: out ipb_rbus ); end ipbus_ver; architecture rtl of ipbus_ver is begin ipbus_out.ipb_rdata <= X"a622" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement). ipbus_out.ipb_ack <= ipbus_in.ipb_strobe; ipbus_out.ipb_err <= '0'; end rtl; -- Build log -- -- build 0x1000 : 22/08/11 : Starting build ID -- build 0x1001 : 29/08/11 : Version for SPI testing -- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate -- build 0x1003 : buggy -- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase -- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t -- build 0x1006 : 26/10/11 : trying with jumbo frames -- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames -- build 0x1008 : 31/10/11 : rhino frames + multibus demo fmc-mtlu-sw-master/EUDETdummy/hdl/led_stretcher.vhd 0000664 0000000 0000000 00000002530 14436063765 0022563 0 ustar 00root root 0000000 0000000 -- stretcher -- -- Stretches a single clock pulse so it's visible on an LED -- -- Dave Newbold, January 2013 -- -- $Id$ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity led_stretcher is generic( WIDTH: positive := 1 ); port( clk: in std_logic; -- Assumed to be 125MHz ipbus clock d: in std_logic_vector(WIDTH - 1 downto 0); -- Input (edge detected) q: out std_logic_vector(WIDTH - 1 downto 0) -- LED output, ~250ms pulse ); end led_stretcher; architecture rtl of led_stretcher is signal d17, d17_d: std_logic; begin clkdiv: entity work.ipbus_clock_div port map( clk => clk, d17 => d17 ); process(clk) begin if rising_edge(clk) then d17_d <= d17; end if; end process; lgen: for i in WIDTH - 1 downto 0 generate signal s, sd, e, e_d, sl: std_logic; signal scnt: unsigned(6 downto 0); begin process(clk) begin if rising_edge(clk) then s <= d(i); -- Possible clock domain crossing from slower clock (sync not important) sd <= s; e <= (e or (s and not sd)) and not e_d; if d17 = '1' and d17_d = '0' then e_d <= e; if e = '1' then scnt <= "0000001"; elsif sl = '0' then scnt <= scnt + 1; end if; end if; end if; end process; sl <= '1' when scnt = "0000000" else '0'; q(i) <= not sl; end generate; end rtl; fmc-mtlu-sw-master/EUDETdummy/hdl/logic_clocks_rtl.vhd 0000664 0000000 0000000 00000034525 14436063765 0023261 0 ustar 00root root 0000000 0000000 --============================================================================= --! @file logic_clocks_rtl.vhd --============================================================================= -- ------------------------------------------------------------------------------- -- -- -- University of Bristol, High Energy Physics Group. -- -- ------------------------------------------------------------------------------- -- -- VHDL Architecture fmc_mTLU_lib.logic_clocks.rtl -- -------------------------------------------------------------------------------- -- -- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21) -- -- Based on output of Xilinx Coregen and Alvro Dosil TLU code. ------------------------------------------------------------------------------ -- "Output Output Phase Duty Pk-to-Pk Phase" -- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------ -- CLK_OUT1___640.000______0.000______50.0______175.916____213.982 -- CLK_OUT2___160.000______0.000______50.0______223.480____213.982 -- CLK_OUT3____40.000______0.000______50.0______306.416____213.982 -- ------------------------------------------------------------------------------ -- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------ -- __primary__________40.000____________0.010 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.ipbus.all; library unisim; use unisim.vcomponents.all; --! @brief Generates 160MHz , 640MHz clocks from an incoming 40MHz clock. --! Can switch between clock generated from on-board Xtal ( clk_logic_xtal ) and external clock. --! Can also output clock to external clock pins. --! --! @author David Cussans , David.Cussans@bristol.ac.uk -- --! @date 14:20:26 11/14/12 -- --! @version v0.1 -- --! @details --! \br IPBus Address map: --! \br (decode 2 bits) --! \li 0x00000000 - control/status register: --! \li bit-0 - PLL locked ( 1 = locked ) --! \li bit-1 - buff-PLL locked ( 1 = locked ) --! \li bit-2 - use xtal for logic ( 1 = xtal , 0= external) --! \li bit-3 - clock connector is an input ( 1=input , 0 = output) --! \li 0x00000001 - reset logic. Write to bit-zero to send reset. --! --! ENTITY logic_clocks IS GENERIC( g_USE_EXTERNAL_CLK : integer := 1 ); PORT( ipbus_clk_i : IN std_logic; ipbus_i : IN ipb_wbus; ipbus_reset_i : IN std_logic; Reset_i : IN std_logic; clk_logic_xtal_i : IN std_logic; --! 40MHz clock derived from onboard xtal clk_8x_logic_o : OUT std_logic; --! 640MHz clock clk_4x_logic_o : OUT std_logic; --! 160MHz clock ipbus_o : OUT ipb_rbus; strobe_8x_logic_o : OUT std_logic; --! strobes once every 4 cycles of clk_16x strobe_4x_logic_o : OUT std_logic; --! one pulse every 4 cycles of clk_4x DUT_clk_o : OUT std_logic; --! 40MHz to DUTs logic_clocks_locked_o : OUT std_logic; --! Goes high if clocks locked. logic_reset_o : OUT std_logic --! Goes high to reset counters etc. Sync with clk_4x_logic ); -- Declarations END ENTITY logic_clocks ; -- ARCHITECTURE rtl OF logic_clocks IS signal s_clk40 , s_clk40_internal : std_logic; signal s_clk160 ,s_clk160_internal : std_logic; signal ryanclock : std_logic; signal s_clk320 , s_clk320_internal : std_logic; signal s_clk40_out : std_logic; -- Clock generated by DDR register to feed out of chip. signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '0'; -- default to -- input from ext -- signal s_logic_clk_rst : std_logic := '0'; signal s_locked_pll, s_locked_bufpll : std_logic; signal s_clk : std_logic; signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic; signal s_extclk, s_extclkG : std_logic; -- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic : std_logic; signal s_clkfbout_buf , s_clkfbout : std_logic; signal s_strobe_generator : std_logic_vector(3 downto 0) := "1000"; -- ! Store state of ring buffer to generate strobe signal s_logic_clk_generator : std_logic_vector(3 downto 0) := "1100"; --! Stores state of 40MHz "clock" --signal s_strobe_generator : std_logic_vector(15 downto 0) := "1111000000000000"; -- ! Store state of ring buffer to generate strobe --signal s_logic_clk_generator : std_logic_vector(15 downto 0) := "1111111100000000"; --! Stores state of 40MHz "clock" signal s_strobe160 :std_logic_vector(15 downto 0) := "1000000000000000"; -- 160 strobe ring signal s_strobe_fb : std_logic := '0'; signal s_logic_reset_ipb, s_logic_reset_ipb_d1 : std_logic := '0'; -- ! Reset signal in IPBus clock domain signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 , s_logic_reset_d4 : std_logic := '0'; -- ! reset signal clocked onto logic-clock domain. attribute SHREG_EXTRACT: string; attribute SHREG_EXTRACT of s_logic_reset_d1: signal is "no"; -- Synchroniser not to be optimised into shre attribute SHREG_EXTRACT of s_logic_reset_d2: signal is "no"; -- Synchroniser not to be optimised into shreg attribute SHREG_EXTRACT of s_logic_reset_d3: signal is "no"; -- Synchroniser not to be optimised into shreg attribute SHREG_EXTRACT of s_logic_reset_d4: signal is "no"; -- Synchroniser not to be optimised into shreg signal s_ipbus_ack : std_logic := '0'; signal s_reset_pll : std_logic := '0'; -- ! Global Reset signal signal s_extclk_internal : std_logic := '0'; signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range ); --! Hold status of clocks BEGIN ----------------------------------------------------------------------------- -- IPBus write ----------------------------------------------------------------------------- ipbus_write: process (ipbus_clk_i) begin -- process ipb_clk_i if rising_edge(ipbus_clk_i) then s_logic_reset_ipb <= '0'; if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then case ipbus_i.ipb_addr(1 downto 0) is when "00" => s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source when "01" => s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset when others => null; end case; end if; -- register reset signal to aid timing. s_logic_reset_ipb_d1 <= s_logic_reset_ipb; s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack; -- register the clock status signals onto IPBus domain. --s_clock_status_ipb <= x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll; s_clock_status_ipb <= x"0000000" & '0' & '0' & '0' & s_locked_pll; -- The only useful bit is not the PLL lock status. end if; end process ipbus_write; ipbus_o.ipb_ack <= s_ipbus_ack; ipbus_o.ipb_err <= '0'; ----------------------------------------------------------------------------- -- IPBUS read ----------------------------------------------------------------------------- with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <= s_clock_status_ipb when "00", (others => '1') when others; ----------------------------------------------------------------------------- -- Generate reset signal on logic-clock domain -- This relies on the IPBus clock being much slower than the 4x logic clock. ----------------------------------------------------------------------------- p_reset: process (s_clk160_internal) begin -- process p_reset if rising_edge(s_clk160_internal) then s_logic_reset_d1 <= s_logic_reset_ipb_d1; s_logic_reset_d2 <= s_logic_reset_d1; s_logic_reset_d3 <= s_logic_reset_d2; s_logic_reset_d4 <= s_logic_reset_d2 and ( not s_logic_reset_d3); s_logic_reset <= s_logic_reset_d4; end if; end process p_reset; logic_reset_o <= s_logic_reset; logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll; -- Use Generate, since can't figure out how BUFGMUX works -- gen_extclk_input: if ( g_USE_EXTERNAL_CLK = 1) generate -- s_DUT_Clk <= s_extclkG; -- Hard wire for now. -- end generate gen_extclk_input; -- gen_intclk_input: if ( g_USE_EXTERNAL_CLK = 0) generate s_DUT_Clk <= clk_logic_xtal_i; -- end generate gen_intclk_input; --! Clocking primitive ------------------------------------- --! Instantiation of the PLL primitive pll_base_inst : PLL_BASE generic map (BANDWIDTH => "OPTIMIZED", --CLK_FEEDBACK => "CLKOUT0", --"CLKFBOUT", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "SYSTEM_SYNCHRONOUS", DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 16, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 2, -- 1-->2 move from 640 to 320 CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT1_DIVIDE => 4, -- 4-->8 move from 160 to 80 CLKOUT1_PHASE => 0.000, CLKOUT1_DUTY_CYCLE => 0.500, CLKOUT2_DIVIDE => 16, -- 16--> 32 move from 40 to 20 CLKOUT2_PHASE => 0.000, CLKOUT2_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 25.000, REF_JITTER => 0.010) port map( -- Output clocks CLKFBOUT => s_clkfbout, CLKOUT0 => s_clk320, CLKOUT1 => s_clk160, CLKOUT2 => s_clk40, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, -- Status and control signals LOCKED => s_locked_pll, -- RST => s_logic_clk_rst, RST => s_reset_pll, -- Input clock control -- CLKFBIN => s_clkfbout_buf, CLKFBIN => s_clkfbout, CLKIN => s_DUT_clk); -- CLKIN => clk_logic_xtal_i); s_reset_pll <= Reset_i or s_logic_reset; ----------------------------------------------- --BUFPLL not supported by 7 Series. We need to replace it with BUFIO+BUFR -- Buffer the 16x clock and generate the ISERDES strobe signal -- BUFPLL_inst : BUFPLL -- generic map ( -- DIVIDE => 4) -- port map ( -- IOCLK => s_clk640_internal, -- 1-bit output: Output I/O clock -- LOCK => s_locked_bufpll, -- 1-bit output: Synchronized LOCK output -- SERDESSTROBE => strobe_16x_logic_O, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2) -- GCLK => s_clk160_internal, -- 1-bit input: BUFG clock input -- LOCKED => s_locked_pll, -- 1-bit input: LOCKED input from PLL -- PLLIN => s_clk640 -- 1-bit input: Clock input from PLL -- ); BUFG_inst: BUFG port map ( I => s_clk320, O => s_clk320_internal ); -- BUFR_inst: BUFR -- generic map ( -- BUFR_DIVIDE => "4" -- ) -- port map ( -- I => s_clk160_internal, -- CE => '1', -- CLR => '0', -- O => ryanclock -- ); -- BUFG_inst2: BUFG -- port map ( -- I => ryanclock, -- O => strobe_16x_logic_O -- Not sure this is actually a strobe... Check -- ); ----------------------------------------------- clk_8x_logic_o <= s_clk320_internal; DUT_clk_o <= s_DUT_clk; -- Generate a strobe signal every 4 clocks. -- Can't use a clock signal as a combinatorial signal. Hence the baroque -- method of generating a strobe. Add a mechanism to restart if the '1' gets -- lost .... ------------------ generate_4x_strobe: process (s_clk160_internal)-- , s_clk40_out) begin -- process generate_4x_strobe if rising_edge(s_clk160_internal) then if s_logic_reset = '1' then s_strobe_generator <= "1000"; s_logic_clk_generator <= "1100"; --s_strobe160 <= "1000000000000000"; elsif (s_locked_pll ='1') then s_strobe_generator <= s_strobe_generator(2 downto 0) & s_strobe_generator(3); -- <- bit shift left s_logic_clk_generator <= s_logic_clk_generator(2 downto 0) & s_logic_clk_generator(3); -- <- bit shift left --s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15); end if; end if; end process generate_4x_strobe; strobe_4x_logic_o <= s_strobe_generator(3); -- Every 4 clocks this gets to 1 for one pulse s_clk40_out <= s_logic_clk_generator(3); -- Every 4 clocks this gets to 1 for two pulses (so half F of the original clock? But then it is a clk80 not clk40.) Not used it seems. --------------- generate_8x_strobe: process (s_clk320_internal) begin if rising_edge(s_clk320_internal) then if s_logic_reset = '1' then s_strobe160 <= "1000000000000000"; --s_strobe_generator <= "1111000000000000";-- --s_logic_clk_generator <= "1111111100000000";-- elsif (s_locked_pll ='1') then s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15); --s_strobe_generator <= s_strobe_generator(14 downto 0) & s_strobe_generator(15); -- --s_logic_clk_generator <= s_logic_clk_generator(14 downto 0) & s_logic_clk_generator(15); -- <- bit shift left end if; end if; end process generate_8x_strobe; strobe_8x_logic_O <= s_strobe160(15); --strobe_4x_logic_o <= s_strobe_generator(15); -- --s_clk40_out <= s_logic_clk_generator(15); -- -- buffer 160MHz (4x) clock -------------------------------------- clk160_o_buf : BUFG port map( O => s_clk160_internal, I => s_clk160); clk_4x_logic_o <= s_clk160_internal; -- -- buffer 40MHz (1x) clock -- -------------------------------------- -- clk40_o_buf : BUFG -- port map( -- O => s_clk40_internal, -- I => s_clk40); -- clk_logic_o <= s_clk40_out; END ARCHITECTURE rtl; fmc-mtlu-sw-master/EUDETdummy/hdl/top_EUDET_dummy.vhd 0000664 0000000 0000000 00000072124 14436063765 0022705 0 ustar 00root root 0000000 0000000 -- Top-level design for TLU v1E -- -- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard -- -- You must edit this file to set the IP and MAC addresses -- -- Dave Newbold, 4/10/16-- library IEEE; library UNISIM; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use work.fmcTLU.all; use work.ipbus_decode_tlu.all; use work.ipbus.all; use work.ipbus_reg_types.all; use UNISIM.vcomponents.all; --Library UNISIM; --use UNISIM.vcomponents.all; use work.ipbus.ALL; entity top_EUDET_dummy is generic( constant FW_VERSION : unsigned(31 downto 0):= X"ffff0006"; -- Firmware revision. Remember to change this as needed. g_NUM_DUTS : positive := 4; -- <- was 3 g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4 g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4 g_NUM_EXT_SLAVES :positive :=8;-- <-- ?? g_EVENT_DATA_WIDTH :positive := 32;-- <-- ?? g_IPBUS_WIDTH :positive := 32;-- <-- was 32 g_SPILL_COUNTER_WIDTH :positive := 12;-- <-- ?? g_BUILD_SIMULATED_MAC :integer := 0 ); port( --Clock --sysclk: in std_logic; --50 MHz clock input from FPGA clk_enclustra: in std_logic; --Enclustra onboard oscillator 40 MHz. Used for the IPBus block sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins sysclk_40_i_p: in std_logic; sysclk_40_i_n: in std_logic; --Misc leds: out std_logic_vector(3 downto 0); -- status LEDs dip_sw: in std_logic_vector(3 downto 0); -- switches gpio: out std_logic; -- gpio pin on J1 (eventually make it inout) --RGMII interface signals rgmii_txd: out std_logic_vector(3 downto 0); rgmii_tx_ctl: out std_logic; rgmii_txc: out std_logic; rgmii_rxd: in std_logic_vector(3 downto 0); rgmii_rx_ctl: in std_logic; rgmii_rxc: in std_logic; phy_rstn: out std_logic; --I2C bus i2c_scl_b: inout std_logic; i2c_sda_b: inout std_logic; i2c_reset: out std_logic; --Reset line for the expander serial lines --Clock generator controls clk_gen_rst: out std_logic; --Reset line for the Si5345 clock generator (active low) --clk_gen_lol: in std_logic; --LOL signal. Do not use for now as it is connected to CONT_FROM_FPGA<0> --TLU signals for DUTs busy_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines from DUTs (active high) (busy to FPGA) busy_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines to DUTs (active high) (busy from FPGA) cont_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines from DUTs cont_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines to DUTs spare_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines from DUTs spare_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines to DUTs triggers_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines from DUTs triggers_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines to DUTs dut_clk_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Clock from DUTs dut_clk_o: out std_logic_vector(g_NUM_DUTS-1 downto 0) --Clock to DUTs --reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --T0 synchronization signal --reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Shutter output --shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); ); end top_EUDET_dummy; architecture rtl of top_EUDET_dummy is signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, clk_200, sysclk_40, clk_encl_buf, userled: std_logic; signal mac_addr: std_logic_vector(47 downto 0); signal ip_addr: std_logic_vector(31 downto 0); signal ipb_out: ipb_wbus; signal ipb_in: ipb_rbus; signal inf_leds: std_logic_vector(1 downto 0); signal s_i2c_scl_enb : std_logic; signal s_i2c_sda_enb : std_logic; signal encl_clock50: std_logic; -- This is a 50 MHz clock generated from the Enclustra onboard oscillator (rather than the clock input) --signal s_i2c_sda_i : std_logic; --signal s_i2c_scl_i : std_logic; ------------------------------------------ -- Internal signal declarations SIGNAL T0_o : std_logic; SIGNAL buffer_full_o : std_logic; --! Goes high when event buffer almost full SIGNAL clk_8x_logic : std_logic; -- 320MHz clock SIGNAL clk_4x_logic : std_logic; --! normally 160MHz SIGNAL clk_logic_xtal : std_logic; -- ! 40MHz clock from onboard xtal SIGNAL data_strobe : std_logic; -- goes high when data ready to load into event buffer SIGNAL dout : std_logic; SIGNAL dout1 : std_logic; SIGNAL event_data : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0); signal ipbww: ipb_wbus_array(N_SLAVES - 1 downto 0); signal ipbrr: ipb_rbus_array(N_SLAVES - 1 downto 0); SIGNAL logic_clocks_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic SIGNAL logic_reset : std_logic; SIGNAL overall_trigger : std_logic; --! goes high to load trigger data SIGNAL overall_veto : std_logic; --! Halts triggers when high SIGNAL postVetoTrigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe) SIGNAL postVetotrigger : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active and enabled --trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet. SIGNAL rst_fifo_o : std_logic; --! rst signal to first level fifos SIGNAL s_edge_fall_times : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe) SIGNAL s_edge_falling : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge SIGNAL s_edge_rise_times : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe) SIGNAL s_edge_rising : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge --SIGNAL s_i2c_scl_enb : std_logic; --SIGNAL s_i2c_sda_enb : std_logic; SIGNAL s_shutter : std_logic; --! shutter signal from TimePix, retimed onto local clock SIGNAL s_triggerLogic_reset : std_logic; SIGNAL shutter_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0); SIGNAL shutter_i : std_logic; SIGNAL spill_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0); SIGNAL spill_i : std_logic; SIGNAL strobe_8x_logic : std_logic; --! Pulses one cycle every 4 of 16x clock. SIGNAL strobe_4x_logic : std_logic; -- one pulse every 4 cycles of clk_4x SIGNAL trigger_count : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0); type myTrigArray is array (g_NUM_DUTS-1 downto 0) of std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0); signal TrigNArray : myTrigArray; SIGNAL TriggerNumber : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0); SIGNAL TriggerNumberStrobe : std_logic_vector(g_NUM_DUTS-1 downto 0); SIGNAL stretchFlags : std_logic_vector(g_NUM_DUTS-1 downto 0) := "0011"; -- ! define which dummyDUT have their busy line stretched SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe) SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0); SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy signal ctrl, stat: ipb_reg_v(0 downto 0); --My signals --SIGNAL busy_toggle_o : std_logic_vector(g_NUM_DUTS-1 downto 0); ---------------------------------------------- ---------------------------------------------- component DUTInterfaces generic( g_NUM_DUTS : positive := 4;-- <- was 3 g_IPBUS_WIDTH : positive := 32 ); port ( clk_4x_logic_i : IN std_logic ; strobe_4x_logic_i : IN std_logic ; --! goes high every 4th clock cycle trigger_counter_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset trigger_i : IN std_logic ; --! goes high when trigger logic issues a trigger reset_or_clk_to_dut_i : IN std_logic ; --! Synchronization signal. Passed TO DUT pins shutter_to_dut_i : IN std_logic ; --! Goes high TO indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high -- IPBus signals. ipbus_clk_i : IN std_logic ; ipbus_i : IN ipb_wbus ; --! Signals from IPBus core TO slave ipbus_reset_i : IN std_logic ; ipbus_o : OUT ipb_rbus ; --! signals from slave TO IPBus core -- Signals to/from DUT busy_from_dut : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! BUSY input from DUTs busy_to_dut : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! BUSY input to DUTs (single ended) clk_from_dut : IN std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O reset_to_dut: OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Replaces reset_or_clk_to_dut trigger_to_dut : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger output shutter_to_dut : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Shutter output veto_o : OUT std_logic ); end component DUTInterfaces; ---------------------------------------------- ---------------------------------------------- component Dummy_DUT Port ( CLK : in STD_LOGIC; --! this is the USB clock. RST : in STD_LOGIC; --! Synchronous clock Trigger : in STD_LOGIC; --! Trigger from TLU stretchBusy: in STD_LOGIC; --! flag: if 1 extend the BUSY signal Busy : out STD_LOGIC; --! Busy to TLU DUTClk : out STD_LOGIC; --! clock from DUT TriggerNumber : out STD_LOGIC_VECTOR(31 downto 0); TriggerNumberStrobe : out STD_LOGIC; FSM_Error : out STD_LOGIC ); end component; ---------------------------------------------- ---------------------------------------------- COMPONENT eventBuffer GENERIC ( g_EVENT_DATA_WIDTH : positive := 32; g_IPBUS_WIDTH : positive := 32; g_READ_COUNTER_WIDTH : positive := 16 ); PORT ( clk_4x_logic_i : IN std_logic ; data_strobe_i : IN std_logic ; -- Indicates data TO transfer event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0); ipbus_clk_i : IN std_logic ; ipbus_i : IN ipb_wbus ; ipbus_reset_i : IN std_logic ; strobe_4x_logic_i : IN std_logic ; --trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet. rst_fifo_o : OUT std_logic ; --! rst signal TO first level fifos buffer_full_o : OUT std_logic ; --! Goes high when event buffer almost full ipbus_o : OUT ipb_rbus ; logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic ); END COMPONENT eventBuffer; ---------------------------------------------- ---------------------------------------------- -- COMPONENT eventFormatter -- GENERIC ( -- g_EVENT_DATA_WIDTH : positive := 64; -- g_IPBUS_WIDTH : positive := 32; -- g_COUNTER_TRIG_WIDTH : positive := 32; -- g_COUNTER_WIDTH : positive := 12; -- g_EVTTYPE_WIDTH : positive := 4; --! Width of the event type word -- --g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...) -- g_NUM_EDGE_INPUTS : positive := 4; --! Number of edge inputs -- g_NUM_TRIG_INPUTS : positive := 6 --! Number of trigger inputs (POSSIBLY WRONG!) -- ); -- PORT ( -- clk_4x_logic_i : IN std_logic ; --! Rising edge active -- ipbus_clk_i : IN std_logic ; -- logic_strobe_i : IN std_logic ; --! Pulses high once every 4 cycles of clk_4x_logic -- logic_reset_i : IN std_logic ; --! goes high TO reset counters. Synchronous with clk_4x_logic -- rst_fifo_i : IN std_logic ; --! Goes high TO reset FIFOs -- buffer_full_i : IN std_logic ; --! Goes high when output fifo full -- trigger_i : IN std_logic ; --! goes high TO load trigger data. One cycle of clk_4x_logic -- trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Array of trigger times ( w.r.t. logic_strobe) -- trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! high for each input that "fired" -- trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Trigger count -- shutter_i : IN std_logic ; -- shutter_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0); -- spill_i : IN std_logic ; -- spill_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0); -- edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when rising edge -- edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when falling edge -- edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe) -- edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe) -- ipbus_i : IN ipb_wbus ; -- ipbus_o : OUT ipb_rbus ; -- data_strobe_o : OUT std_logic ; --! goes high when data ready TO load into event buffer -- event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0); -- reset_timestamp_i : IN std_logic ; --! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o -- reset_timestamp_o : OUT std_logic --! Goes high for one clock cycle of clk_4x_logic when timestamp reset -- ); -- END COMPONENT eventFormatter; ---------------------------------------------- ---------------------------------------------- COMPONENT logic_clocks GENERIC ( g_USE_EXTERNAL_CLK : integer := 1 ); PORT ( ipbus_clk_i : IN std_logic ; ipbus_i : IN ipb_wbus ; ipbus_reset_i : IN std_logic ; Reset_i : IN std_logic ; clk_logic_xtal_i : IN std_logic ; -- ! 40MHz clock from onboard xtal clk_8x_logic_o : OUT std_logic ; -- 640MHz clock clk_4x_logic_o : OUT std_logic ; -- 160MHz clock ipbus_o : OUT ipb_rbus ; strobe_8x_logic_o : OUT std_logic ; -- strobes once every 4 cycles of clk_16x strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x --extclk_p_b : INOUT std_logic ; -- either external clock in, or a clock being driven out --extclk_n_b : INOUT std_logic ; DUT_clk_o : OUT std_logic ; logic_clocks_locked_o : OUT std_logic ; logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic ); END COMPONENT logic_clocks; ---------------------------------------------- COMPONENT i2c_master PORT ( i2c_scl_i : IN std_logic; i2c_sda_i : IN std_logic; ipbus_clk_i : IN std_logic; ipbus_i : IN ipb_wbus; ipbus_reset_i : IN std_logic; i2c_scl_enb_o : OUT std_logic; i2c_sda_enb_o : OUT std_logic; ipbus_o : OUT ipb_rbus ); END COMPONENT i2c_master; -- component clk_wiz_0 -- port -- (-- Clock in ports -- clk_in1 : in std_logic; -- -- Clock out ports -- clk_out1 : out std_logic; -- -- Status and control signals -- reset : in std_logic; -- locked : out std_logic -- ); -- end component; -- Optional embedded configurations -- pragma synthesis_off FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces; --FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface; FOR ALL : T0_Shutter_Iface USE ENTITY work.T0_Shutter_Iface; FOR ALL : eventBuffer USE ENTITY work.eventBuffer; FOR ALL : eventFormatter USE ENTITY work.eventFormatter; FOR ALL : i2c_master USE ENTITY work.i2c_master;--
'0');
-- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
shutter_i <= '0';
-- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
shutter_cnt_i <= (OTHERS => '0');
-- ModuleWare code(v1.12) for instance 'I17' of 'gnd'
dout1 <= '0';
-- ModuleWare code(v1.12) for instance 'I18' of 'gnd'
dout <= '0';
-- ModuleWare code(v1.12) for instance 'I19' of 'merge'
--gpio_hdr <= dout1 & dout & s_shutter & T0_o;
-- ModuleWare code(v1.12) for instance 'I8' of 'sor'
overall_veto <= buffer_full_o OR veto_o;
-- ModuleWare code(v1.12) for instance 'I16' of 'sor'
s_triggerLogic_reset <= logic_reset OR T0_o;
i2c_reset <= '1';
clk_gen_rst <= '1';
gpio <= strobe_8x_logic;
sysclk_50_o_p <= '0';
sysclk_50_o_n <= '0';
--busy_o <= std_logic_vector(to_unsigned(0, busy_o'length));
--busy_o <= '000000';
--sysclk_40_o_p <= sysclk;
------------------------------------------
infra: entity work.enclustra_ax3_pm3_infra
port map(
sysclk => clk_encl_buf,
clk_ipb_o => clk_ipb,
rst_ipb_o => rst_ipb,
rst_125_o => phy_rst_e,
clk_200_o => clk_200,
nuke => nuke,
soft_rst => soft_rst,
leds => inf_leds,
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
mac_addr => mac_addr,
ip_addr => ip_addr,
ipb_in => ipb_in,
ipb_out => ipb_out
);
--leds <= not ('0' & userled & inf_leds); -- Check this.
phy_rstn <= not phy_rst_e;
-- mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
-- ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
mac_addr <= X"020ddba1151d"; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c81d"; -- 192.168.200.29
------------------------------------------
I1 : entity work.ipbus_ctrlreg_v
port map(
clk => clk_ipb,
reset => rst_ipb,
ipbus_in => ipbww(N_SLV_CTRL_REG),
ipbus_out => ipbrr(N_SLV_CTRL_REG),
d => stat,
q => ctrl
);
stat(0) <= std_logic_vector(FW_VERSION);-- <-Let's use this as firmware revision number
soft_rst <= ctrl(0)(0);
nuke <= ctrl(0)(1);
------------------------------------------
I2 : entity work.ipbus_fabric_sel
generic map(
NSLV => N_SLAVES,
SEL_WIDTH => IPBUS_SEL_WIDTH)
port map(
ipb_in => ipb_out,
ipb_out => ipb_in,
sel => ipbus_sel_ipbus_example(ipb_out.ipb_addr),
ipb_to_slaves => ipbww,
ipb_from_slaves => ipbrr
);
------------------------------------------
I3 : i2c_master
PORT MAP (
i2c_scl_i => i2c_scl_b,
i2c_sda_i => i2c_sda_b,
ipbus_clk_i => clk_ipb,
ipbus_i => ipbww(N_SLV_I2C_0),
ipbus_reset_i => rst_ipb,
i2c_scl_enb_o => s_i2c_scl_enb,
i2c_sda_enb_o => s_i2c_sda_enb,
ipbus_o => ipbrr(N_SLV_I2C_0)
);
----------------------------------------------
I4 : logic_clocks
GENERIC MAP (
g_USE_EXTERNAL_CLK => 0
)
PORT MAP (
ipbus_clk_i => clk_ipb,
ipbus_i => ipbww(N_SLV_LGCCLK),
ipbus_reset_i => rst_ipb,
Reset_i => logic_clocks_reset,
clk_logic_xtal_i => sysclk_40, -- Not sure this is correct
clk_8x_logic_o => clk_8x_logic,
clk_4x_logic_o => clk_4x_logic,
ipbus_o => ipbrr(N_SLV_LGCCLK),
strobe_8x_logic_o => strobe_8x_logic,
strobe_4x_logic_o => strobe_4x_logic,
DUT_clk_o => open,
logic_clocks_locked_o => leds(3),
logic_reset_o => logic_reset
);
------------------------------------------
-- I6 : eventFormatter
-- GENERIC MAP (
-- g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
-- g_IPBUS_WIDTH => g_IPBUS_WIDTH,
-- g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
-- g_COUNTER_WIDTH => 12,
-- g_EVTTYPE_WIDTH => 4, --! Width of the event type word
-- --g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
-- g_NUM_EDGE_INPUTS => g_NUM_EDGE_INPUTS, --! Number of edge inputs
-- g_NUM_TRIG_INPUTS => g_NUM_TRIG_INPUTS --! Number of trigger inputs
-- )
-- PORT MAP (
-- clk_4x_logic_i => clk_4x_logic,
-- ipbus_clk_i => clk_ipb,
-- logic_strobe_i => strobe_4x_logic,
-- logic_reset_i => logic_reset,
-- rst_fifo_i => rst_fifo_o,
-- buffer_full_i => buffer_full_o,
-- trigger_i => overall_trigger,
-- trigger_times_i => postVetoTrigger_times,
-- trigger_inputs_fired_i => postVetotrigger,
-- trigger_cnt_i => trigger_count,
-- shutter_i => shutter_i,
-- shutter_cnt_i => shutter_cnt_i,
-- spill_i => spill_i,
-- spill_cnt_i => spill_cnt_i,
-- edge_rise_i => s_edge_rising,
-- edge_fall_i => s_edge_falling,
-- edge_rise_time_i => s_edge_rise_times,
-- edge_fall_time_i => s_edge_fall_times,
-- ipbus_i => ipbww(N_SLV_EVFMT),
-- ipbus_o => ipbrr(N_SLV_EVFMT),
-- data_strobe_o => data_strobe,
-- event_data_o => event_data,
-- reset_timestamp_i => T0_o,
-- reset_timestamp_o => OPEN
-- );
------------------------------------------
I7 : eventBuffer
GENERIC MAP (
g_EVENT_DATA_WIDTH => 32,
g_IPBUS_WIDTH => g_IPBUS_WIDTH,
g_READ_COUNTER_WIDTH => 13
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
--clk_4x_logic_i => sysclk_40,
data_strobe_i => TriggerNumberStrobe(0),
event_data_i => TrigNArray(0),
ipbus_clk_i => clk_ipb,
ipbus_i => ipbww(N_SLV_EVBUF),
ipbus_reset_i => rst_ipb,
strobe_4x_logic_i => strobe_4x_logic,
rst_fifo_o => rst_fifo_o,
buffer_full_o => buffer_full_o,
ipbus_o => ipbrr(N_SLV_EVBUF),
logic_reset_i => logic_reset
);
------------------------------------------
-- I9 : DUTInterfaces
-- GENERIC MAP (
-- g_NUM_DUTS => g_NUM_DUTS,
-- g_IPBUS_WIDTH => g_IPBUS_WIDTH
-- )
-- PORT MAP (
-- clk_4x_logic_i => clk_4x_logic,
-- strobe_4x_logic_i => strobe_4x_logic,
-- trigger_counter_i => trigger_count,
-- trigger_i => overall_trigger,
-- reset_or_clk_to_dut_i => T0_o,
-- shutter_to_dut_i => s_shutter,
-- ipbus_clk_i => clk_ipb,
-- ipbus_i => ipbww(N_SLV_DUT),
-- ipbus_reset_i => rst_ipb,
-- ipbus_o => ipbrr(N_SLV_DUT),
-- busy_from_dut => busy_i,
-- busy_to_dut => open,
-- clk_from_dut => dut_clk_i,
-- clk_to_dut => dut_clk_o,
-- --reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
-- --reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
-- reset_to_dut => spare_o,
-- trigger_to_dut => triggers_o,
-- --shutter_to_dut_n_o => shutter_to_dut_n_o,
-- --shutter_to_dut_p_o => shutter_to_dut_p_o,
-- shutter_to_dut => cont_o,
-- veto_o => veto_o
-- );
-------------TEST AREA------------
-- test0: entity work.test_inToOut
-- port map(
-- clk_in => clk_200,
-- busy_in=> busy_i,
-- control_in=> cont_i,
-- trig_in=> triggers_i,
-- clkDut_in=> dut_clk_i,
-- spare_in=> spare_i,
-- busy_out=> busy_o,
-- control_out=> cont_o,
-- trig_out=> triggers_o,
-- clkDut_out=> dut_clk_o,
-- spare_out=> spare_o
-- );
-- dutout0: entity work.DUTs_outputs
-- port map(
-- clk_in => encl_clock50,
-- d_clk_o => dut_clk_o,
-- d_trg_o => triggers_o,
-- d_busy_o => busy_o,
-- d_cont_o => cont_o,
-- d_spare_o => spare_o
-- );
-- clk50_o_fromEnclustra : clk_wiz_0
-- port map (
-- -- Clock in ports
-- clk_in1 => clk_encl_buf, --sysclk_40,
-- -- Clock out ports
-- clk_out1 => encl_clock50,
-- -- Status and control signals
-- reset => '0',
-- locked => open
-- );
----------------------------------------------
OutBlocks:
for iDUT in 0 to g_NUM_DUTS-1 generate
begin
-- generate an instance of the Dummy DUT behind connector 0
DUT_Instance: Dummy_DUT
Port map (
--CLK => clk_4x_logic,--160 Mhz clock
CLK => sysclk_40,
RST => cont_i(iDUT),-- coming from HDMI pin
Trigger => triggers_i(iDUT), --coming from HDMI pin
stretchBusy => stretchFlags(iDUT),
Busy => busy_o(iDUT), --going out on HDMI pin
DUTClk => dut_clk_o(iDUT), --going out on HDMI pin
TriggerNumber => TrigNArray(iDUT),
TriggerNumberStrobe => TriggerNumberStrobe(iDUT),
FSM_Error => open
);
end generate;
------------------------------------------
------------------------------------------
IBUFGDS_inst: IBUFGDS
generic map (
IBUF_LOW_PWR=> false
)
port map (
O => sysclk_40,
I => sysclk_40_i_p,
IB => sysclk_40_i_n
);
------------------------------------------
IBUFG_inst: IBUFG
port map (
O => clk_encl_buf,
I => clk_enclustra--sysclk
);
end rtl;
fmc-mtlu-sw-master/EUDETdummy/scripts/ 0000775 0000000 0000000 00000000000 14436063765 0020151 5 ustar 00root root 0000000 0000000 fmc-mtlu-sw-master/EUDETdummy/scripts/EUDETdummy.py 0000664 0000000 0000000 00000056076 14436063765 0022463 0 ustar 00root root 0000000 0000000 # -*- coding: utf-8 -*-
import uhal;
import pprint;
#from FmcTluI2c import *
import time
from I2CuHal import I2CCore
from si5345 import si5345 # Library for clock chip
from AD5665R import AD5665R # Library for DAC
from PCA9539PW import PCA9539PW # Library for serial line expander
class EUDETdummy:
"""docstring for TLU"""
def __init__(self, dev_name, man_file):
self.dev_name = dev_name
self.manager= uhal.ConnectionManager(man_file)
self.hw = self.manager.getDevice(self.dev_name)
self.nDUTs= 4 #Number of DUT connectors
self.nChannels= 6 #Number of trigger inputs
self.VrefInt= 2.5 #Internal DAC voltage reference
self.VrefExt= 1.3 #External DAC voltage reference
self.intRefOn= False #Internal reference is OFF by default
self.fwVersion = self.hw.getNode("version").read()
self.hw.dispatch()
print "EUDUMMY FIRMWARE VERSION= " , hex(self.fwVersion)
# Instantiate a I2C core to configure components
self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
#self.TLU_I2C.state()
enableCore= True #Only need to run this once, after power-up
self.enableCore()
# Instantiate clock chip
self.zeClock=si5345(self.TLU_I2C, 0x68)
res= self.zeClock.getDeviceVersion()
self.zeClock.checkDesignID()
# Instantiate DACs and configure them to use reference based on TLU setting
self.zeDAC1=AD5665R(self.TLU_I2C, 0x13)
self.zeDAC2=AD5665R(self.TLU_I2C, 0x1F)
self.zeDAC1.setIntRef(self.intRefOn)
self.zeDAC2.setIntRef(self.intRefOn)
# Instantiate the serial line expanders and configure them to default values
self.IC6=PCA9539PW(self.TLU_I2C, 0x74)
self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
self.IC6.setIOReg(0, 0x00)# 0= output, 1= input
self.IC6.setOutputs(0, 0x88)# If output, set to XX
self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
self.IC6.setIOReg(1, 0x00)# 0= output, 1= input
self.IC6.setOutputs(1, 0x88)# If output, set to XX
self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
self.IC7.setInvertReg(0, 0x00)# 0= normal, 1= inverted
self.IC7.setIOReg(0, 0x00)# 0= output, 1= input
self.IC7.setOutputs(0, 0x0F)# If output, set to XX
self.IC7.setInvertReg(1, 0x00)# 0= normal, 1= inverted
self.IC7.setIOReg(1, 0x00)# 0= output, 1= input
self.IC7.setOutputs(1, 0x50)# If output, set to XX
##################################################################################################################################
##################################################################################################################################
def DUTOutputs(self, dutN, enable=False, verbose=False):
## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
## NOTE: CLK direction must be defined separately using DUTClkSrc
if (dutN < 0) | (dutN> (self.nDUTs-1)):
print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
return -1
bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
print " Setting DUT:", dutN, "to", enable
if verbose:
print "\tBank", bank, "Nibble", nibble
res= self.IC6.getIOReg(bank)
oldStatus= res[0]
mask= 0xF << 4*nibble
newStatus= oldStatus & (~mask)
if (not enable): # we want to write 0 to activate the outputs so check opposite of "enable"
newStatus |= mask
if verbose:
print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
self.IC6.setIOReg(bank, newStatus)
return newStatus
def DUTClkSrc(self, dutN, clkSrc=0, verbose= False):
## Allows to choose the source of the clock signal sent to the DUTs over HDMI
## clkSrc= 0: clock disabled
## clkSrc= 1: clock from Si5345
## clkSrc=2: clock from FPGA
if (dutN < 0) | (dutN> (self.nDUTs-1)):
print "\tERROR: DUTClkSrc. The DUT number must be comprised between 0 and ", self.nDUTs-1
return -1
if (clkSrc < 0) | (clkSrc> 2):
print "\tERROR: DUTClkSrc. clkSrc can only be 0 (disabled), 1 (Si5345) or 2 (FPGA)"
return -1
bank=0
maskLow= 1 << (1* dutN) #CLK FROM FPGA
maskHigh= 1<< (1* dutN +4) #CLK FROM Si5345
mask= maskLow | maskHigh
res= self.IC7.getIOReg(bank)
oldStatus= res[0]
newStatus= oldStatus & ~mask #set both bits to zero
outStat= ""
if clkSrc==0:
newStatus = newStatus | mask
outStat= "disabled"
elif clkSrc==1:
newStatus = newStatus | maskLow
outStat= "Si5435"
elif clkSrc==2:
newStatus= newStatus | maskHigh
outStat= "FPGA"
print " Setting DUT:", dutN, "clock source to", outStat
if verbose:
print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
self.IC7.setIOReg(bank, newStatus)
return newStatus
def enableClkLEMO(self, enable= False, verbose= False):
## Enable or disable the output clock to the differential LEMO output
bank=1
mask= 0x10
res= self.IC7.getIOReg(bank)
oldStatus= res[0]
newStatus= oldStatus & ~mask
outStat= "enabled"
if (not enable): #A 0 activates the output. A 1 disables it.
newStatus= newStatus | mask
outStat= "disabled"
print " Clk LEMO", outStat
if verbose:
print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
self.IC7.setIOReg(bank, newStatus)
return newStatus
def enableCore(self):
## At power up the Enclustra I2C lines are disabled (tristate buffer is off).
## This function enables the lines. It is only required once.
mystop=True
print " Enabling I2C bus (expect 127):"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
self.TLU_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
self.TLU_I2C.write(myslave, mycmd, mystop)
res= self.TLU_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
def getAllChannelsCounts(self):
chCounts=[]
for ch in range (0,self.nChannels):
chCounts.append(int(self.getChCount(ch)))
return chCounts
def getChStatus(self):
inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
self.hw.dispatch()
print "\tInput status= " , hex(inputStatus)
return inputStatus
def getChCount(self, channel):
regString= "triggerInputs.ThrCount"+ str(channel)+"R"
count = self.hw.getNode(regString).read()
self.hw.dispatch()
print "\tCh", channel, "Count:" , count
return count
def getClockStatus(self):
clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
self.hw.dispatch()
print " CLOCK STATUS [expected 1]"
print "\t", hex(clockStatus)
if ( clockStatus == 0 ):
"ERROR: Clocks in EUDUMMY FPGA are not locked."
return clockStatus
def getDUTmask(self):
DUTMaskR = self.hw.getNode("DUTInterfaces.DutMaskR").read()
self.hw.dispatch()
print "\tDUTMask read back as:" , hex(DUTMaskR)
return DUTMaskR
def getExternalVeto(self):
extVeto= self.hw.getNode("triggerLogic.ExternalTriggerVetoR").read()
self.hw.dispatch()
print "\tEXTERNAL Veto read back as:", hex(extVeto)
return extVeto
def getFifoData(self, nWords):
#fifoData= self.hw.getNode("eventBuffer.EventFifoData").read()
fifoData= self.hw.getNode("eventBuffer.EventFifoData").readBlock (nWords);
self.hw.dispatch()
#print "\tFIFO Data:", hex(fifoData)
return fifoData
def getFifoLevel(self):
FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
self.hw.dispatch()
print "\tFIFO level read back as:", hex(FifoFill)
return FifoFill
def getFifoCSR(self):
FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
self.hw.dispatch()
print "\tFIFO CSR read back as:", hex(FifoCSR)
return FifoCSR
def getInternalTrg(self):
trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
self.hw.dispatch()
print "\tTrigger frequency read back as:", trigIntervalR, "Hz"
return trigIntervalR
def getMode(self):
DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
self.hw.dispatch()
print "\tDUT mode read back as:" , hex(DUTInterfaceModeR)
return DUTInterfaceModeR
def getModeModifier(self):
DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
self.hw.dispatch()
print "\tDUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR)
return DUTInterfaceModeModifierR
def getSN(self):
epromcontent=self.readEEPROM(0xfa, 6)
print " EUDET dummy serial number (EEPROM):"
result="\t"
for iaddr in epromcontent:
result+="%02x "%(iaddr)
print result
return epromcontent
def getPostVetoTrg(self):
triggerN = self.hw.getNode("triggerLogic.PostVetoTriggersR").read()
self.hw.dispatch()
print "\tPOST VETO TRIGGER NUMBER:", (triggerN)
return triggerN
def getPulseDelay(self):
pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
self.hw.dispatch()
print "\tPulse delay read back as:", hex(pulseDelayR)
return pulseDelayR
def getPulseStretch(self):
pulseStretchR = self.hw.getNode("triggerLogic.PulseStretchR").read()
self.hw.dispatch()
print "\tPulse stretch read back as:", hex(pulseStretchR)
return pulseStretchR
def getRecordDataStatus(self):
RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
self.hw.dispatch()
print "\tData recording:", RecordStatus
return RecordStatus
def getTriggerVetoStatus(self):
trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
self.hw.dispatch()
print "\tTrigger veto status read back as:", trgVetoStatus
return trgVetoStatus
def getTrgPattern(self):
triggerPattern_low = self.hw.getNode("triggerLogic.TriggerPattern_lowR").read()
triggerPattern_high = self.hw.getNode("triggerLogic.TriggerPattern_highR").read()
self.hw.dispatch()
print "\tTrigger pattern read back as: 0x%08X 0x%08X" %(triggerPattern_high, triggerPattern_low)
return triggerPattern_low, triggerPattern_high
def getVetoDUT(self):
IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
self.hw.dispatch()
print "\tIgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR)
return IgnoreDUTBusyR
def getVetoShutters(self):
IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
self.hw.dispatch()
print "\tIgnoreShutterVeto read back as:" , IgnoreShutterVeto
return IgnoreShutterVeto
def pulseT0(self):
cmd = int("0x1",16)
self.hw.getNode("Shutter.PulseT0").write(cmd)
self.hw.dispatch()
print "\tPulsing T0"
def readEEPROM(self, startadd, bytes):
mystop= 1
time.sleep(0.1)
myaddr= [startadd]#0xfa
self.TLU_I2C.write( 0x50, [startadd], mystop)
res= self.TLU_I2C.read( 0x50, bytes)
return res
def resetClock(self):
# Set the RST pin from the PLL to 1
print " Clocks reset"
cmd = int("0x1",16)
self.hw.getNode("logic_clocks.LogicRst").write(cmd)
self.hw.dispatch()
def resetClocks(self):
#Reset clock PLL
self.resetClock()
#Get clock status after reset
self.getClockStatus()
#Restore clock PLL
self.restoreClock()
#Get clock status after restore
self.getClockStatus()
#Get serdes status
self.getChStatus()
def resetCounters(self):
cmd = int("0x2", 16) #write 0x2 to reset
self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
self.hw.dispatch()
cmd = int("0x0", 16) #write 0x2 to reset
self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
self.hw.dispatch()
#print "Trigger Reset: 0x%X" % restatus
print "\tTrigger counters reset"
def resetSerdes(self):
cmd = int("0x3",16)
self.setChStatus(cmd)
inputStatus= self.getChStatus()
print "\t Input status during reset = " , hex(inputStatus)
cmd = int("0x0",16)
self.setChStatus(cmd)
inputStatus= self.getChStatus()
print "\t Input status after reset = " , hex(inputStatus)
cmd = int("0x4",16)
self.setChStatus(cmd)
inputStatus= self.getChStatus()
print "\t Input status during calibration = " , hex(inputStatus)
cmd = int("0x0",16)
self.setChStatus(cmd)
inputStatus= self.getChStatus()
print "\t Input status after calibration = " , hex(inputStatus)
def restoreClock(self):
# Set the RST pin from the PLL to 0
print " Clocks restore"
cmd = int("0x0",16)
self.hw.getNode("logic_clocks.LogicRst").write(cmd)
self.hw.dispatch()
def setChStatus(self, cmd):
self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
self.hw.dispatch()
print " INPUT STATUS SET TO= " , hex(inputStatus)
def setClockStatus(self, cmd):
# Only use this for testing. The clock source is actually selected in the Si5345.
self.hw.getNode("logic_clocks.LogicClocksCSR").write(cmd)
self.hw.dispatch()
def setDUTmask(self, DUTMask):
print " DUT MASK ENABLING: Mask= " , hex(DUTMask)
self.hw.getNode("DUTInterfaces.DutMaskW").write(DUTMask)
self.hw.dispatch()
self.getDUTmask()
def setFifoCSR(self, cmd):
self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
self.hw.dispatch()
self.getFifoCSR()
def setInternalTrg(self, triggerInterval):
print " TRIGGERS INTERNAL:"
if triggerInterval == 0:
internalTriggerFreq = 0
print "\tdisabled"
else:
internalTriggerFreq = 160000.0/triggerInterval
print "\t Setting:", internalTriggerFreq, "Hz"
self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
self.hw.dispatch()
self.getInternalTrg()
def setMode(self, mode):
print " DUT MODE SET TO: ", hex(mode)
self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
self.hw.dispatch()
self.getMode()
def setModeModifier(self, modifier):
print " DUT MODE MODIFIER:", hex(modifier)
self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
self.hw.dispatch()
self.getModeModifier()
def setPulseDelay(self, pulseDelay):
print " TRIGGER DELAY SET TO", hex(pulseDelay), "[Units= 160MHz clock, 5-bit values (one per input) packed in to 32-bit word]"
self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
self.hw.dispatch()
self.getPulseDelay()
def setPulseStretch(self, pulseStretch):
print " INPUT COINCIDENCE WINDOW SET TO", hex(pulseStretch) ,"[Units= 160MHz clock cycles, 5-bit values (one per input) packed in to 32-bit word]"
self.hw.getNode("triggerLogic.PulseStretchW").write(pulseStretch)
self.hw.dispatch()
self.getPulseStretch()
def setRecordDataStatus(self, status=False):
print " Data recording set:"
self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
self.hw.dispatch()
self.getRecordDataStatus()
def setTriggerVetoStatus(self, status=False):
self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
self.hw.dispatch()
self.getTriggerVetoStatus()
def setTrgPattern(self, triggerPatternH, triggerPatternL):
triggerPatternL &= 0xffffffff
triggerPatternH &= 0xffffffff
print " TRIGGER PATTERN (for external triggers) SET TO 0x%08X 0x%08X. Two 32-bit words." %(triggerPatternH, triggerPatternL)
self.hw.getNode("triggerLogic.TriggerPattern_lowW").write(triggerPatternL)
self.hw.getNode("triggerLogic.TriggerPattern_highW").write(triggerPatternH)
self.hw.dispatch()
self.getTrgPattern()
def setVetoDUT(self, ignoreDUTBusy):
print " VETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy)
self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
self.hw.dispatch()
self.getVetoDUT()
def setVetoShutters(self, newState):
if newState:
print " IgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER"
cmd= int("0x0",16)
else:
print " IgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER"
cmd= int("0x1",16)
self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
self.hw.dispatch()
self.getVetoShutters()
def writeThreshold(self, DACtarget, Vtarget, channel):
#Writes the threshold. The DAC voltage differs from the threshold voltage because
#the range is shifted to be symmetrical around 0V.
#Check if the DACs are using the internal reference
if (self.intRefOn):
Vref= self.VrefInt
else:
Vref= self.VrefExt
#Calculate offset voltage (because of the following shifter)
Vdac= ( Vtarget + Vref ) / 2
print" THRESHOLD setting:"
if channel==7:
print "\tCH: ALL"
else:
print "\tCH:", channel
print "\tTarget V:", Vtarget
dacValue = 0xFFFF * (Vdac / Vref)
DACtarget.writeDAC(int(dacValue), channel, True)
def parseFifoData(self, fifoData, nEvents, verbose):
#for index in range(0, len(fifoData)-1, 6):
outList= []
for index in range(0, (nEvents)*6, 6):
word0= (fifoData[index] << 32) + fifoData[index + 1]
word1= (fifoData[index + 2] << 32) + fifoData[index + 3]
word2= (fifoData[index + 4] << 32) + fifoData[index + 5]
evType= (fifoData[index] & 0xF0000000) >> 28
inTrig= (fifoData[index] & 0x0FFF0000) >> 16
tStamp= ((fifoData[index] & 0x0000FFFF) << 32) + fifoData[index + 1]
fineTs= fifoData[index + 2]
evNum= fifoData[index + 3]
fineTsList=[-1]*12
fineTsList[3]= (fineTs & 0x000000FF)
fineTsList[2]= (fineTs & 0x0000FF00) >> 8
fineTsList[1]= (fineTs & 0x00FF0000) >> 16
fineTsList[0]= (fineTs & 0xFF000000) >> 24
fineTsList[7]= (fifoData[index + 4] & 0x000000FF)
fineTsList[6]= (fifoData[index + 4] & 0x0000FF00) >> 8
fineTsList[5]= (fifoData[index + 4] & 0x00FF0000) >> 16
fineTsList[4]= (fifoData[index + 4] & 0xFF000000) >> 24
fineTsList[11]= (fifoData[index + 5] & 0x000000FF)
fineTsList[10]= (fifoData[index + 5] & 0x0000FF00) >> 8
fineTsList[9]= (fifoData[index + 5] & 0x00FF0000) >> 16
fineTsList[8]= (fifoData[index + 5] & 0xFF000000) >> 24
if verbose:
print "====== EVENT", evNum, "================================================="
print "[", hex(word0), "]", "\t TYPE", hex(evType), "\t TRIGGER", hex(inTrig), "\t TIMESTAMP", (tStamp)
print "[",hex(word1), "]", "\tEV NUM", evNum, "\tFINETS[0,3]", hex(fineTs)
print "[",hex(word2), "]", "\tFINETS[4,11]", hex(word2)
print fineTsList
fineTsList.insert(0, tStamp)
fineTsList.insert(0, evNum)
#print fineTsList
outList.insert(len(outList), fineTsList)
printdata= False
if (printdata):
print "=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-="
print "EN#\tCOARSE_TS\tFINE_TS0...FINE_TS11"
pprint.pprint(outList)
return outList
##################################################################################################################################
##################################################################################################################################
def initialize(self):
print "\nEUDUMMY INITIALIZING..."
# We need to pass it listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage
#READ CONTENT OF EPROM VIA I2C
self.getSN()
#
# #SET DACs
targetV= -0.12
DACchannel= 7
self.writeThreshold(self.zeDAC1, targetV, DACchannel, )
self.writeThreshold(self.zeDAC2, targetV, DACchannel, )
#
# #ENABLE/DISABLE HDMI OUTPUTS
#self.DUTOutputs(0, True, False)
#self.DUTOutputs(1, True, False)
#self.DUTOutputs(2, True, False)
#self.DUTOutputs(3, True, False)
## ENABLE/DISABLE LEMO CLOCK OUTPUT
#self.enableClkLEMO(True, False)
#
# #Check clock status
self.getClockStatus()
resetClocks = 0
resetSerdes = 0
resetCounters= 0
if resetClocks:
self.resetClocks()
self.getClockStatus()
if resetSerdes:
self.resetSerdes()
if resetCounters:
self.resetCounters()
print "EUDUMMY INITIALIZED"
##################################################################################################################################
##################################################################################################################################
def start(self, logtimestamps=False):
print "EUDUMMY STARTING..."
print " EUDUMMY RUNNING"
##################################################################################################################################
##################################################################################################################################
def stop(self):
print "EUDUMMY STOPPING..."
print " EUDUMMY STOPPED"
fmc-mtlu-sw-master/EUDETdummy/scripts/EUDETdummyaddrmap.xml 0000664 0000000 0000000 00000012517 14436063765 0024154 0 ustar 00root root 0000000 0000000