Details: This error message is generated whenever part names are changed for components in either the subdesign or the root design after the subdesign has been packaged in the root design. The change in part names can occur due to one of the following reasons: change in component definition properties; selection of a different PPT row for the component (by using the Modify command in Design Entry HDL); use of COMP_NAME or COMP_NAME_SUFFIX properties.
This message is not generated if the subdesign was packaged using USE_SUBDESIGN. Packager-XL picks up the part names from the previous run of the root design packaging and does not read the subdesign state file again, whereas, in the case of FORCE_SUBDESIGN, the part names are read from the subdesign state file for each packaging run.
")
)
(
(tool "Packager-XL")
(class "LOGICAL")
(severity 30)
(error_num 289)
(short_msg "INFO(SPCODD-289): Part name conflict found for 'CN2_9'. This may be updated during packaging.")
(long_msg "INFO(SPCODD-289): Part name conflict found for 'CN2_9'. This may be updated during packaging.
Sub Design Part Name : CAPN4I-1UF,16V,X5R,GNM21
Root Design Part Name : CAPCERSMDCL2_0402-1UF,10V
Details: This error message is generated whenever part names are changed for components in either the subdesign or the root design after the subdesign has been packaged in the root design. The change in part names can occur due to one of the following reasons: change in component definition properties; selection of a different PPT row for the component (by using the Modify command in Design Entry HDL); use of COMP_NAME or COMP_NAME_SUFFIX properties.
This message is not generated if the subdesign was packaged using USE_SUBDESIGN. Packager-XL picks up the part names from the previous run of the root design packaging and does not read the subdesign state file again, whereas, in the case of FORCE_SUBDESIGN, the part names are read from the subdesign state file for each packaging run.
")
)
(
(tool "Packager-XL")
(class "LOGICAL")
(severity 30)
(error_num 289)
(short_msg "INFO(SPCODD-289): Part name conflict found for 'QZ1_9'. This may be updated during packaging.")
(long_msg "INFO(SPCODD-289): Part name conflict found for 'QZ1_9'. This may be updated during packaging.
Sub Design Part Name : BF-100.000MBE-T-GND=GND_SIGNALA
Root Design Part Name : BF-50.000MBE-T-GND=GND_SIGNAL,A
Details: This error message is generated whenever part names are changed for components in either the subdesign or the root design after the subdesign has been packaged in the root design. The change in part names can occur due to one of the following reasons: change in component definition properties; selection of a different PPT row for the component (by using the Modify command in Design Entry HDL); use of COMP_NAME or COMP_NAME_SUFFIX properties.
This message is not generated if the subdesign was packaged using USE_SUBDESIGN. Packager-XL picks up the part names from the previous run of the root design packaging and does not read the subdesign state file again, whereas, in the case of FORCE_SUBDESIGN, the part names are read from the subdesign state file for each packaging run.
")
)
(
(tool "Packager-XL")
...
...
@@ -1029,5 +1001,137 @@
The schematic for this module might have been updated with a different root design. Update the subdesign state file by packaging this module as the root design.
")
)
(
(tool "Packager-XL")
(class "LOGICAL")
(severity 40)
(error_num 228)
(short_msg "ERROR(SPCODD-228): Cannot package the following primitive instance in any section of the physical part 'FIDUCIAL'.")
(long_msg "ERROR(SPCODD-228): Cannot package the following primitive instance in any section of the physical part 'FIDUCIAL'.
The primitive instance has pins which does not match the section definition in chips.prt. Check the pin definitions for each section in the chips.prt file. Regenerate the netlist and rerun packager.
Details: This error occurs when the entity/verilog.v file is not in sync with the physical part used in the design and Packager-XL fails to package the primitive instance in any of the sections of the physical part. Rewrite the part symbols with the new name. This will create a new entity/verilog.v file and then package the design.
The primitive instance has pins which does not match the section definition in chips.prt. Check the pin definitions for each section in the chips.prt file. Regenerate the netlist and rerun packager.
Details: This error occurs when the entity/verilog.v file is not in sync with the physical part used in the design and Packager-XL fails to package the primitive instance in any of the sections of the physical part. Rewrite the part symbols with the new name. This will create a new entity/verilog.v file and then package the design.
The primitive instance has pins which does not match the section definition in chips.prt. Check the pin definitions for each section in the chips.prt file. Regenerate the netlist and rerun packager.
Details: This error occurs when the entity/verilog.v file is not in sync with the physical part used in the design and Packager-XL fails to package the primitive instance in any of the sections of the physical part. Rewrite the part symbols with the new name. This will create a new entity/verilog.v file and then package the design.
The primitive instance has pins which does not match the section definition in chips.prt. Check the pin definitions for each section in the chips.prt file. Regenerate the netlist and rerun packager.
Details: This error occurs when the entity/verilog.v file is not in sync with the physical part used in the design and Packager-XL fails to package the primitive instance in any of the sections of the physical part. Rewrite the part symbols with the new name. This will create a new entity/verilog.v file and then package the design.
The primitive instance has pins which does not match the section definition in chips.prt. Check the pin definitions for each section in the chips.prt file. Regenerate the netlist and rerun packager.
Details: This error occurs when the entity/verilog.v file is not in sync with the physical part used in the design and Packager-XL fails to package the primitive instance in any of the sections of the physical part. Rewrite the part symbols with the new name. This will create a new entity/verilog.v file and then package the design.
The primitive instance has pins which does not match the section definition in chips.prt. Check the pin definitions for each section in the chips.prt file. Regenerate the netlist and rerun packager.
Details: This error occurs when the entity/verilog.v file is not in sync with the physical part used in the design and Packager-XL fails to package the primitive instance in any of the sections of the physical part. Rewrite the part symbols with the new name. This will create a new entity/verilog.v file and then package the design.
