Commit 60cc9054 authored by David Cussans's avatar David Cussans Committed by Juan David Gonzalez Cobas

Changing R53 ( termination resistor for data from CDR ) from XX to 100-Ohms

Changing R94 ( pull-up resistor for clock to DFF ) from 0 to XX
Exported to fmc_tlu_v1f_36.brd
parent 33d4f25c
{ Machine generated file created by SPI }
{ Last modified was 15:56:11 Wednesday, June 10, 2020 }
{ Last modified was 14:14:25 Wednesday, September 02, 2020 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -61,14 +61,14 @@ import_constraints_only_feedback 'OFF'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '1'
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1f_20.brd'
last_board_file 'fmc_tlu_v1f_36.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'YES'
......
......@@ -110,3 +110,7 @@
2019-11-13T11:16:42 ===> "P:/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxnet.dat"
2019-11-13T11:16:42 ===> "P:/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxprt.dat"
2019-11-13T11:16:42 ===> "P:/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstdmlmodels.dat"
2020-09-02T14:13:22 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstchip.dat"
2020-09-02T14:13:22 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxnet.dat"
2020-09-02T14:13:22 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxprt.dat"
2020-09-02T14:13:22 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstdmlmodels.dat"
{ Packager-XL run on 13-Nov-2019 AT 11:16:10 }
{ Packager-XL run on 02-Sep-2020 AT 14:13:12 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page1";
BODY = "24AA025E48","I8": LOCATION = "IC5" #&CDS_LOCATION = "IC5" &SEC = "1" #&CDS_SEC = "1";
......
FILE_TYPE = LIBRARY_PARTS;
{ Packager-XL run on 13-Nov-2019 AT 11:16:10 }
{ Packager-XL run on 02-Sep-2020 AT 14:13:12 }
primitive '1-HOLE_0-8-BASE';
pin
'A'<0>:
......
FILE_TYPE=PINLIST;
{ Packager-XL run on 13-Nov-2019 AT 11:16:10 }
TIME=' COMPILATION ON 13-Nov-2019 AT 11:16:10';
{ Packager-XL run on 02-Sep-2020 AT 14:13:12 }
TIME=' COMPILATION ON 02-Sep-2020 AT 14:13:12';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
......
......@@ -59,15 +59,15 @@ PCA9517DGKR-GND=GND_SIGNAL PCA9517DGKR 1
PCA9539PW-VDD=P3V3,VSS=GND_SIGA PCA9539PW 2
PCOAX-PLEMO00C-GND=GND_SIGNAL EPK.00.250.NTN 6
PLEMO2CI-EPG.00.302.NLN-GND=GNA EPG.00.302.NLN 1
RSMD0402_0.0625W-XX,1% R0402_XX_1%_0.063W 3
RSMD0402_1/16W-0R0,1% R0402_0R_1%_0.063W_100PPM 11
RSMD0402_0.0625W-XX,1% R0402_XX_1%_0.063W 4
RSMD0402_1/16W-0R0,1% R0402_0R_1%_0.063W_100PPM 10
RSMD0402_1/16W-100,1% R0402_100R_1%_0.063W_200PPM 6
RSMD0402_1/16W-1K,1% R0402_1K_1%_0.063W_100PPM 11
RSMD0402_1/16W-2.2K,1% R0402_2K2_1%_0.063W_200PPM 4
RSMD0402_1/16W-2K,1% R0402_2K_1%_0.063W_100PPM 2
RSMD0402_1/16W-47,1% R0402_47R_1%_0.063W_200PPM 42
RSMD0603_-00, R0603_00_JUMPER 19
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 10
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 11
RSMD0603_1/10W-10K,1% R0603_10K_1%_0.1W_100PPM 12
RSMD0603_1/10W-150,1% R0603_150R_1%_0.1W_100PPM 2
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 2
......@@ -78,7 +78,7 @@ RSMD0603_1/10W-51,1% R0603_51R_1%_0.1W_100PPM 8
RSMD0603_1/10W-6.19K,1% R0603_6K19_1%_0.1W_100PPM 2
RSMD0603_1/10W-75,1% R0603_75R_1%_0.1W_100PPM 12
RSMD0603_1/10W-82,1% R0603_82R_1%_0.1W_100PPM 3
RSMD0603_1/10W-XX,1% R0603_XX_1%_0.1W_100PPM 14
RSMD0603_1/10W-XX,1% R0603_XX_1%_0.1W_100PPM 13
RSMD0603_1/16W-2K,1% R0603_2K_1%_0.063W_100PPM 1
RSMD0603_1/16W-68,1% R0603_68R_1%_0.063W_100PPM 12
RSMD0805_125MW-100,1% R0805_100R_1%_0.125W_100PPM 12
......
FILE_TYPE = EXPANDEDNETLIST;
{ Packager-XL run on 13-Nov-2019 AT 11:16:10 CONSTRAINTS_VIEW_GENERATED}
{ Packager-XL run on 02-Sep-2020 AT 14:13:12 CONSTRAINTS_VIEW_GENERATED}
NET_NAME
'BEAM_TRIGGER_N<0>'
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):BEAM_TRIGGER_N'<0>:
......
LOGICAL PART CROSS REFERENCE - 13-Nov-2019 AT 11:16:10
LOGICAL PART CROSS REFERENCE - 02-Sep-2020 AT 14:13:12
DRAWING: @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
......@@ -570,7 +570,7 @@ CAPCERSMDCL2_0402-1NF_X7R,50V I88 C30
1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):GND_SIGNAL
2 P3V3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):P3V3
RSMD0603_1/10W-XX,1% I90 R53
RSMD0603_1/10W-100,1% I90 R53
1 DATA_FROM_CDR_P A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):DATA_FROM_CDR_P
2 DATA_FROM_CDR_N B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):DATA_FROM_CDR_N
......@@ -622,7 +622,7 @@ RSMD0402_1/16W-2.2K,1% I111 R74
1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):GND_SIGNAL
2 DATA_TO_FFD_P B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):DATA_TO_FFD_P
RSMD0402_1/16W-0R0,1% I112 R94
RSMD0402_0.0625W-XX,1% I112 R94
1 UNNAMED_7_NBSG53AMOD_I2_VTCLK A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):UNNAMED_7_NBSG53AMOD_I2_VTCLK
2 P3V3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):P3V3
......@@ -3539,7 +3539,7 @@ CAPCERSMDCL2_0402-10NF,16V_GEN I141 C63
2 P3V3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):P3V3
END LOGICAL PART CROSS REFERENCE
GLOBAL SIGNAL CROSS REFERENCE - 13-Nov-2019 AT 11:16:10
GLOBAL SIGNAL CROSS REFERENCE - 02-Sep-2020 AT 14:13:12
BEAM_TRIGGER_N<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):BEAM_TRIGGER_N(0)
J4 H38 H<38> ASP-134606-01 I1 @FMC_TLU_V1_LIB.PC036A_FMC_LPC_CONNECTOR(SCH_1):PAGE1
TP6_7 1 A<0> TP_HOLE-0.8MM I179 @FMC_TLU_V1_LIB.FMC_TLU_THRESHOLD_DISCRIMINATOR_DUAL(SCH_1):PAGE1
......@@ -3940,12 +3940,12 @@ CONT_TO_FPGA<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):CONT_TO_FPGA(3)
DATA_FROM_CDR_N @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):DATA_FROM_CDR_N
J4 C26 C<26> ASP-134606-01 I2 @FMC_TLU_V1_LIB.PC036A_FMC_LPC_CONNECTOR(SCH_1):PAGE1
IC8 28 DATAOUTN ADN2814ACPZ-VCC=P3V3,VEE=GND_SA I3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R53 2 B<0> RSMD0603_1/10W-XX,1% I90 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R53 2 B<0> RSMD0603_1/10W-100,1% I90 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
DATA_FROM_CDR_P @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):DATA_FROM_CDR_P
J4 C27 C<27> ASP-134606-01 I2 @FMC_TLU_V1_LIB.PC036A_FMC_LPC_CONNECTOR(SCH_1):PAGE1
IC8 29 DATAOUTP ADN2814ACPZ-VCC=P3V3,VEE=GND_SA I3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R53 1 A<0> RSMD0603_1/10W-XX,1% I90 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R53 1 A<0> RSMD0603_1/10W-100,1% I90 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
DATA_TO_FFD_N @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):DATA_TO_FFD_N
J4 D24 D<24> ASP-134606-01 I2 @FMC_TLU_V1_LIB.PC036A_FMC_LPC_CONNECTOR(SCH_1):PAGE1
......@@ -5116,7 +5116,7 @@ P3V3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):P3V3
R55 1 A<0> RSMD0402_1/16W-0R0,1% I36 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE8
J1 1 A<0> CON16P-MTLW-108-07-L-D-250 I146 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
J1 2 A<1> CON16P-MTLW-108-07-L-D-250 I146 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
R94 2 B<0> RSMD0402_1/16W-0R0,1% I112 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R94 2 B<0> RSMD0402_0.0625W-XX,1% I112 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R95 2 B<0> RSMD0402_1/16W-0R0,1% I113 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R99 1 A<0> RSMD0603_1/10W-XX,1% I119 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
C60 2 B<0> CAPCERSMDCL2_0402-100NF,16V_GEN I127 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
......@@ -6238,7 +6238,7 @@ UNNAMED_7_NBSG53AMOD_I2_SEL @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):UNNAMED_7_
UNNAMED_7_NBSG53AMOD_I2_VTCLK @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):UNNAMED_7_NBSG53AMOD_I2_VTCLK
IC9 1 VTCLK* NBSG53AMNGMOD-(),(GND_SIGNAL:1A I2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R43 2 B<0> RSMD0402_1/16W-0R0,1% I59 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R94 1 A<0> RSMD0402_1/16W-0R0,1% I112 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
R94 1 A<0> RSMD0402_0.0625W-XX,1% I112 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
UNNAMED_7_NBSG53AMOD_I2_VTCLK_1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):UNNAMED_7_NBSG53AMOD_I2_VTCLK_1
IC9 4 VTCLK NBSG53AMNGMOD-(),(GND_SIGNAL:1A I2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
......@@ -6526,7 +6526,7 @@ XB_9 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_C
R9_9 2 B<0> RSMD0402_1/16W-100,1% I48 @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3
END GLOBAL SIGNAL CROSS REFERENCE
GLOBAL PART CROSS REFERENCE - 13-Nov-2019 AT 11:16:10
GLOBAL PART CROSS REFERENCE - 02-Sep-2020 AT 14:13:12
C1 CAPCERSMDCL2_0603-1UF,16V
1 GND_SIGNAL @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):GND_SIGNAL I73 @FMC_TLU_V1_LIB.FMC_TLU_DAC_VTHRESH(SCH_1):PAGE1
......@@ -9203,7 +9203,7 @@ R26_9 RSMD0402_1/16W-100,1%
1 GND_SIGNAL @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):GND_SIGNAL I41 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE8
2 UNNAMED_8_74AVC2T45_I20_A2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):UNNAMED_8_74AVC2T45_I20_A2 I41 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE8
R53 RSMD0603_1/10W-XX,1%
R53 RSMD0603_1/10W-100,1%
1 DATA_FROM_CDR_P @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):DATA_FROM_CDR_P I90 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
2 DATA_FROM_CDR_N @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):DATA_FROM_CDR_N I90 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
......@@ -9495,7 +9495,7 @@ R91_4 RSMD0402_1/16W-47,1%
1 UNNAMED_3_COMMONMODELINEFILTE_9 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):UNNAMED_3_COMMONMODELINEFILTER_I14_1 I136 @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3
2 UNNAMED_3_CAPCERSMDCL2_I11_A_9 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):UNNAMED_3_CAPCERSMDCL2_I11_A I136 @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3
R94 RSMD0402_1/16W-0R0,1%
R94 RSMD0402_0.0625W-XX,1%
1 UNNAMED_7_NBSG53AMOD_I2_VTCLK @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):UNNAMED_7_NBSG53AMOD_I2_VTCLK I112 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
2 P3V3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):P3V3 I112 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
......
Log File: C:\Users\phpgb\AppData\Local\Temp\s34o.
Markers File: C:\Users\phpgb\AppData\Local\Temp\s34o.1
Debug File: C:\Users\phpgb\AppData\Local\Temp\s34o.3
Log File: /tmp/filernOugc
Markers File: /tmp/fileE0FwKZ
Debug File: /tmp/filep45kTA
Debug[0] := TRUE
Elapsed time since start = (00:00:00)
......@@ -13,8 +13,7 @@ Elapsed time since start = (00:00:00)
* Loading State Files *
*************************
INFO(SPCODD-95): State file primitive @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I1@CNINTERFACE.SI5345(CHIPS) has been deleted from the design.
Force load the state file for subdesign @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1) of type FMC_TLU_VSUPPLY5V
Force load the state file for subdesign @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1) of type FMC_TLU_VSUPPLY5V
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1_I40@BRIS_CDS_SPECIAL.LT1175(CHIPS) changed from REG1_5:1 to REG1_5:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1_I42@CNDISCRETE.FERRITE(CHIPS) changed from L2_5:1 to L2_5:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1_I44@CNDISCRETE.FERRITE(CHIPS) changed from L3_5:1 to L3_5:1.
......@@ -447,10 +446,10 @@ Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I122@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C39_9:1 to C39_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I127@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C41_9:1 to C41_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I128@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C40_9:1 to C40_9:1.
Elapsed time since start = (00:00:15)
Elapsed time since start = (00:00:03)
*****************************************
* End loading State Files (00:00:09) *
* End loading State Files (00:00:01) *
*****************************************
......@@ -458,7 +457,7 @@ Elapsed time since start = (00:00:15)
* Starting to assign physical parts. *
****************************************
Elapsed time since start = (00:00:15)
Elapsed time since start = (00:00:03)
***********************************************
* End assigning physical parts. (00:00:00) *
......@@ -958,10 +957,10 @@ Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU
* Packaging *
***************
Elapsed time since start = (00:00:15)
Elapsed time since start = (00:00:04)
*******************************
* End packaging (00:00:00) *
* End packaging (00:00:01) *
*******************************
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I128@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C40_9:1 to C40_9:1.
......@@ -1455,3 +1454,5 @@ Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I128@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C40_9:1 to C40_9:1.
DDB_INFO: State file for design FMC_TLU_TOPLEVEL_F successfully written.
DDB_INFO: Pst files for design FMC_TLU_TOPLEVEL_F successfully written.
system time 0
user time 2
Log File: C:\Users\phpgb\AppData\Local\Temp\s8c8.
Markers File: C:\Users\phpgb\AppData\Local\Temp\s8c8.1
Debug File: C:\Users\phpgb\AppData\Local\Temp\s8c8.3
Log File: C:\Users\phpgb\AppData\Local\Temp\s34o.
Markers File: C:\Users\phpgb\AppData\Local\Temp\s34o.1
Debug File: C:\Users\phpgb\AppData\Local\Temp\s34o.3
Debug[0] := TRUE
Elapsed time since start = (00:00:01)
Elapsed time since start = (00:00:00)
**************************************************************
* End processing project file and command line (00:00:00) *
......@@ -13,7 +13,8 @@ Elapsed time since start = (00:00:01)
* Loading State Files *
*************************
Force load the state file for subdesign @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1) of type FMC_TLU_VSUPPLY5V
INFO(SPCODD-95): State file primitive @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I1@CNINTERFACE.SI5345(CHIPS) has been deleted from the design.
Force load the state file for subdesign @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1) of type FMC_TLU_VSUPPLY5V
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1_I40@BRIS_CDS_SPECIAL.LT1175(CHIPS) changed from REG1_5:1 to REG1_5:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1_I42@CNDISCRETE.FERRITE(CHIPS) changed from L2_5:1 to L2_5:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1_I44@CNDISCRETE.FERRITE(CHIPS) changed from L3_5:1 to L3_5:1.
......@@ -400,7 +401,6 @@ Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I246@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C33_9:1 to C33_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I247@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C32_9:1 to C32_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I248@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C31_9:1 to C31_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I1@CNINTERFACE.SI5345(CHIPS) changed from IC8_9:1 to IC8_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I4@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C1_9:1 to C1_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I6@CNDISCRETE.USBLC6-2(CHIPS) changed from D3_9:1 to D3_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I7@CNCONNECTOR.PLEMO2CI(CHIPS) changed from LM1_9:1 to LM1_9:1.
......@@ -447,10 +447,10 @@ Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I122@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C39_9:1 to C39_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I127@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C41_9:1 to C41_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I128@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C40_9:1 to C40_9:1.
Elapsed time since start = (00:00:12)
Elapsed time since start = (00:00:15)
*****************************************
* End loading State Files (00:00:04) *
* End loading State Files (00:00:09) *
*****************************************
......@@ -458,7 +458,7 @@ Elapsed time since start = (00:00:12)
* Starting to assign physical parts. *
****************************************
Elapsed time since start = (00:00:12)
Elapsed time since start = (00:00:15)
***********************************************
* End assigning physical parts. (00:00:00) *
......@@ -958,7 +958,7 @@ Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU
* Packaging *
***************
Elapsed time since start = (00:00:12)
Elapsed time since start = (00:00:15)
*******************************
* End packaging (00:00:00) *
......
......@@ -752,34 +752,6 @@
Details: This error message is generated whenever part names are changed for components in either the subdesign or the root design after the subdesign has been packaged in the root design. The change in part names can occur due to one of the following reasons: change in component definition properties; selection of a different PPT row for the component (by using the Modify command in Design Entry HDL); use of COMP_NAME or COMP_NAME_SUFFIX properties.
This message is not generated if the subdesign was packaged using USE_SUBDESIGN. Packager-XL picks up the part names from the previous run of the root design packaging and does not read the subdesign state file again, whereas, in the case of FORCE_SUBDESIGN, the part names are read from the subdesign state file for each packaging run.
")
)
(
(tool "Packager-XL")
(class "LOGICAL")
(severity 30)
(error_num 289)
(short_msg "INFO(SPCODD-289): Part name conflict found for 'CN2_9'. This may be updated during packaging.")
(long_msg "INFO(SPCODD-289): Part name conflict found for 'CN2_9'. This may be updated during packaging.
Sub Design Part Name : CAPN4I-1UF,16V,X5R,GNM21
Root Design Part Name : CAPCERSMDCL2_0402-1UF,10V
Details: This error message is generated whenever part names are changed for components in either the subdesign or the root design after the subdesign has been packaged in the root design. The change in part names can occur due to one of the following reasons: change in component definition properties; selection of a different PPT row for the component (by using the Modify command in Design Entry HDL); use of COMP_NAME or COMP_NAME_SUFFIX properties.
This message is not generated if the subdesign was packaged using USE_SUBDESIGN. Packager-XL picks up the part names from the previous run of the root design packaging and does not read the subdesign state file again, whereas, in the case of FORCE_SUBDESIGN, the part names are read from the subdesign state file for each packaging run.
")
)
(
(tool "Packager-XL")
(class "LOGICAL")
(severity 30)
(error_num 289)
(short_msg "INFO(SPCODD-289): Part name conflict found for 'QZ1_9'. This may be updated during packaging.")
(long_msg "INFO(SPCODD-289): Part name conflict found for 'QZ1_9'. This may be updated during packaging.
Sub Design Part Name : BF-100.000MBE-T-GND=GND_SIGNALA
Root Design Part Name : BF-50.000MBE-T-GND=GND_SIGNAL,A
Details: This error message is generated whenever part names are changed for components in either the subdesign or the root design after the subdesign has been packaged in the root design. The change in part names can occur due to one of the following reasons: change in component definition properties; selection of a different PPT row for the component (by using the Modify command in Design Entry HDL); use of COMP_NAME or COMP_NAME_SUFFIX properties.
This message is not generated if the subdesign was packaged using USE_SUBDESIGN. Packager-XL picks up the part names from the previous run of the root design packaging and does not read the subdesign state file again, whereas, in the case of FORCE_SUBDESIGN, the part names are read from the subdesign state file for each packaging run.
")
)
(
(tool "Packager-XL")
......
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