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AIDA-2020 TLU - Hardware
Commit 38ac36fa authored by David Cussans's avatar David Cussans
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updating artwork

parent 8b3d2120
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Showing with 14613 additions and 621618 deletions
Cadence/ADAProject.ini 0 → 100644
View file @ 38ac36fa
[MainWorkSpace]
ActiveTabIndex=-1
OpenTabNames=@Invalid()
Cadence/adw/shoppingCart.xml
View file @ 38ac36fa
This diff is collapsed.
Cadence/fmc_tlu_v1f.cpm
View file @ 38ac36fa
{ Machine generated file created by SPI }
{ Last modified was 18:41:21 Monday, September 14, 2020 }
{ Last modified was 18:07:17 Wednesday, October 07, 2020 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -68,7 +68,7 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1f_36.brd'
last_board_file 'fmc_tlu_v1f_38.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'YES'
......@@ -95,11 +95,32 @@ load_check 'OFF'
connect_check 'OFF'
END_ERCDX
START_PDV
Symbol_Pinname_VectorBusBracket '0'
Symbol_PinProperty_Rotation_Left '0'
Symbol_PinProperty_Rotation_Right '0'
Symbol_PinProperty_Rotation_Top '90'
Symbol_PinProperty_Rotation_Bottom '90'
Symbol_PinProperty_Alignment_Left 'Right'
Symbol_PinProperty_Alignment_Right 'Left'
Symbol_PinProperty_Alignment_Top 'Left'
Symbol_PinProperty_Alignment_Bottom 'Right'
Symbol_PinPropertySetup_Rotation_Apply 'No'
Symbol_PinPropertySetup_Alignment_Apply 'No'
END_PDV
START_PDF
CURRENTPDFVIEWER '0'
CURRENTPDFVIEWERPATH 'Default'
END_PDF
START_CANVAS
GRID_PIN_PITCH '0.050000'
GRID_SNAP_FRACTION '1.000000'
GRID_DOC_SNAP_FRACTION '0.500000'
GRID_DISPLAY_MULTIPLE '1'
END_CANVAS
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
......
Cadence/padstack_editor.jrl 0 → 100644
View file @ 38ac36fa
\t (00:00:00) padstack_editor 17.2 S061 Linux SPB 64-bit Edition
\t (00:00:00) Journal start - Tue Oct 6 18:32:06 2020
\t (00:00:00) Host=excession.phy.bris.ac.uk User=phdgc Pid=18223 CPUs=12
\t (00:00:00) CmdLine= /software/CAD/Cadence/SPB17.20.061/tools/bin/padstack_editor.exe
\t (00:00:00)
\d (00:00:03) QtSignal MainWindow Open triggered
\d (00:00:12) QtFillin /projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd17.x/pe_allegro_lib/padstacks/padstack_smd/fiducial150-250.pad
\d (00:00:26) QtSignal MainWindow Open triggered
\d (00:00:44) QtFillin fiducial150-250.pad
\d (00:00:56) QtSignal GuidedTabsParent GuidedTabs currentChanged Drill
\d (00:00:58) QtSignal GuidedTabsParent GuidedTabs currentChanged Start
\d (00:01:05) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:01:45) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (23:06:04) QtSignal MainWindow Open triggered
\d (23:06:06) QtFillin No
\d (23:06:23) QtFillin fiducial1500-3000.pad
\d (23:06:28) QtSignal GuidedTabsParent GuidedTabs currentChanged Drill
\d (23:06:29) QtSignal GuidedTabsParent GuidedTabs currentChanged Start
\d (23:06:30) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (23:06:33) QtSignal GuidedDesignLayersTab LayersTable itemSelectionChanged 0 "Anti Pad"
\d (23:06:33) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Anti Pad" 0 4
\d (23:06:34) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Anti Pad" 0 4
\d (23:06:34) QtSignal GuidedDesignLayersTab LayersTable cellDoubleClicked 0 "Anti Pad" 0 4
\d (23:06:34) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Anti Pad" 0 4
\d (23:06:35) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Anti Pad" 0 4
\d (23:06:36) QtSignal GuidedDesignLayersTab LayersTable cellDoubleClicked 0 "Anti Pad" 0 4
\d (23:06:36) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Anti Pad" 0 4
\d (23:06:39) QtSignal GuidedDesignLayersTab PadDiameter editingFinished 2.5000
\d (23:06:48) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (23:06:53) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (23:06:53) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (23:07:03) QtSignal GuidedMaskLayersTab PadDiameter editingFinished 1.5000
\d (23:07:06) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (23:07:10) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (23:07:19) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 0 Pad
\d (23:07:20) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 Pad 0 1
\d (23:07:23) QtSignal GuidedMaskLayersTab PadDiameter editingFinished 3.0000
\d (23:07:26) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (23:07:31) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (23:07:37) QtSignal MainWindow Save triggered
\d (23:07:44) QtSignal pseCheckBrowser Close clicked
\d (23:07:46) QtFillin Yes
\d (23:07:52) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (23:07:55) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (23:08:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (23:08:08) QtSignal GuidedDesignLayersTab LayersTable itemSelectionChanged 0 "Thermal Pad"
\d (23:08:08) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Thermal Pad" 0 3
\d (23:08:12) QtSignal GuidedDesignLayersTab PadShape CurrentIndexChanged Circle
\d (23:08:18) QtSignal GuidedDesignLayersTab PadDiameter editingFinished 2.5000
\d (23:08:31) QtSignal GuidedDesignLayersTab PadDiameter editingFinished 1.5000
\d (23:08:38) QtSignal MainWindow Save triggered
\d (23:08:42) QtSignal MainWindow Exit triggered
\t (23:08:42) Journal end - Wed Oct 7 17:40:48 2020
Cadence/worklib/fmc_tlu_toplevel_f/bom/bom_v1f_34.rpt deleted 100644 → 0
View file @ 8b3d2120
TITLE: Bill of Materials
DATE: 01/08/2020
DESIGN: fmc_tlu_toplevel_f
TEMPLATE: P:\cad\tools\cadence_templates\spreadsheet-format.bom
CALLOUT:
Part Name Ref Des Qty PART_NUMBER PART_DESCRIPTION OL_COMMENTS KL_COMMENTS PL_COMMENTS Do Not Fit MANUFACTURER
1-HOLE_0-8-BASE LK1_9,LK2_9,LK3_9,LK4_9 4 ? 0.8mm Hole ? ? ? ? ?
24AA025E48T-I/SN IC5 1 24AA025E48T-I/SN ? ? ? ? ? MICROCHIP
74LVC1G14GW IC14,IC16 2 74LVC1G14GW ? ? ? ? ? NXP/PHILIPS
AD5665RBRUZ-1 IC1,IC2 2 AD5665RBRUZ-1 ? ? ? ? ? ANALOG DEVICES
ADN2814ACPZ IC8 1 ADN2814ACPZ ? ? ? ? ? ANALOG DEVICES
ASP-134606-01 J4 1 ASP-134606-01 ? ? ? ? ? SAMTEC
BF-50.000MBE-T QZ1_9 1 BF-100.000MBE-T ? ? ? ? ? TXC CRYSTALS
CAPCERSMDCL2_0402-100NF,10V C1_1,C1_2,C1_3,C1_4,C2_1,C2_2,C2_3,C2_4,C3_1,C3_2,C3_3,C3_4,C4_1,C4_2,C4_3,C4_4,C5_1,C5_2,C5_3,C5_4,C6_9,C11_1,C11_2,C11_3,C11_4,C12_1,C12_2,C12_3,C12_4,C13_1,C13_2,C13_3,C13_4,C18_9,C20_9,C27_9,C28_9,C29_9,C30_9,C38_9,C39_9,C41,C42,C57,C57_2,C57_3,C57_4,C58,C58_2,C58_3,C58_4 51 CC0402_100NF_10V_10%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0402-100NF,16V_GEN C7,C7_1,C7_2,C7_3,C7_4,C8,C9,C10,C11_9,C12_9,C14_9,C15_9,C17_9,C19,C19_9,C20,C22_9,C23,C23_9,C24,C25,C25_9,C26,C35,C36,C37_9,C60,C61,C62,C64 30 CC0402_100NF_16V_10%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0402-10NF,16V_GEN C31_9,C32_9,C33_9,C34_9,C35_9,C36_9,C63 7 CC0402_10NF_16V_10%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0402-1NF_X7R,50V C27,C28,C29,C30,C33,C34,C59 7 CC0402_1NF_50V_10%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0402-1UF,10V C47,C48,C49,C50,CN2_9 5 CC0402_1.0UF_10V_10%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0402-1UF,16V C53,C53_2,C53_3,C53_4,C54,C54_2,C54_3,C54_4,C55,C55_2,C55_3,C55_4,C56,C56_2,C56_3,C56_4 16 CC0402_1.0UF_16V_10%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0402-4.7NF,50V_GEN C6_1,C6_2,C6_3,C6_4,C8_1,C8_2,C8_3,C8_4 8 CC0402_4.7NF_50V_10%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0402-470NF,6.3V_GEN C18 1 CC0402_470NF_6V3_10%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0603-1.0NF,50V C31 1 CC0603_1NF_50V_10%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0603-1.0UF,6.3V C5_6,C5_7,C5_8,C6_6,C6_7,C6_8,C8_6,C8_7,C8_8,C14_6,C14_7,C14_8,C51,C52 14 CC0603_1UF_6V3_10%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0603-100NF,16V C1_6,C1_7,C1_8,C1_9,C2_6,C2_7,C2_8,C2_9,C3,C3_9,C4_9,C5_9,C7_6,C7_7,C7_8,C9_1,C9_2,C9_3,C9_4,C9_6,C9_7,C9_8,C10_1,C10_2,C10_3,C10_4,C10_6,C10_7,C10_8,C10_9,C11,C11_6,C11_7,C11_8,C12,C12_6,C12_7,C12_8,C13_6,C13_7,C13_8,C14,C15,C16,C17,C37,C38,C39,C40,C40_9,C41_9,C43,C70 53 CC0603_100NF_16V_10%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0603-100NF,50V_X7R C32 1 CC0603_100NF_50V_10%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0603-10NF,50V C3_6,C3_7,C3_8,C4_6,C4_7,C4_8 6 CC0603_10NF_50V_10%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0603-10NF,50V_X7R C21,C22 2 CC0603_10NF_50V_10%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0603-10UF,6.3V C8_9,C9_9,C16_9,C24_9,C26_9 5 CC0603_10UF_6V3_20%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0603-10UF_X5R,6.3V C13 1 CC0603_10UF_6V3_10%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0603-1UF,16V C1,C2,C4,C5,C6,C44,C45,C46 8 CC0603_1UF_16V_10%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0805-22UF,6.3V C13_9,C21_9 2 CC0805_22UF_6V3_15%_X7R ? ? ? ? ? GENERIC
CAPCERSMDCL2_0805-4.7UF,10V C9_5,C10_5,C11_5,C12_5 4 GRM21BF51A475ZA01 ? ? ? ? ? MURATA
CAPCERSMDCL2_1210-10UF,10V_GEN C7_9 1 CC1210_10UF_25V_10%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_1210-22UF,16V C7_5,C8_5 2 CC1210_22UF_16V_10%_X5R ? ? ? ? ? GENERIC
CAPCERSMDCL2_1210-4.7UF,50V C1_5,C2_5,C3_5,C4_5,C5_5,C6_5 6 CC1210_4.7UF_50V_10%_X7R ? ? ? ? ? GENERIC
COMMON_MODE_LINE_FILTER_4312-744231091,90OHM L1_1,L1_2,L1_3,L1_4,L1_9,L2_1,L2_2,L2_3,L2_4,L2_9,L3_1,L3_2,L3_3,L3_4,L3_9,L4_1,L4_2,L4_3,L4_4,L4_9,L8_9 21 744231091 ? ? ? ? ? WURTH ELEKTRONIK
CON16P-MTLW-108-07-L-D-250 J1 1 MTLW-108-07-L-D-250 ? ? ? ? ? SAMTEC
CON19P-HDMI-19-01-X-SM J1_1,J1_2,J1_3,J1_4 4 HDMI-19-01-X-SM ? ? ? ? ? SAMTEC
CON20P_SFP-1888247-1 J2 1 1888247-1 ? ? ? ? ? TYCO
CON3P-SIL254D J1_9,J3 2 MTLW-103-07-L-S-250 ? ? ? ? ? SAMTEC
DS92001TLD IC1_9,IC2_9,IC3_9,IC4_9,IC5_9,IC7_9,IC15 7 DS92001TLD ? ? ? ? ? National Semiconductor
FERRITE_C0805-LI0805H121R-10,LI0805H121R-10 L5_9,L6_9,L7_9 3 LI0805H121R-10 ? ? ? ? ? STEWARD
FERRITE_SMD-7427921,WURTH L2_5,L3_5 2 7427921 ? ? ? ? ? WURTH
FERRITE_SMD-BLM41P800S,MURATA L1_5 1 08.11.BLM41P800S ? ? ? ? ? MURATA
HBAT-540C D1_6,D1_7,D1_8,D2_6,D2_7,D2_8 6 HBAT-540C ? ? ? ? ? AVAGO TECHNOLOGIES
INDUCTANCE_LQH32C_23-4.7UH L1,L2 2 LQH32CN4R7M23 ? ? ? ? ? MURATA
LED1-597_GREEN LD1,LD2,LD3 3 597-3301-502F ? ? ? ? ? DIALIGHT
LP38692SD_WSON-1.8V,TEXAS INSTRUMENTS U1_9 1 LP38692SD-1.8 Fixed 1.8V low dropout regulator, 900mA , stable with ceramic capacitors , WSON-6 package Available from Farnell 2492289 ? ? ? ?
LP5951_SOT23-5-1.3V,TEXAS INSTRUMENTS U1 1 LP5951MF-1.3 1.3V, 150mA Low Dropout Regulator Farnell 1312651 - - ? ?
LT1129CST-5_SOT223-LINEAR VR1_5 1 Linear Technology LT1129CST-5 700mA, 5V LDO Regulator Farnell 1663375 - - ? ?
LT1175_SOT_223 REG1_5 1 Farnell 500mA Negative low dropout Micropower Regulator - - - ? ?
LTM8047EY#PBF RG1_5,RG2_5 2 LTM8047EY#PBF ? ? ? ? ? LINEAR TECHNOLOGY
MAX9601_TSSOP IC1_6,IC1_7,IC1_8 3 MAX9601EUP ? ? ? ? ? Maxim
NB6N11SMNG IC13 1 NB6N11SMNG ? ? ? ? ? ON SEMICONDUCTOR
NBSG53AMNGMOD IC9 1 NBSG53AMNGMOD ? ? ? ? ? ON SEMICONDUCTOR
OPA4277UA IC3,IC4 2 OPA4277UA ? ? ? ? ? TEXAS INSTRUMENTS
PCA9517DGKR IC10 1 PCA9517DGKR ? ? ? ? ? TEXAS INSTRUMENTS
PCA9539PW IC6,IC7 2 PCA9539PW ? ? ? ? ? NXP/PHILIPS
PCOAX-PLEMO00C PX1,PX2,PX3,PX4,PX5,PX6 6 EPK.00.250.NTN ? ? ? ? ? LEMO
PLEMO2CI-EPG.00.302.NLN LM1_9 1 EPG.00.302.NLN ? ? ? ? ? LEMO
RSMD0402_0.0625W-XX,1% R25,R37,R38 3 R0402_XX_1%_0.063W ? ? ? ? ? GENERIC
RSMD0402_1/16W-0R0,1% R43,R44,R52,R54,R55,R69,R71,R72,R73,R94,R95 11 R0402_0R_1%_0.063W_100PPM ? ? ? ? ? GENERIC
RSMD0402_1/16W-100,1% R1_9,R2_9,R3_9,R4_9,R9_9,R26_9 6 R0402_100R_1%_0.063W_200PPM ? ? ? ? ? GENERIC
RSMD0402_1/16W-1K,1% R11_9,R13_9,R14_9,R15_9,R16_9,R17_9,R18_9,R20_9,R21_9,R22_9,R23_9 11 R0402_1K_1%_0.063W_100PPM ? ? ? ? ? GENERIC
RSMD0402_1/16W-2.2K,1% R39,R66,R74,R75 4 R0402_2K2_1%_0.063W_200PPM ? ? ? ? ? GENERIC
RSMD0402_1/16W-2K,1% R40,R42 2 R0402_2K_1%_0.063W_100PPM ? ? ? ? ? GENERIC
RSMD0402_1/16W-47,1% R76,R77,R78,R79,R80,R81,R82,R83,R84,R84_2,R84_3,R84_4,R85,R85_2,R85_3,R85_4,R86,R86_2,R86_3,R86_4,R87,R87_2,R87_3,R87_4,R88,R88_2,R88_3,R88_4,R89,R89_2,R89_3,R89_4,R90,R90_2,R90_3,R90_4,R91,R91_2,R91_3,R91_4,R92,R93 42 R0402_47R_1%_0.063W_200PPM ? ? ? ? ? GENERIC
RSMD0603_-00, R2,R3,R4,R5,R18,R19,R20,R21,R32,R35,R60,R62,R64,R67,R68,R70,R96,R97,R98 19 R0603_00_JUMPER ? ? ? ? ? GENERIC
RSMD0603_1/10W-100,1% R3_6,R3_7,R3_8,R4_6,R4_7,R4_8,R10_9,R25_9,R36,R100 10 R0603_100R_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-10K,1% R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,R16,R17 12 R0603_10K_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-150,1% R45,R46 2 R0603_150R_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-1K,1% R1,R5_9 2 R0603_1K_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-2K,1% R41 1 R0603_2K_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-3.3,1% R1_5 1 R0603_3R3_1%_0.1W_200PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-4.7K,1% R6_9,R26,R27,R28,R29,R30,R31,R47,R48,R49,R50,R51 12 R0603_4K7_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-51,1% R1_1,R1_2,R1_3,R1_4,R2_1,R2_2,R2_3,R2_4 8 R0603_51R_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-6.19K,1% R2_5,R3_5 2 R0603_6K19_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-75,1% R9_6,R9_7,R9_8,R10_6,R10_7,R10_8,R11_6,R11_7,R11_8,R12_6,R12_7,R12_8 12 R0603_75R_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-82,1% R22,R23,R24 3 R0603_82R_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/10W-XX,1% R7_6,R7_7,R7_8,R7_9,R8_6,R8_7,R8_8,R8_9,R34,R53,R61,R63,R65,R99 14 R0603_XX_1%_0.1W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/16W-2K,1% R33 1 R0603_2K_1%_0.063W_100PPM ? ? ? ? ? GENERIC
RSMD0603_1/16W-68,1% R56,R56_7,R56_8,R57,R57_7,R57_8,R58,R58_7,R58_8,R59,R59_7,R59_8 12 R0603_68R_1%_0.063W_100PPM ? ? ? ? ? GENERIC
RSMD0805_125MW-100,1% R1_6,R1_7,R1_8,R2_6,R2_7,R2_8,R5_6,R5_7,R5_8,R6_6,R6_7,R6_8 12 R0805_100R_1%_0.125W_100PPM ? ? ? ? ? GENERIC
SFP_CAGE-SP-74737-004 SFP1 1 74737-004 ? ? ? ? ? MOLEX
SI5395A-A-GM IC8_9 1 Si5395A-A-GM ? ? ? ? ? SILICON LABS
SN65MLVD040RGZ IC1_1,IC1_2,IC1_3,IC1_4,IC6_9 5 SN65MLVD040RGZ ? ? ? ? ? TEXAS INSTRUMENTS
SN74AVC2T45DCU IC11,IC12 2 SN74AVC2T45DCU ? ? ? ? ? TEXAS INSTRUMENTS
TPS78633DCQ IC2_1,IC2_2,IC2_3,IC2_4 4 TPS78633DCQ ? ? ? ? ? TEXAS INSTRUMENTS
TP_HOLE-0.8MM TP1,TP1_1,TP1_2,TP1_3,TP1_4,TP1_6,TP1_7,TP1_8,TP2,TP2_1,TP2_2,TP2_3,TP2_4,TP2_6,TP2_7,TP2_8,TP3,TP3_1,TP3_2,TP3_3,TP3_4,TP3_6,TP3_7,TP3_8,TP4,TP4_1,TP4_2,TP4_3,TP4_4,TP4_6,TP4_7,TP4_8,TP5,TP5_1,TP5_2,TP5_3,TP5_4,TP5_6,TP5_7,TP5_8,TP6,TP6_1,TP6_2,TP6_3,TP6_4,TP6_6,TP6_7,TP6_8,TP7,TP7_1,TP7_2,TP7_3,TP7_4,TP7_6,TP7_7,TP7_8,TP8,TP8_1,TP8_2,TP8_3,TP8_4,TP8_6,TP8_7,TP8_8,TP9,TP9_1,TP9_2,TP9_3,TP9_4,TP10,TP10_1,TP10_2,TP10_3,TP10_4,TP11,TP11_1,TP11_2,TP11_3,TP11_4,TP12_1,TP12_2,TP12_3,TP12_4 83 TP_HOLE_0.8mm ? ? ? ? ? ?
USBLC6-2SC6 D1,D1_2,D1_3,D1_4,D2,D2_2,D2_3,D2_4,D3,D3_1,D3_2,D3_3,D3_4,D3_9,D4,D4_2,D4_3,D4_4,D5,D6,D7 21 USBLC6-2SC6 ? ? ? ? ? ST MICROELECTRONICS
TOTAL 638
Cadence/worklib/fmc_tlu_toplevel_f/packaged/last_import_time.txt
View file @ 38ac36fa
......@@ -114,3 +114,7 @@
2020-09-02T14:13:22 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxnet.dat"
2020-09-02T14:13:22 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxprt.dat"
2020-09-02T14:13:22 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstdmlmodels.dat"
2020-10-07T18:06:07 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstchip.dat"
2020-10-07T18:06:07 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxnet.dat"
2020-10-07T18:06:07 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxprt.dat"
2020-10-07T18:06:07 ===> "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstdmlmodels.dat"
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstback.dat
View file @ 38ac36fa
{ Packager-XL run on 02-Sep-2020 AT 14:13:12 }
{ Packager-XL run on 07-Oct-2020 AT 18:06:01 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page1";
BODY = "24AA025E48","I8": LOCATION = "IC5" #&CDS_LOCATION = "IC5" &SEC = "1" #&CDS_SEC = "1";
......@@ -47,6 +47,18 @@ BODY = "CON16P","I146": LOCATION = "J1" #&CDS_LOCATION = "J1" &SEC = "1" #&CDS_S
"A<13>": PN = "14" !CDS_PN = "14";
"A<14>": PN = "15" !CDS_PN = "15";
"A<15>": PN = "16" !CDS_PN = "16";
BODY = "FIDUCIAL","I149": LOCATION = "RFT2" #&CDS_LOCATION = "RFT2" &SEC = "1" #&CDS_SEC = "1";
"1": PN = "1" !CDS_PN = "1";
BODY = "FIDUCIAL","I150": LOCATION = "RFT3" #&CDS_LOCATION = "RFT3" &SEC = "1" #&CDS_SEC = "1";
"1": PN = "1" !CDS_PN = "1";
BODY = "FIDUCIAL","I151": LOCATION = "RFB1" #&CDS_LOCATION = "RFB1" &SEC = "1" #&CDS_SEC = "1";
"1": PN = "1" !CDS_PN = "1";
BODY = "FIDUCIAL","I152": LOCATION = "RFB3" #&CDS_LOCATION = "RFB3" &SEC = "1" #&CDS_SEC = "1";
"1": PN = "1" !CDS_PN = "1";
BODY = "FIDUCIAL","I153": LOCATION = "RFB2" #&CDS_LOCATION = "RFB2" &SEC = "1" #&CDS_SEC = "1";
"1": PN = "1" !CDS_PN = "1";
BODY = "FIDUCIAL","I154": LOCATION = "RFT1" #&CDS_LOCATION = "RFT1" &SEC = "1" #&CDS_SEC = "1";
"1": PN = "1" !CDS_PN = "1";
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page6";
BODY = "PCA9539","I1": LOCATION = "IC6" #&CDS_LOCATION = "IC6" &SEC = "1" #&CDS_SEC = "1";
"A0": PN = "21" !CDS_PN = "21";
......
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstchip.dat
View file @ 38ac36fa
FILE_TYPE = LIBRARY_PARTS;
{ Packager-XL run on 02-Sep-2020 AT 14:13:12 }
{ Packager-XL run on 07-Oct-2020 AT 18:06:01 }
primitive '1-HOLE_0-8-BASE';
pin
'A'<0>:
......@@ -2857,6 +2857,25 @@ primitive 'FERRITE_SMD-BLM41P800S,MURATA';
PARENT_PPT_PART='FERRITE_SMD-BLM41P800S,MURATA';
end_body;
end_primitive;
primitive 'FIDUCIAL';
pin
'1':
PIN_NUMBER='(1)';
PINUSE='NC';
NO_LOAD_CHECK='Both';
NO_IO_CHECK='Both';
NO_ASSERT_CHECK='TRUE';
NO_DIR_CHECK='TRUE';
ALLOW_CONNECT='TRUE';
end_pin;
body
PART_NAME='FIDUCIAL';
BODY_NAME='FIDUCIAL';
JEDEC_TYPE='FIDUCIAL1000URD';
PHYS_DES_PREFIX='FID';
CLASS='IO';
end_body;
end_primitive;
primitive 'HBAT-540C';
pin
'A':
......
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstpin.dat
View file @ 38ac36fa
FILE_TYPE=PINLIST;
{ Packager-XL run on 02-Sep-2020 AT 14:13:12 }
TIME=' COMPILATION ON 02-Sep-2020 AT 14:13:12';
{ Packager-XL run on 07-Oct-2020 AT 18:06:01 }
TIME=' COMPILATION ON 07-Oct-2020 AT 18:06:01';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
......@@ -400,6 +400,9 @@ primitive 'FERRITE_SMD-BLM41P800S,MURATA';body 'FERRITE';
'B'<0>:'(2)';BIDI;
'A'<0>:'(1)';BIDI;
end_primitive;
primitive 'FIDUCIAL'; body 'FIDUCIAL';
'1':'(1)';
end_primitive;
primitive 'HBAT-540C'; body 'DIODE_DUAL_SERIES';
'A':'(1)';
'C':'(2)';
......
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstprop.dat.old
View file @ 38ac36fa
Logical and Physical Net Conflicts
----------------------------------
DRAWING = @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1)
NET_NAME = VIN_FILTERED
PNN = VIN_FILTERED_5
NET_NAME = M5V7
PNN = M5V7_5
NET_NAME = P5V7
PNN = P5V7_5
Logical and Physical Net Conflicts
----------------------------------
DRAWING = @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1)
NET_NAME = BUSY
PNN = BUSY_1
NET_NAME = BUSY*
PNN = BUSY*_1
NET_NAME = CONT
PNN = CONT_1
NET_NAME = CONT*
PNN = CONT*_1
NET_NAME = SPARE
PNN = SPARE_1
NET_NAME = SPARE*
PNN = SPARE*_1
NET_NAME = TRIG
PNN = TRIG_1
NET_NAME = TRIG*
PNN = TRIG*_1
NET_NAME = HDMI_POWER
PNN = HDMI_POWER_1
Logical and Physical Net Conflicts
----------------------------------
DRAWING = @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I2@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1)
NET_NAME = BUSY
PNN = BUSY_2
NET_NAME = BUSY*
PNN = BUSY*_2
NET_NAME = CONT
PNN = CONT_2
NET_NAME = CONT*
PNN = CONT*_2
NET_NAME = SPARE
PNN = SPARE_2
NET_NAME = SPARE*
PNN = SPARE*_2
NET_NAME = TRIG
PNN = TRIG_2
NET_NAME = TRIG*
PNN = TRIG*_2
NET_NAME = HDMI_POWER
PNN = HDMI_POWER_2
Logical and Physical Net Conflicts
----------------------------------
DRAWING = @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I3@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1)
NET_NAME = BUSY
PNN = BUSY_3
NET_NAME = BUSY*
PNN = BUSY*_3
NET_NAME = CONT
PNN = CONT_3
NET_NAME = CONT*
PNN = CONT*_3
NET_NAME = SPARE
PNN = SPARE_3
NET_NAME = SPARE*
PNN = SPARE*_3
NET_NAME = TRIG
PNN = TRIG_3
NET_NAME = TRIG*
PNN = TRIG*_3
NET_NAME = HDMI_POWER
PNN = HDMI_POWER_3
Logical and Physical Net Conflicts
----------------------------------
DRAWING = @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I4@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1)
NET_NAME = BUSY
PNN = BUSY_4
NET_NAME = BUSY*
PNN = BUSY*_4
NET_NAME = CONT
PNN = CONT_4
NET_NAME = CONT*
PNN = CONT*_4
NET_NAME = SPARE
PNN = SPARE_4
NET_NAME = SPARE*
PNN = SPARE*_4
NET_NAME = TRIG
PNN = TRIG_4
NET_NAME = TRIG*
PNN = TRIG*_4
NET_NAME = HDMI_POWER
PNN = HDMI_POWER_4
Logical and Physical Net Conflicts
----------------------------------
DRAWING = @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1)
NET_NAME = CLK_FROM_HDMI_N
PNN = CLK_FROM_HDMI_N_9
NET_NAME = CLK_FROM_HDMI_P
PNN = CLK_FROM_HDMI_P_9
NET_NAME = CLK_FROM_LEMO_N
PNN = CLK_FROM_LEMO_N_9
NET_NAME = CLK_FROM_LEMO_P
PNN = CLK_FROM_LEMO_P_9
NET_NAME = CLK_TO_LEMO_N
PNN = CLK_TO_LEMO_N_9
NET_NAME = CLK_TO_LEMO_P
PNN = CLK_TO_LEMO_P_9
NET_NAME = XA
PNN = XA_9
NET_NAME = XB
PNN = XB_9
NET_NAME = INTR*
PNN = INTR*_9
NET_NAME = LEMO_CLK_N
PNN = LEMO_CLK_N_9
NET_NAME = LEMO_CLK_P
PNN = LEMO_CLK_P_9
NET_NAME = CLK_FBACK_N
PNN = CLK_FBACK_N_9
NET_NAME = CLK_FBACK_P
PNN = CLK_FBACK_P_9
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstrprt.dat
View file @ 38ac36fa
......@@ -43,6 +43,7 @@ DS92001TLD-DAP=GND_SIGNAL,GND=A DS92001TLD 7
FERRITE_C0805-LI0805H121R-10,LA LI0805H121R-10 3
FERRITE_SMD-7427921,WURTH 7427921 2
FERRITE_SMD-BLM41P800S,MURATA 08.11.BLM41P800S 1
FIDUCIAL 6
HBAT-540C HBAT-540C 6
INDUCTANCE_LQH32C_23-4.7UH LQH32CN4R7M23 2
LED1-597_GREEN 597-3301-502F 3
......@@ -90,4 +91,4 @@ TPS78633DCQ TPS78633DCQ 4
TP_HOLE-0.8MM TP_HOLE_0.8mm 83
USBLC6-2SC6 USBLC6-2SC6 21
Total 638
Total 644
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxnet.dat
View file @ 38ac36fa
FILE_TYPE = EXPANDEDNETLIST;
{ Packager-XL run on 02-Sep-2020 AT 14:13:12 CONSTRAINTS_VIEW_GENERATED}
{ Packager-XL run on 07-Oct-2020 AT 18:06:01 CONSTRAINTS_VIEW_GENERATED}
NET_NAME
'BEAM_TRIGGER_N<0>'
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):BEAM_TRIGGER_N'<0>:
......@@ -3907,6 +3907,24 @@ NODE_NAME IC7 1
NODE_NAME SFP1 NC
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7_I5@CNMECH.SFP_CAGE(CHIPS)':
'NC': CDS_PINID='NC';
NODE_NAME RFT2 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I149@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
'1': CDS_PINID='\1\';
NODE_NAME RFT3 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I150@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
'1': CDS_PINID='\1\';
NODE_NAME RFB1 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I151@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
'1': CDS_PINID='\1\';
NODE_NAME RFB3 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I152@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
'1': CDS_PINID='\1\';
NODE_NAME RFB2 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I153@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
'1': CDS_PINID='\1\';
NODE_NAME RFT1 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I154@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
'1': CDS_PINID='\1\';
NET_NAME
'P12V'
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):P12V':
......
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxprt.dat
View file @ 38ac36fa
FILE_TYPE=EXPANDEDPARTLIST;
{ Packager-XL run on 02-Sep-2020 AT 14:13:12 }
{ Packager-XL run on 07-Oct-2020 AT 18:06:01 }
DIRECTIVES
PST_VERSION='PST_HDL_CENTRIC_VERSION_0';
ROOT_DRAWING='FMC_TLU_TOPLEVEL_F';
POST_TIME='02-Sep-2020 AT 14:13:12';
POST_TIME='07-Oct-2020 AT 18:06:01';
SOURCE_TOOL='PACKAGER_XL';
END_DIRECTIVES;
......@@ -19868,6 +19868,126 @@ l/lt1175/chips/chips.prt',
REUSE_INSTANCE='FMC_TLU_VSUPPLY5V_5',
REUSE_NAME='FMC_TLU_VSUPPLY5V';
PART_NAME
RFB1 'FIDUCIAL':;
SECTION_NUMBER 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I151@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
C_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page1_i151@bris_cds_special.f~
iducial(chips)',
P_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page2_i151@bris_cds_special.f~
iducial(chips)',
PATH='I151',
DRAWING='@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1',
PHYS_PAGE='2',
XY='(3525,-2675)',
ROT='0',
VER='1',
CDS_LIB='bris_cds_special',
CDS_PART_NAME='FIDUCIAL',
PRIM_FILE='/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_specia~
l/fiducial/chips/chips.prt';
PART_NAME
RFB2 'FIDUCIAL':;
SECTION_NUMBER 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I153@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
C_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page1_i153@bris_cds_special.f~
iducial(chips)',
P_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page2_i153@bris_cds_special.f~
iducial(chips)',
PATH='I153',
DRAWING='@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1',
PHYS_PAGE='2',
XY='(3900,-2325)',
ROT='0',
VER='1',
CDS_LIB='bris_cds_special',
CDS_PART_NAME='FIDUCIAL',
PRIM_FILE='/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_specia~
l/fiducial/chips/chips.prt';
PART_NAME
RFB3 'FIDUCIAL':;
SECTION_NUMBER 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I152@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
C_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page1_i152@bris_cds_special.f~
iducial(chips)',
P_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page2_i152@bris_cds_special.f~
iducial(chips)',
PATH='I152',
DRAWING='@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1',
PHYS_PAGE='2',
XY='(3875,-1975)',
ROT='0',
VER='1',
CDS_LIB='bris_cds_special',
CDS_PART_NAME='FIDUCIAL',
PRIM_FILE='/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_specia~
l/fiducial/chips/chips.prt';
PART_NAME
RFT1 'FIDUCIAL':;
SECTION_NUMBER 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I154@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
C_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page1_i154@bris_cds_special.f~
iducial(chips)',
P_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page2_i154@bris_cds_special.f~
iducial(chips)',
PATH='I154',
DRAWING='@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1',
PHYS_PAGE='2',
XY='(3900,-2650)',
ROT='0',
VER='1',
CDS_LIB='bris_cds_special',
CDS_PART_NAME='FIDUCIAL',
PRIM_FILE='/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_specia~
l/fiducial/chips/chips.prt';
PART_NAME
RFT2 'FIDUCIAL':;
SECTION_NUMBER 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I149@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
C_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page1_i149@bris_cds_special.f~
iducial(chips)',
P_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page2_i149@bris_cds_special.f~
iducial(chips)',
PATH='I149',
DRAWING='@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1',
PHYS_PAGE='2',
XY='(3500,-2000)',
ROT='0',
VER='1',
CDS_LIB='bris_cds_special',
CDS_PART_NAME='FIDUCIAL',
PRIM_FILE='/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_specia~
l/fiducial/chips/chips.prt';
PART_NAME
RFT3 'FIDUCIAL':;
SECTION_NUMBER 1
'@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I150@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)':
C_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page1_i150@bris_cds_special.f~
iducial(chips)',
P_PATH='@fmc_tlu_v1_lib.fmc_tlu_toplevel_f(sch_1):page2_i150@bris_cds_special.f~
iducial(chips)',
PATH='I150',
DRAWING='@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1',
PHYS_PAGE='2',
XY='(3525,-2350)',
ROT='0',
VER='1',
CDS_LIB='bris_cds_special',
CDS_PART_NAME='FIDUCIAL',
PRIM_FILE='/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_specia~
l/fiducial/chips/chips.prt';
PART_NAME
RG1_5 'LTM8047EY#PBF':
ROOM='POWER_SUPPLY',
......
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxref.dat
View file @ 38ac36fa
LOGICAL PART CROSS REFERENCE - 02-Sep-2020 AT 14:13:12
LOGICAL PART CROSS REFERENCE - 07-Oct-2020 AT 18:06:01
DRAWING: @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
......@@ -57,6 +57,24 @@ CON16P-MTLW-108-07-L-D-250 I146 J1
11 GND_SIGNAL A<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):GND_SIGNAL
1 P3V3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):P3V3
FIDUCIAL I149 RFT2
1 NC 1 NC
FIDUCIAL I150 RFT3
1 NC 1 NC
FIDUCIAL I151 RFB1
1 NC 1 NC
FIDUCIAL I152 RFB3
1 NC 1 NC
FIDUCIAL I153 RFB2
1 NC 1 NC
FIDUCIAL I154 RFT1
1 NC 1 NC
DRAWING: @FMC_TLU_V1_LIB.PC036A_FMC_LPC_CONNECTOR(SCH_1):PAGE1
......@@ -3539,7 +3557,7 @@ CAPCERSMDCL2_0402-10NF,16V_GEN I141 C63
2 P3V3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):P3V3
END LOGICAL PART CROSS REFERENCE
GLOBAL SIGNAL CROSS REFERENCE - 02-Sep-2020 AT 14:13:12
GLOBAL SIGNAL CROSS REFERENCE - 07-Oct-2020 AT 18:06:01
BEAM_TRIGGER_N<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):BEAM_TRIGGER_N(0)
J4 H38 H<38> ASP-134606-01 I1 @FMC_TLU_V1_LIB.PC036A_FMC_LPC_CONNECTOR(SCH_1):PAGE1
TP6_7 1 A<0> TP_HOLE-0.8MM I179 @FMC_TLU_V1_LIB.FMC_TLU_THRESHOLD_DISCRIMINATOR_DUAL(SCH_1):PAGE1
......@@ -4937,6 +4955,12 @@ NC NC
IC6 1 INT* PCA9539PW-VDD=P3V3,VSS=GND_SIGA I1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE6
IC7 1 INT* PCA9539PW-VDD=P3V3,VSS=GND_SIGA I6 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE6
SFP1 NC NC SFP_CAGE-SP-74737-004-GND=GND_A I5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7
RFT2 1 1 FIDUCIAL I149 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFT3 1 1 FIDUCIAL I150 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFB1 1 1 FIDUCIAL I151 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFB3 1 1 FIDUCIAL I152 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFB2 1 1 FIDUCIAL I153 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFT1 1 1 FIDUCIAL I154 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
P12V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):P12V
J4 C35 C<35> ASP-134606-01 I2 @FMC_TLU_V1_LIB.PC036A_FMC_LPC_CONNECTOR(SCH_1):PAGE1
......@@ -6526,7 +6550,7 @@ XB_9 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_C
R9_9 2 B<0> RSMD0402_1/16W-100,1% I48 @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3
END GLOBAL SIGNAL CROSS REFERENCE
GLOBAL PART CROSS REFERENCE - 02-Sep-2020 AT 14:13:12
GLOBAL PART CROSS REFERENCE - 07-Oct-2020 AT 18:06:01
C1 CAPCERSMDCL2_0603-1UF,16V
1 GND_SIGNAL @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):GND_SIGNAL I73 @FMC_TLU_V1_LIB.FMC_TLU_DAC_VTHRESH(SCH_1):PAGE1
......@@ -9529,6 +9553,24 @@ REG1_5 LT1175_SOT_223
2 M5V7_5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):M5V7 I40 @FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1
4 M5V7_5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):M5V7 I40 @FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1
RFB1 FIDUCIAL
1 NC NC I151 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFB2 FIDUCIAL
1 NC NC I153 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFB3 FIDUCIAL
1 NC NC I152 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFT1 FIDUCIAL
1 NC NC I154 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFT2 FIDUCIAL
1 NC NC I149 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RFT3 FIDUCIAL
1 NC NC I150 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1
RG1_5 LTM8047EY#PBF
H1 VIN_FILTERED_5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED I70 @FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1
H2 VIN_FILTERED_5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED I70 @FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):PAGE1
......
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pxl.chg
View file @ 38ac36fa
{ Packager-XL run on 02-Sep-2020 AT 14:13:16.00 }
{ Packager-XL run on 07-Oct-2020 AT 18:06:03.00 }
BINDING CHANGES LIST
......@@ -54,8 +54,6 @@ DELETED BINDINGS:
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I123@CNPASSIVE.RES_ARRAY_X4(CHIPS) (2) WAS ASSIGNED TO RN3_9 SECTION WITH PIN UNKNOWN
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I123@CNPASSIVE.RES_ARRAY_X4(CHIPS) (1) WAS ASSIGNED TO RN3_9 SECTION WITH PIN UNKNOWN
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I123@CNPASSIVE.RES_ARRAY_X4(CHIPS) (0) WAS ASSIGNED TO RN3_9 SECTION WITH PIN UNKNOWN
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7_I90@CNPASSIVE.RSMD0603(CHIPS) (0) WAS ASSIGNED TO R53 SECTION WITH PIN 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7_I112@CNPASSIVE.RSMD0402(CHIPS) (0) WAS ASSIGNED TO R94 SECTION WITH PIN 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I88@CNPASSIVE.CAPCERSMDCL2(CHIPS) (0) WAS ASSIGNED TO C7_1 SECTION WITH PIN 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I90@CNPASSIVE.CAPCERSMDCL2(CHIPS) (0) WAS ASSIGNED TO C8_1 SECTION WITH PIN 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I91@CNPASSIVE.CAPCERSMDCL2(CHIPS) (0) WAS ASSIGNED TO C6_1 SECTION WITH PIN 1
......@@ -129,8 +127,6 @@ DELETED BINDINGS:
CHANGED BINDINGS:
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7_I90@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_1/10W-100,1% (0) IS ASSIGNED TO R53 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7_I112@CNPASSIVE.RSMD0402(CHIPS) RSMD0402_0.0625W-XX,1% (0) IS ASSIGNED TO R94 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I88@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-100NF,16V_GEN (0) IS ASSIGNED TO C7_1 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I90@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-4.7NF,50V_GEN (0) IS ASSIGNED TO C8_1 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I91@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-4.7NF,50V_GEN (0) IS ASSIGNED TO C6_1 SECTION 1
......@@ -259,8 +255,6 @@ LOGICAL PARTS DELETED FROM DESIGN:
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I123@CNPASSIVE.RES_ARRAY_X4(CHIPS) (2) RN3_9 SECTION WITH PIN UNKNOWN
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I123@CNPASSIVE.RES_ARRAY_X4(CHIPS) (1) RN3_9 SECTION WITH PIN UNKNOWN
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I123@CNPASSIVE.RES_ARRAY_X4(CHIPS) (0) RN3_9 SECTION WITH PIN UNKNOWN
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7_I90@CNPASSIVE.RSMD0603(CHIPS) (0) R53 SECTION WITH PIN 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7_I112@CNPASSIVE.RSMD0402(CHIPS) (0) R94 SECTION WITH PIN 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I88@CNPASSIVE.CAPCERSMDCL2(CHIPS) (0) C7_1 SECTION WITH PIN 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I90@CNPASSIVE.CAPCERSMDCL2(CHIPS) (0) C8_1 SECTION WITH PIN 1
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I91@CNPASSIVE.CAPCERSMDCL2(CHIPS) (0) C6_1 SECTION WITH PIN 1
......@@ -334,8 +328,6 @@ LOGICAL PARTS DELETED FROM DESIGN:
LOGICAL PARTS ADDED TO DESIGN:
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7_I90@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_1/10W-100,1% (0)
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE7_I112@CNPASSIVE.RSMD0402(CHIPS) RSMD0402_0.0625W-XX,1% (0)
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I88@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-100NF,16V_GEN (0)
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I90@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-4.7NF,50V_GEN (0)
@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE4_I1@FMC_TLU_V1_LIB.FMC_TLU_HDMI_DUT_CONNECTOR(SCH_1):PAGE1_I91@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-4.7NF,50V_GEN (0)
......@@ -414,8 +406,6 @@ PHYSICAL CHANGES LIST
PHYSICAL PARTS ADDED TO DESIGN:
R94 RSMD0402_0.0625W-XX,1%
R53 RSMD0603_1/10W-100,1%
C39_9 CAPCERSMDCL2_0402-100NF,10V
C38_9 CAPCERSMDCL2_0402-100NF,10V
R26_9 RSMD0402_1/16W-100,1%
......@@ -489,8 +479,6 @@ C11_1 CAPCERSMDCL2_0402-100NF,10V
PHYSICAL PARTS DELETED FROM DESIGN:
R53 RSMD0603_1/10W-XX,1%
R94 RSMD0402_1/16W-0R0,1%
R1_9 RSMD0603_1/10W-100,1%
R3_9 RSMD0603_1/10W-100,1%
R4_9 RSMD0603_1/10W-100,1%
......
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pxl.dbg
View file @ 38ac36fa
Log File: /tmp/filernOugc
Markers File: /tmp/fileE0FwKZ
Debug File: /tmp/filep45kTA
Log File: /tmp/filet8gfOu
Markers File: /tmp/fileR7Etfw
Debug File: /tmp/fileuAxvdz
Debug[0] := TRUE
Elapsed time since start = (00:00:00)
......@@ -446,10 +446,10 @@ Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I122@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C39_9:1 to C39_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I127@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C41_9:1 to C41_9:1.
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I128@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C40_9:1 to C40_9:1.
Elapsed time since start = (00:00:03)
Elapsed time since start = (00:00:02)
*****************************************
* End loading State Files (00:00:01) *
* End loading State Files (00:00:00) *
*****************************************
......@@ -457,7 +457,7 @@ Elapsed time since start = (00:00:03)
* Starting to assign physical parts. *
****************************************
Elapsed time since start = (00:00:03)
Elapsed time since start = (00:00:02)
***********************************************
* End assigning physical parts. (00:00:00) *
......@@ -957,10 +957,10 @@ Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU
* Packaging *
***************
Elapsed time since start = (00:00:04)
Elapsed time since start = (00:00:02)
*******************************
* End packaging (00:00:01) *
* End packaging (00:00:00) *
*******************************
Ref des for prim inst @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE5_I1@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I128@CNPASSIVE.CAPCERSMDCL2(CHIPS) changed from C40_9:1 to C40_9:1.
......
Cadence/worklib/fmc_tlu_toplevel_f/packaged/pxl.state
View file @ 38ac36fa
FILE_TYPE = PXL_HDL_CENTRIC_STATE_FILE;
VERSION = PXL_HDL_CENTRIC_VERSION_1;
TIME = '02-Sep-2020 AT 14:13:16.00';
TIME = '07-Oct-2020 AT 18:06:03.00';
{--------------------------------------------------------------------------}
......@@ -141,6 +141,72 @@ BEGIN_LIB_INFO:
END_LIB_INFO;
END_PRIM;
BEGIN_PRIM:
PATH_NAME = '@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I149@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)';
LOCATION = 'RFT2';
SEC = '1';
BEGIN_LIB_INFO:
PRIM_FILE = '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_special/fiducial/chips/chips.prt';
PART_NAME = 'FIDUCIAL';
END_LIB_INFO;
END_PRIM;
BEGIN_PRIM:
PATH_NAME = '@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I150@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)';
LOCATION = 'RFT3';
SEC = '1';
BEGIN_LIB_INFO:
PRIM_FILE = '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_special/fiducial/chips/chips.prt';
PART_NAME = 'FIDUCIAL';
END_LIB_INFO;
END_PRIM;
BEGIN_PRIM:
PATH_NAME = '@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I151@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)';
LOCATION = 'RFB1';
SEC = '1';
BEGIN_LIB_INFO:
PRIM_FILE = '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_special/fiducial/chips/chips.prt';
PART_NAME = 'FIDUCIAL';
END_LIB_INFO;
END_PRIM;
BEGIN_PRIM:
PATH_NAME = '@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I152@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)';
LOCATION = 'RFB3';
SEC = '1';
BEGIN_LIB_INFO:
PRIM_FILE = '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_special/fiducial/chips/chips.prt';
PART_NAME = 'FIDUCIAL';
END_LIB_INFO;
END_PRIM;
BEGIN_PRIM:
PATH_NAME = '@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I153@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)';
LOCATION = 'RFB2';
SEC = '1';
BEGIN_LIB_INFO:
PRIM_FILE = '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_special/fiducial/chips/chips.prt';
PART_NAME = 'FIDUCIAL';
END_LIB_INFO;
END_PRIM;
BEGIN_PRIM:
PATH_NAME = '@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):PAGE1_I154@BRIS_CDS_SPECIAL.FIDUCIAL(CHIPS)';
LOCATION = 'RFT1';
SEC = '1';
BEGIN_LIB_INFO:
PRIM_FILE = '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_special/fiducial/chips/chips.prt';
PART_NAME = 'FIDUCIAL';
END_LIB_INFO;
END_PRIM;
BEGIN_SIGNAL:
CANON_SIGNAL = '@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):BEAM_TRIGGER_N(0)';
LOG_SIGNAL = '@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1):BEAM_TRIGGER_N(0)';
......@@ -12599,40 +12665,41 @@ END_MODULE; { end of module '@FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_F(SCH_1)'}
BEGIN_REFDES_LIST:
TP4_8, IC3_9, R72, D12, R5_6, R20_9, C1, R73, R110, D13, C6_1, R5_7, L5_9, C2, ~
R74, R111, D14, C6_2, R5_8, C3, SFP1, R75, R112, D15, C6_3, C22_9, R5_9, C4, R76, ~
R113, D16, C6_4, C5, R77, R114, C6_5, C6, R78, R115, C6_6, R17_9, C7, R79, C6_7, ~
RN3_9, C8, C10_1, C6_8, C9, C53_2, C10_2, C6_9, C19_9, C53_3, C10_3, C53_4, C1~
0_4, C10_5, C36_9, C10_6, TP6_1, RG1_5, C10_7, TP6_2, C10_8, C40, TP6_3, QZ1_9, ~
C10_9, C41, D1_1, TP6_4, C42, D1_2, C43, J1_1, D1_3, TP6_6, C44, J1_2, D1_4, T~
P6_7, C45, J1_3, TP6_8, IC5_9, C46, J1_4, R7_6, D1_6, R22_9, C47, C8_1, R7_7, ~
D1_7, L7_9, C48, C8_2, R7_8, D1_8, C49, C8_3, C24_9, R7_9, C8_4, C8_5, J1_9, C~
8_6, R19_9, C41_9, C8_7, R30, C12_1, C8_8, R31, C55_2, C12_2, C8_9, R32, C55_3, ~
C12_3, R10_6, R33, C55_4, C12_4, R10_7, R34, C12_5, R10_8, R35, C38_9, C12_6, ~
R10_9, R36, TP8_1, C12_7, R37, TP8_2, C12_8, R38, TP8_3, C12_9, R39, D3_1, TP8_4, ~
R1, R84_2, D3_2, LK1_9, R2, R84_3, D3_3, TP8_6, R3, R84_4, D3_4, TP8_7, R4, R80, ~
TP8_8, IC7_9, R5, R81, R9_6, R24_9, R6, R82, R9_7, R7, R83, D1, R9_8, R8, R84, ~
D2, D3_9, R9_9, C26_9, R9, R85, D3, R86, D4, R87, D5, R88, D6, R89, D7, C1_1, D8, ~
C57_2, C1_2, D9, C57_3, C1_3, R12_6, C57_4, C1_4, R12_7, C1_5, R12_8, C1_6, C1~
4_6, R12_9, C1_7, C14_7, C1_8, C14_8, C1_9, C14_9, C50, TP10_1, C51, R86_2, TP~
10_2, LK3_9, C52, R86_3, TP10_3, C31_9, R86_4, C53, TP10_4, C54, TP1_1, C55, L~
2_1, TP1_2, U1_9, R26_9, C56, L2_2, TP1_3, C57, R2_1, L2_3, TP1_4, C58, R2_2, ~
L2_4, C28_9, C59, R2_3, L2_5, TP1_6, R2_4, TP1_7, R2_5, TP1_8, R2_6, C3_1, R2_7, ~
L2_9, R40, C3_2, R2_8, R41, C3_3, R2_9, R42, R57_7, C3_4, R43, R57_8, R91_2, C~
3_5, R44, R91_3, C3_6, R14_9, R45, R91_4, C3_7, R46, C3_8, R47, C3_9, C16_9, R48, ~
TP12_1, CN2_9, R49, R88_2, TP12_2, R88_3, TP12_3, C33_9, TP1, R88_4, IC2_1, TP~
12_4, TP2, TP3_1, IC2_2, TP3, R90, L4_1, TP3_2, IC2_3, TP4, R91, L4_2, TP3_3, ~
IC2_4, TP5, IC10, R92, L4_3, TP3_4, TP6, IC11, R93, L4_4, IC12, TP7, R94, TP3_6, ~
C10, TP8, R95, IC13, TP3_7, LD1, C11, R96, TP9, IC14, RN2_1, TP3_8, IC2_9, LD2, ~
C12, R97, IC15, RN2_2, R4_6, LD3, C13, R98, IC16, C5_1, RN2_3, R4_7, L4_9, C14, ~
R99, C5_2, RN2_4, R4_8, C15, C5_3, R4_9, C21_9, C16, R59_7, C5_4, C17, R59_8, ~
C5_5, C18, C5_6, R16_9, C19, C5_7, RN2_9, C5_8, J1, C5_9, C18_9, J2, J3, C60, J4, ~
C61, C35_9, C62, C63, TP5_1, C64, TP5_2, C65, TP5_3, C66, TP5_4, C67, C68, TP5_6, ~
TP5_7, TP5_8, IC4_9, R6_6, R21_9, C7_1, R6_7, L6_9, C7_2, R6_8, R50, C7_3, R6_9, ~
C23_9, R51, C7_4, IC1, R52, C7_5, IC2, R53, C7_6, R18_9, IC3, C40_9, R54, C7_7, ~
IC4, R55, C11_1, C7_8, IC5, R56, C54_2, C11_2, C7_9, IC6, R57, C54_3, C11_3, IC7, ~
R58, C54_4, C11_4, IC8, R59, C11_5, C37_9, IC9, C11_6, TP7_1, RG2_5, C11_7, TP~
7_2, C11_8, TP7_3, C11_9, D2_1, TP7_4, D2_2, D2_3, TP7_6, D2_4, TP7_7, C20, TP~
7_8, IC6_9, C21, R8_6, D2_6, R23_9, C22, C9_1, R8_7, D2_7, L8_9, C23, C9_2, R8_8, ~
D2_8, C24, C9_3, C25_9, R8_9, C25, C9_4, REG1_5, C26, C9_5, C27, C9_6, C28, C9_7, ~
R113, D16, C6_4, C5, R77, R114, C6_5, C6, R78, R115, RFT1, C6_6, R17_9, C7, R79, ~
RFT2, C6_7, RN3_9, C8, RFT3, C10_1, C6_8, C9, C53_2, C10_2, C6_9, C19_9, C53_3, ~
C10_3, C53_4, C10_4, C10_5, C36_9, C10_6, TP6_1, RG1_5, C10_7, TP6_2, C10_8, C40, ~
TP6_3, QZ1_9, C10_9, C41, D1_1, TP6_4, C42, D1_2, C43, J1_1, D1_3, TP6_6, C44, ~
J1_2, D1_4, TP6_7, C45, J1_3, TP6_8, IC5_9, C46, J1_4, R7_6, D1_6, R22_9, C47, ~
C8_1, R7_7, D1_7, L7_9, C48, C8_2, R7_8, D1_8, C49, C8_3, C24_9, R7_9, C8_4, C~
8_5, J1_9, C8_6, R19_9, C41_9, C8_7, R30, C12_1, C8_8, R31, C55_2, C12_2, C8_9, ~
R32, C55_3, C12_3, R10_6, R33, C55_4, C12_4, R10_7, R34, C12_5, R10_8, R35, C3~
8_9, C12_6, R10_9, R36, TP8_1, C12_7, R37, TP8_2, C12_8, R38, TP8_3, C12_9, R39, ~
D3_1, TP8_4, R1, R84_2, D3_2, LK1_9, R2, R84_3, D3_3, TP8_6, R3, R84_4, D3_4, ~
TP8_7, R4, R80, TP8_8, IC7_9, R5, R81, RFB1, R9_6, R24_9, R6, R82, RFB2, R9_7, ~
R7, R83, D1, RFB3, R9_8, R8, R84, D2, D3_9, R9_9, C26_9, R9, R85, D3, R86, D4, ~
R87, D5, R88, D6, R89, D7, C1_1, D8, C57_2, C1_2, D9, C57_3, C1_3, R12_6, C57_4, ~
C1_4, R12_7, C1_5, R12_8, FID1, C1_6, C14_6, R12_9, FID2, C1_7, C14_7, FID3, C~
1_8, C14_8, FID4, C1_9, C14_9, C50, FID5, TP10_1, C51, R86_2, FID6, TP10_2, LK~
3_9, C52, R86_3, TP10_3, C31_9, R86_4, C53, TP10_4, C54, TP1_1, C55, L2_1, TP1_2, ~
U1_9, R26_9, C56, L2_2, TP1_3, C57, R2_1, L2_3, TP1_4, C58, R2_2, L2_4, C28_9, ~
C59, R2_3, L2_5, TP1_6, R2_4, TP1_7, R2_5, TP1_8, R2_6, C3_1, R2_7, L2_9, R40, ~
C3_2, R2_8, R41, C3_3, R2_9, R42, R57_7, C3_4, R43, R57_8, R91_2, C3_5, R44, R~
91_3, C3_6, R14_9, R45, R91_4, C3_7, R46, C3_8, R47, C3_9, C16_9, R48, TP12_1, ~
CN2_9, R49, R88_2, TP12_2, R88_3, TP12_3, C33_9, TP1, R88_4, IC2_1, TP12_4, TP2, ~
TP3_1, IC2_2, TP3, R90, L4_1, TP3_2, IC2_3, TP4, R91, L4_2, TP3_3, IC2_4, TP5, ~
IC10, R92, L4_3, TP3_4, TP6, IC11, R93, L4_4, IC12, TP7, R94, TP3_6, C10, TP8, ~
R95, IC13, TP3_7, LD1, C11, R96, TP9, IC14, RN2_1, TP3_8, IC2_9, LD2, C12, R97, ~
IC15, RN2_2, R4_6, LD3, C13, R98, IC16, C5_1, RN2_3, R4_7, L4_9, C14, R99, C5_2, ~
RN2_4, R4_8, C15, C5_3, R4_9, C21_9, C16, R59_7, C5_4, C17, R59_8, C5_5, C18, ~
C5_6, R16_9, C19, C5_7, RN2_9, C5_8, J1, C5_9, C18_9, J2, J3, C60, J4, C61, C3~
5_9, C62, C63, TP5_1, C64, TP5_2, C65, TP5_3, C66, TP5_4, C67, C68, TP5_6, TP5_7, ~
TP5_8, IC4_9, R6_6, R21_9, C7_1, R6_7, L6_9, C7_2, R6_8, R50, C7_3, R6_9, C23_9, ~
R51, C7_4, IC1, R52, C7_5, IC2, R53, C7_6, R18_9, IC3, C40_9, R54, C7_7, IC4, ~
R55, C11_1, C7_8, IC5, R56, C54_2, C11_2, C7_9, IC6, R57, C54_3, C11_3, IC7, R58, ~
C54_4, C11_4, IC8, R59, C11_5, C37_9, IC9, C11_6, TP7_1, RG2_5, C11_7, TP7_2, ~
C11_8, TP7_3, C11_9, D2_1, TP7_4, D2_2, D2_3, TP7_6, D2_4, TP7_7, C20, TP7_8, ~
IC6_9, C21, R8_6, D2_6, R23_9, C22, C9_1, R8_7, D2_7, L8_9, C23, C9_2, R8_8, D~
2_8, C24, C9_3, C25_9, R8_9, C25, C9_4, REG1_5, C26, C9_5, C27, C9_6, C28, C9_7, ~
C29, C13_1, C9_8, C56_2, C13_2, C9_9, C56_3, C13_3, R11_6, C56_4, C70, C13_4, ~
R11_7, R11_8, R10, C39_9, C13_6, R11_9, R11, TP9_1, C13_7, R12, TP9_2, C13_8, ~
R13, TP9_3, C13_9, R14, TP9_4, R15, R85_2, VR1_5, LK2_9, R16, R85_3, D4_2, C30_9, ~
......
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G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: fmc_tlu_v1e_144.brd*
G04 Film Name: OUTLINE*
G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-2015-S079*
G04 Origin Date: Thu May 18 13:49:56 2017*
G04 *
G04 Layer: BOARD GEOMETRY/OUTLINE*
G04 *
G04 Offset: (0.0000 0.0000)*
G04 Mirror: No*
G04 Mode: Positive*
G04 Rotation: 0*
G04 FullContactRelief: No*
G04 UndefLineWidth: 0.0500*
G04 ================== end FILE IDENTIFICATION RECORD ====================*
%FSLAX35Y35*MOMM*%
%IR0*IPPOS*OFA0.00000B0.00000*MIA0B0*SFA1.00000B1.00000*%
%ADD10C,.05*%
G75*
%LPD*%
G75*
G54D10*
G01X23000000Y0D02*
X0D01*
Y11500000D01*
X23000000D01*
Y0D01*
M02*
Cadence/worklib/fmc_tlu_toplevel_f/physical/README
View file @ 38ac36fa
fmc_tlu_v1a
fmc_tlu_v1f , release 38
These file describes PCB fabrication and assembly details of a
FMC based "mini TLU" for the AIDA project.
FMC based TLU for the AIDA-2020 project.
contact: David.Cussans@bristol.ac.uk
tel: 0117 95 46879
0117 33 17199
fax: 0117 925 5624
P.Baesso@bristol.ac.uk
tel: 0117 928 7481
Files produced by Cadence Allegro PE16.6
Files produced by Cadence Allegro PE17.2
Artwork:
--------
......@@ -26,12 +23,12 @@ Build:
Six Layers as follows:
fmc_tlu_v1d_55_L01P.ger
fmc_tlu_v1d_55_L02P.ger
fmc_tlu_v1d_55_L03P.ger
fmc_tlu_v1d_55_L04P.ger
fmc_tlu_v1d_55_L05P.ger
fmc_tlu_v1d_55_L06P.ger
art_tlu_v1f_L1P_38.art
art_tlu_v1f_L2P_38.art
art_tlu_v1f_L3P_38.art
art_tlu_v1f_L4P_38.art
art_tlu_v1f_L5P_38.art
art_tlu_v1f_L6P_38.art
Suggested build (1.6mm total thickness)
1-2 0.22 mm
......@@ -48,80 +45,78 @@ FR4 or similar laminate
Solder Masks
------------
fmc_tlu_v1d_55_LSM1.ger
fmc_tlu_v1d_55_LSM2.ger
art_tlu_v1f_SM1_38.art
art_tlu_v1f_SM2_38.art
Colour not critical, suggest green. Photo-imagable.
Solderpaste mask
-----------------
fmc_tlu_v1d_55_SMD1.ger
fmc_tlu_v1d_55_SMD2.ger
art_tlu_v1f_SP1_38.art
art_tlu_v1f_SP6_38.art
Silk screen
-----------
fmc_tlu_v1d_55_POS1.ger
fmc_tlu_v1d_55_POS2.ger
art_tlu_v1f_SS1_38.art
art_tlu_v1f_SILKSCREENPKG_TOP_38.art
art_tlu_v1f_SILKSCREENTOP_38.art
art_tlu_v1f_SS6_38.art
art_tlu_v1f_SILKSCREENBOTTOM_38.art
art_tlu_v1f_SILKSCREENPGK_BOTTOM_38.art
Colour not critical, suggest white.
Assembly Diagram
-----------------
fmc_tlu_v1d_55_ASSEMBLY_TOP.ger
fmc_tlu_v1d_55_ASSEMBLY_BOTTOM.ger
art_tlu_v1f_AST_38.art
art_tlu_v1f_ASB_38.art
Board outline: (Gerber RS-274X)
-------------------------------
fmc_tlu_v1d_55_OUTLINE.ger
art_tlu_v1f_OUTLINE_38.art
For details of FMC standard board outline see ansi_vita_57.1_double_fmc_outline.pdf
For details of cut-out for J3 ( Molex 44661-1011 very-low-height RJ45 connector ) see 446611011_sd.pdf
Some dimensions shown on:
fmc_tlu_v1d_55_DIMENSION.ger
Drill figure: ( illustration of hole sizes and position )
-------------
fmc_tlu_v1d_55_BOHR.ger
art_tlu_v1f_DD_38.art
Drill information ( Excellon format, described in nc_param.txt )
-----------------
Plated and unplated holes in same file.
fmc_tlu_v1d_55_NC1.exc
art_tlu_v1f_NC-1-6.drl
Routing Information
-------------------
Centre-line for router
fmc_tlu_v1d_55.rou
art_fmc_tlu_v1f_1-6.rou
Bill of Materials
-----------------
Two "sheets":
- one line per component type
- one line per component instance ( includes position information )
fmc_tlu_v1d.xlsx
bom_v1f_38.xlsx
Component placement
-------------------
placement_pin1.txt
placement_bodycentre_38.txt
( Position of pin-1 in mm and rotation in degrees of each component )
( Position of body centre in mm and rotation in degrees of each component )
IPC-2581 format:
ODB++ format:
-------------
Fabrication and assembly information in
fmc_tlu_v1d_55.xml
\ No newline at end of file
fmc_tlu_v1f_38.tgz
\ No newline at end of file
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DEVICE-TYPE GERBER_RS274X
OUTPUT-UNITS MM
FILM-SIZE 2400000 1600000
FORMAT 2.5
ABORT-ON-ERROR NO
SCALE 1
SUPPRESS-LEAD-ZEROES YES
SUPPRESS-TRAIL-ZEROES NO
SUPPRESS-EQUAL YES
UNDEF-APT-CONT NO
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(---------------------------------------------------------------------)
( )
( Dangling Line and Via Report )
( )
( Drawing : fmc_tlu_v1f_38.brd )
( Software Version : 17.2S061 )
( Date/Time : Wed Oct 7 20:00:25 2020 )
( )
(---------------------------------------------------------------------)
Report methodology:
- Dangling lines have at least one end not connected.
- Dangling vias have one or no connection
- Plus are not a test, thieving or netshort property via.
- Not part of the current partition.
- To suppress items in dangle report add the OK_DANGLE property to the via
or connect line.
<< Dangling Lines >> - Location marked with a star (*) is dangling.
Net Layer Length Location
------------------------------------------------------------------------------------------
VCCA BOTTOM 0.0556 *(81.9444 93.2500) to (82.0000 93.2500)
<< Dangling Vias >>
Net Padstack Location Layers
---------------------------------------------------------------------------
VREF_A_M2C VIA (132.9650 13.1570) TOP/BOTTOM
VP1<0>_5 VIA (31.0881 23.9931) TOP/BOTTOM
VP1<0>_5 VIA (32.3581 23.9931) TOP/BOTTOM
VP1<0>_5 VIA (32.3581 22.7231) TOP/BOTTOM
VP1<0>_5 VIA (31.0881 22.7231) TOP/BOTTOM
VP1<0>_5 VIA (32.3581 21.4531) TOP/BOTTOM
VP1<0>_5 VIA (31.0881 21.4531) TOP/BOTTOM
VM2<0>_5 VIA (5.6419 23.9931) TOP/BOTTOM
VM2<0>_5 VIA (8.1819 21.4531) TOP/BOTTOM
VM2<0>_5 VIA (6.9119 22.7231) TOP/BOTTOM
VM2<0>_5 VIA (5.6419 22.7231) TOP/BOTTOM
VM2<0>_5 VIA (6.9119 21.4531) TOP/BOTTOM
VM2<0>_5 VIA (5.6419 21.4531) TOP/BOTTOM
VM2<0>_5 VIA (11.8181 22.7231) TOP/BOTTOM
VM2<0>_5 VIA (11.8181 23.9931) TOP/BOTTOM
VM2<0>_5 VIA (10.5481 22.7231) TOP/BOTTOM
VM2<0>_5 VIA (10.5481 23.9931) TOP/BOTTOM
VM2<0>_5 VIA (10.5481 21.4531) TOP/BOTTOM
VM2<0>_5 VIA (8.1819 22.7231) TOP/BOTTOM
VM2<0>_5 VIA (8.1819 23.9931) TOP/BOTTOM
VM2<0>_5 VIA (6.9119 23.9931) TOP/BOTTOM
VM2<0>_5 VIA (11.8181 21.4531) TOP/BOTTOM
VIN_FILTERED_5 VIA (29.8181 14.0069) TOP/BOTTOM
VIN_FILTERED_5 VIA (26.1819 16.5469) TOP/BOTTOM
VIN_FILTERED_5 VIA (24.9119 15.2769) TOP/BOTTOM
VIN_FILTERED_5 VIA (24.9119 14.0069) TOP/BOTTOM
VIN_FILTERED_5 VIA (23.6419 14.0069) TOP/BOTTOM
VIN_FILTERED_5 VIA (23.6419 15.2769) TOP/BOTTOM
VIN_FILTERED_5 VIA (6.9119 14.0069) TOP/BOTTOM
VIN_FILTERED_5 VIA (11.8181 14.0069) TOP/BOTTOM
VIN_FILTERED_5 VIA (8.1819 16.5469) TOP/BOTTOM
VIN_FILTERED_5 VIA (6.9119 15.2769) TOP/BOTTOM
VIN_FILTERED_5 VIA (5.6419 14.0069) TOP/BOTTOM
VIN_FILTERED_5 VIA (5.6419 15.2769) TOP/BOTTOM
UNNAMED_8_PCA9517_I2_EN VIA (202.8048 24.2500) TOP/BOTTOM
UNNAMED_1_LTM8047_I82_ADJ_5 VIA (31.6700 12.7500) TOP/BOTTOM
UNNAMED_1_LTM8047_I70_ADJ_5 VIA (16.8000 15.5500) TOP/BOTTOM
UNNAMED_1_CAPCERSMDCL2_I185_B_6 VIA (15.7048 84.0000) TOP/BOTTOM
UNNAMED_1_AD5665R_I80_ADDR2 VIA (30.0000 44.7952) TOP/BOTTOM
TRST_L VIA (91.0550 8.0770) TOP/BOTTOM
SFP_TX_FAULT_FPGA VIA (101.2150 8.0770) TOP/BOTTOM
SFP_TX_FAULT_FPGA VIA (220.3000 18.6452) TOP/BOTTOM
SFP_TX_DISABLE_FPGA VIA (99.9450 9.7230) TOP/BOTTOM
SFP_TX_DISABLE_FPGA VIA (210.3000 18.6452) TOP/BOTTOM
SFP_LOS_FPGA VIA (99.9450 7.7550) TOP/BOTTOM
SFP_LOS_FPGA VIA (221.5000 18.6452) TOP/BOTTOM
SDA VIA (94.8650 4.9650) TOP/BOTTOM
SCL VIA (96.1350 4.6430) TOP/BOTTOM
P5V VIA (74.3202 99.0500) TOP/BOTTOM
P5V VIA (61.3202 99.0500) TOP/BOTTOM
P5V VIA (46.3202 99.0500) TOP/BOTTOM
P5V VIA (33.3202 99.0500) TOP/BOTTOM
P5V VIA (18.3202 99.0500) TOP/BOTTOM
P5V VIA (5.3202 99.0500) TOP/BOTTOM
P12V VIA (87.2450 4.9650) TOP/BOTTOM
P12V VIA (89.7850 4.9650) TOP/BOTTOM
GBTCLK0_M2C* VIA (127.8850 7.7550) TOP/BOTTOM
GBTCLK0_M2C VIA (129.1550 7.8000) TOP/BOTTOM
GA1 VIA (89.7850 7.7550) TOP/BOTTOM
GA0 VIA (91.0550 4.6430) TOP/BOTTOM
FPGA_TDO VIA (96.1350 8.0770) TOP/BOTTOM
FMC_TMS_BUF VIA (92.3250 7.7550) TOP/BOTTOM
FMC_TDO VIA (94.8650 7.7550) TOP/BOTTOM
FMC_TCK_BUF VIA (97.4050 7.7550) TOP/BOTTOM
FMC_PWR_GOOD_FLASH_RST_B VIA (132.9650 7.7550) TOP/BOTTOM
FMC_PRSNT_M2C_L VIA (131.6950 12.8350) TOP/BOTTOM
FMC_LA<8> VIA (118.9950 10.0450) TOP/BOTTOM
FMC_LA<7> VIA (117.7250 13.1570) TOP/BOTTOM
FMC_LA<4> VIA (121.5350 12.8350) TOP/BOTTOM
FMC_LA<11> VIA (113.9150 12.8350) TOP/BOTTOM
FMC_LA<10> VIA (116.4550 4.6430) TOP/BOTTOM
FMC_LA*<8> VIA (117.7250 10.0000) TOP/BOTTOM
FMC_LA*<7> VIA (116.4550 12.8350) TOP/BOTTOM
FMC_LA*<4> VIA (120.2650 13.1570) TOP/BOTTOM
FMC_LA*<25> VIA (98.6750 10.0450) TOP/BOTTOM
FMC_LA*<11> VIA (112.6450 13.1570) TOP/BOTTOM
FMC_LA*<10> VIA (115.1850 4.9650) TOP/BOTTOM
ENABLE_CLK_TO_DUT<2> VIA (131.4815 75.5185) TOP/BOTTOM
ENABLE_CLK_TO_DUT<1> VIA (157.3000 75.4000) TOP/BOTTOM
ENABLE_CLK_TO_DUT<0> VIA (183.4630 75.5000) TOP/BOTTOM
DUT_CLK_TO_FPGA<1> VIA (107.5650 7.7550) TOP/BOTTOM
DUT_CLK_FROM_FPGA<1> VIA (108.8350 8.0770) TOP/BOTTOM
DP0_M2C* VIA (125.3450 4.9650) TOP/BOTTOM
DP0_M2C VIA (126.6150 4.9979) TOP/BOTTOM
DP0_C2M* VIA (130.4250 4.9650) TOP/BOTTOM
DP0_C2M VIA (131.6950 4.9979) TOP/BOTTOM
CONT_TO_FPGA<3> VIA (121.5350 10.0450) TOP/BOTTOM
CONT_TO_FPGA<0> VIA (125.3450 10.0000) TOP/BOTTOM
CONT_FROM_FPGA<3> VIA (122.8050 10.0779) TOP/BOTTOM
CONT_FROM_FPGA<0> VIA (126.6150 10.0450) TOP/BOTTOM
CLK_GEN_RST_N VIA (101.2150 12.8350) TOP/BOTTOM
CDR_LOS VIA (103.7550 10.0450) TOP/BOTTOM
BUSY_TO_FPGA<3> VIA (108.8350 12.8350) TOP/BOTTOM
BUSY_TO_FPGA<0> VIA (113.9150 10.0450) TOP/BOTTOM
BUSY_FROM_FPGA<3> VIA (110.1050 13.1570) TOP/BOTTOM
BUSY_FROM_FPGA<2> VIA (111.3750 4.6430) TOP/BOTTOM
BEAM_TRIGGER_P<0> VIA (87.2450 13.1570) TOP/BOTTOM
BEAM_TRIGGER_N<0> VIA (85.9750 12.8350) TOP/BOTTOM
P3V3 VIA (98.3048 72.0000) TOP/BOTTOM
<< Summary >>
Total dangling lines: 1
Total dangling vias: 99
Cadence/worklib/fmc_tlu_toplevel_f/physical/nc_param.txt
View file @ 38ac36fa
INTEGER-PLACES 3
DECIMAL-PLACES 5
X-OFFSET 0.000000
Y-OFFSET 0.000000
FEEDRATE 1
COORDINATES ABSOLUTE
OUTPUT-UNITS METRIC
TOOL-ORDER INCREASING
REPEAT-CODES YES
SUPPRESS-LEAD-ZEROES NO
SUPPRESS-TRAIL-ZEROES NO
SUPPRESS-EQUAL NO
TOOL-SELECT YES
OPTIMIZE_DRILLING NO
ENHANCED_EXCELLON YES
TAPE-FILE P:/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/art_tlu_v1f_NC.drl
ROUTE-FILE P:/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/art_fmc_tlu_v1f.rou
HEADER none
LEADER 12
CODE ASCII
SEPARATE NO
SEPARATE-ROUTING NO
DRILLING LAYER-PAIR
BACKDRILL NO
COUNTER NO
CAVITY NO
TOLERANCE_DRILL NO
TOLERANCE_TRAVEL YES
TOOL_SIZE NO
ROTATION YES
NON_STANDARD NO
TOTAL_DRILL YES
SEPARATE_SLOT NO
SUPPRESS_TOLERANCE YES
SUPPRESS_TOOLSIZE NO
SUPPRESS_ROTATION YES
INTEGER-PLACES 3
DECIMAL-PLACES 5
X-OFFSET 0.000000
Y-OFFSET 0.000000
FEEDRATE 1
COORDINATES ABSOLUTE
OUTPUT-UNITS METRIC
TOOL-ORDER INCREASING
REPEAT-CODES YES
SUPPRESS-LEAD-ZEROES NO
SUPPRESS-TRAIL-ZEROES NO
SUPPRESS-EQUAL NO
TOOL-SELECT YES
OPTIMIZE_DRILLING NO
ENHANCED_EXCELLON YES
TAPE-FILE /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/art_tlu_v1f_NC.drl
ROUTE-FILE /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/art_fmc_tlu_v1f.rou
HEADER none
LEADER 12
CODE ASCII
SEPARATE NO
SEPARATE-ROUTING NO
DRILLING LAYER-PAIR
BACKDRILL NO
CAVITY NO
COUNTER NO
TOLERANCE_DRILL NO
TOLERANCE_TRAVEL YES
TOOL_SIZE NO
ROTATION YES
NON_STANDARD NO
TOTAL_DRILL YES
SEPARATE_SLOT NO
SUPPRESS_TOLERANCE YES
SUPPRESS_TOOLSIZE NO
SUPPRESS_ROTATION YES
Cadence/worklib/fmc_tlu_toplevel_f/physical/nc_tools_auto.txt
View file @ 38ac36fa
0.3000 P T01 0.000000 0.000000
0.3302 P T02 0.000000 0.000000
0.4064 P T03 0.000000 0.000000
0.6000 P T04 0.000000 0.000000
0.8128 P T05 0.000000 0.000000
0.8499 P T06 0.000000 0.000000
0.9000 P T07 0.000000 0.000000
0.9144 P T08 0.000000 0.000000
0.9500 P T09 0.000000 0.000000
1.0000 P T10 0.000000 0.000000
1.0500 P T11 0.000000 0.000000
2.6924 P T12 0.000000 0.000000
1.3005 N T13 0.000000 0.000000
1.5500 N T14 0.000000 0.000000
0.3000 P T01 0.000000 0.000000
0.3302 P T02 0.000000 0.000000
0.4064 P T03 0.000000 0.000000
0.6000 P T04 0.000000 0.000000
0.8128 P T05 0.000000 0.000000
0.8499 P T06 0.000000 0.000000
0.9000 P T07 0.000000 0.000000
0.9144 P T08 0.000000 0.000000
0.9500 P T09 0.000000 0.000000
1.0000 P T10 0.000000 0.000000
1.0500 P T11 0.000000 0.000000
2.6924 P T12 0.000000 0.000000
1.3005 N T13 0.000000 0.000000
1.5500 N T14 0.000000 0.000000
Cadence/worklib/fmc_tlu_toplevel_f/physical/netrev.lst
View file @ 38ac36fa
......@@ -2,9 +2,9 @@
( )
( Allegro Netrev Import Logic )
( )
( Drawing : fmc_tlu_v1f_35.brd )
( Drawing : fmc_tlu_v1f_37.brd )
( Software Version : 17.2S061 )
( Date/Time : Wed Sep 2 14:13:22 2020 )
( Date/Time : Wed Oct 7 18:06:06 2020 )
( )
(---------------------------------------------------------------------)
......@@ -19,19 +19,19 @@ Missing symbol has error: No
DRC update: Yes
Schematic directory: '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged'
Design Directory: '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical'
Old design name: '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/fmc_tlu_v1f_35.brd'
New design name: '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/fmc_tlu_v1f_36.brd'
Old design name: '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/fmc_tlu_v1f_37.brd'
New design name: '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/fmc_tlu_v1f_38.brd'
CmdLine: netrev -proj /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/fmc_tlu_v1f.cpm -y 1 -O /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/fmc_tlu_v1f_35.brd /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/fmc_tlu_v1f_36.brd -q /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/temp/constraints_difference_report.xml -$
CmdLine: netrev -proj /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/fmc_tlu_v1f.cpm -y 1 -O /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/fmc_tlu_v1f_37.brd /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/physical/fmc_tlu_v1f_38.brd -q /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/temp/constraints_difference_report.xml -$
------ Preparing to read pst files ------
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstchip.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstchip.dat (00:00:01.16)
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstchip.dat (00:00:00.73)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxprt.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxprt.dat (00:00:00.02)
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxprt.dat (00:00:00.01)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxnet.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxnet.dat (00:00:00.01)
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstxnet.dat (00:00:00.00)
------ Oversights/Warnings/Errors ------
......@@ -41,8 +41,8 @@ Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/
===========================================================
Start Constraint Diff3 Import
Constraint File: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/worklib/fmc_tlu_toplevel_f/packaged/pstcmdb.dat
Allegro Baseline: /tmp/#Taaaaag17636.tmp
Start time: Wed Sep 2 14:13:23 2020
Allegro Baseline: /tmp/#Taaaaag07166.tmp
Start time: Wed Oct 7 18:06:07 2020
===========================================================
......@@ -50,7 +50,7 @@ The constraint difference report file can be viewed using the following command:
cdnFlowOOSMsg.exe -file file:///projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu-hw/Cadence/temp/constraints_difference_report.xml
===========================================================
Finished Constraint Update Time: Wed Sep 2 14:13:23 2020
Finished Constraint Update Time: Wed Oct 7 18:06:07 2020
===========================================================
------ Library Paths ------
......@@ -100,9 +100,9 @@ PADPATH = .
------ Summary Statistics ------
netrev run on Sep 2 14:13:21 2020
netrev run on Oct 7 18:06:05 2020
DESIGN NAME : 'FMC_TLU_TOPLEVEL_F'
PACKAGING ON 02-Sep-2020 AT 14:13:12
PACKAGING ON 07-Oct-2020 AT 18:06:01
COMPILE 'logic'
CHECK_PIN_NAMES OFF
......@@ -134,6 +134,6 @@ netrev run on Sep 2 14:13:21 2020
No oversight detected
No warning detected
cpu time 0:00:03
cpu time 0:00:02
elapsed time 0:00:02
Cadence/worklib/fmc_tlu_toplevel_f/physical/package_manufacturing_artwork.sh 100644 → 100755
View file @ 38ac36fa
......@@ -25,19 +25,19 @@ cp *.rou $SUBDIR
cp nc_tools_auto.txt $SUBDIR
cp nc_param.txt $SUBDIR
cp art_param.txt $SUBDIR
cp *.pdf $SUBDIR
# cp *.pdf $SUBDIR
#
# copy ODB++ file if any.
cp *.tgz $SUBDIR
#
# copy IPC-2581 file if any.
cp *.xml $SUBDIR
# cp *.xml $SUBDIR
#
cp README $SUBDIR
cp *.doc $SUBDIR
#
# Copy the placement information
cp *placement*.txt $SUBDIR
cp placement*.txt $SUBDIR
#
# Copy the bill of materials
cp ../bom/*.{xls,xlsx} $SUBDIR
......
Cadence/worklib/fmc_tlu_toplevel_f/physical/place_txt.txt deleted 100644 → 0
View file @ 8b3d2120
UUNITS = MILLIMETERS
J4 11.7476 58.0700 0 SAMTEC_MHDMI-19
J1 101.4891 1.0485 180 SAMTEC_ASP-134606-01
IC8 49.6381 30.4850 90 SOIC127P600X175-14N
Cadence/worklib/fmc_tlu_toplevel_f/physical/tlu_OUTLINE_v1e.art deleted 100644 → 0
View file @ 8b3d2120
G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: fmc_tlu_v1e_147.brd*
G04 Film Name: tlu_OUTLINE_v1e*
G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-2015-S079*
G04 Origin Date: Thu May 18 17:40:05 2017*
G04 *
G04 Layer: BOARD GEOMETRY/OUTLINE*
G04 *
G04 Offset: (0.0000 0.0000)*
G04 Mirror: No*
G04 Mode: Positive*
G04 Rotation: 0*
G04 FullContactRelief: No*
G04 UndefLineWidth: 0.0500*
G04 ================== end FILE IDENTIFICATION RECORD ====================*
%FSLAX35Y35*MOMM*%
%IR0*IPPOS*OFA0.00000B0.00000*MIA0B0*SFA1.00000B1.00000*%
%ADD10C,.05*%
G75*
%LPD*%
G75*
G54D10*
G01X23000000Y0D02*
X0D01*
Y11500000D01*
X23000000D01*
Y0D01*
M02*
Cadence/worklib/fmc_tlu_toplevel_f/physical/tlu_v1e_OUTLINE.art deleted 100644 → 0
View file @ 8b3d2120
G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: fmc_tlu_v1e_153.brd*
G04 Film Name: tlu_v1e_OUTLINE*
G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 17.2-P019*
G04 Origin Date: Mon Feb 05 13:34:47 2018*
G04 *
G04 Layer: BOARD GEOMETRY/OUTLINE*
G04 *
G04 Offset: (0.0000 0.0000)*
G04 Mirror: No*
G04 Mode: Positive*
G04 Rotation: 0*
G04 FullContactRelief: No*
G04 UndefLineWidth: 0.2000*
G04 ================== end FILE IDENTIFICATION RECORD ====================*
%FSLAX35Y35*MOMM*%
%IR0*IPPOS*OFA0.00000B0.00000*MIA0B0*SFA1.00000B1.00000*%
%ADD10C,.2*%
G75*
%LPD*%
G75*
G54D10*
G01X23000000Y0D02*
X0D01*
Y11500000D01*
X23000000D01*
Y0D01*
M02*
Cadence/worklib/fmc_tlu_toplevel_f/physical/tlu_v1e_OUTLINE_153.art deleted 100644 → 0
View file @ 8b3d2120
G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: fmc_tlu_v1e_153.brd*
G04 Film Name: tlu_v1e_OUTLINE_153*
G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 17.2-P019*
G04 Origin Date: Mon Feb 05 13:36:23 2018*
G04 *
G04 Layer: BOARD GEOMETRY/OUTLINE*
G04 *
G04 Offset: (0.0000 0.0000)*
G04 Mirror: No*
G04 Mode: Positive*
G04 Rotation: 0*
G04 FullContactRelief: No*
G04 UndefLineWidth: 0.2000*
G04 ================== end FILE IDENTIFICATION RECORD ====================*
%FSLAX35Y35*MOMM*%
%IR0*IPPOS*OFA0.00000B0.00000*MIA0B0*SFA1.00000B1.00000*%
%ADD10C,.2*%
G75*
%LPD*%
G75*
G54D10*
G01X23000000Y0D02*
X0D01*
Y11500000D01*
X23000000D01*
Y0D01*
M02*
Cadence/worklib/fmc_tlu_toplevel_f/sch_1/fmc_tlu_toplevel_f.xcon 100755 → 100644
View file @ 38ac36fa
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