AIDA-2020 TLU - Gateware:ca28778e02c9da94eef24cbc1da2cff74c484004 commitshttps://ohwr.org/project/fmc-mtlu-gw/commits/ca28778e02c9da94eef24cbc1da2cff74c4840042020-11-13T10:34:18Zhttps://ohwr.org/project/fmc-mtlu-gw/commit/ca28778e02c9da94eef24cbc1da2cff74c484004Changing read/write of trigger old off register from W to w . New versions of…2020-11-13T10:34:18ZDavid CussansDavid.Cussans@bristol.ac.ukChanging read/write of trigger old off register from W to w . New versions of uHAL choke on upper case
https://ohwr.org/project/fmc-mtlu-gw/commit/ec85c371625e2d71588ec57ce30e123fadf1259bRemoving TLU manual from Firm(Gate)ware repository. The definitive version is...2020-10-22T19:23:15ZDavid CussansDavid.Cussans@bristol.ac.ukRemoving TLU manual from Firm(Gate)ware repository. The definitive version is in the 'toplevel' repo: <a href="https://ohwr.org/project/fmc-mtlu">https://ohwr.org/project/fmc-mtlu</a>
https://ohwr.org/project/fmc-mtlu-gw/commit/1dc6a17a0266418a5104f09269f519b09aad3154Update README.md2020-10-20T14:27:03ZDavid Cussansdavid.cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/39934bb521b5d3b5432c0e0db84033515e2d9080Minor change in documentation2020-10-20T14:22:16ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/6080bf9e991c1dd505d2245b2b81863b9eaa12e0Merge branch 'dcussans/update_docs' into 'master'2020-10-20T13:54:36ZDavid Cussansdavid.cussans@bristol.ac.uk
Dcussans/update docs
See merge request <a href="/project/fmc-mtlu-gw/merge_requests/5" data-original="project/fmc-mtlu-gw!5" data-link="false" data-link-reference="false" data-project="10974" data-merge-request="61" data-reference-type="merge_request" data-container="body" data-placement="bottom" title="Dcussans/update docs" class="gfm gfm-merge_request has-tooltip">!5</a>https://ohwr.org/project/fmc-mtlu-gw/commit/3eb09f3a5dc0476a7b65a8b4d22c746e8a83dc9cUpdating register map documentation. Edge select register2020-10-20T13:50:38ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/a097f4ff9d000d670cf54afd75f90c2890517916Updating register map documentation2020-10-20T13:43:48ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/e1ada15de2d4ad10c85601a54ff52a8506bb85e1Merge branch 'dcussans/add-ipbus_decode_TLUaddrmap' into 'master'2020-10-20T12:50:11ZDavid Cussansdavid.cussans@bristol.ac.uk
Dcussans/add ipbus decode tl uaddrmap
See merge request <a href="/project/fmc-mtlu-gw/merge_requests/4" data-original="project/fmc-mtlu-gw!4" data-link="false" data-link-reference="false" data-project="10974" data-merge-request="60" data-reference-type="merge_request" data-container="body" data-placement="bottom" title="Dcussans/add ipbus decode tl uaddrmap" class="gfm gfm-merge_request has-tooltip">!4</a>https://ohwr.org/project/fmc-mtlu-gw/commit/9e5c878e6a415935e80e1b37ba3e680b3c1996adDon't automatically execute gendecoders stage2020-10-20T12:35:31ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/8541e84d29fc92203503d55ce8b523de1493e9b4Adding output of gendecoders2020-10-20T12:33:01ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/e9f5032bde4ada54e39dbce669833654bee4955eMerge branch 'dcussans/change_permissions' into HEAD2020-10-20T10:30:46ZDavid CussansDavid.Cussans@bristol.ac.uk
Large number of conflicts reports - but almost all of these seem to have been white-space only
README.md conflict probably not resolved correctly.
Tidying up some files. This seems to have resulted in conflict with master, but I don't know how.https://ohwr.org/project/fmc-mtlu-gw/commit/b198f8bdc111e6f4c937fd75f63476df9ac61964Deleting more SVN dirs2020-09-02T17:42:30ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/3712a10a8957ff16c88794aaf21b5e52d4e4794aRemoving the Subversion directories from subdirectories of PyChips2020-09-02T17:39:26ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/882efdbf625fb411ac9363626df37e3620d2dd45Removing Subversion files from branch2020-09-02T17:33:54ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/2e34ba6e42495b38f652580eb929146d09fd862fMerging changes back to master. Seems to be in a state where the permissions…2020-09-02T16:59:03ZDavid CussansDavid.Cussans@bristol.ac.ukMerging changes back to master. Seems to be in a state where the permissions were wrong. Creating a new branch to merge back to master
https://ohwr.org/project/fmc-mtlu-gw/commit/1ed997b7448eb5937778c348e97f634e5fa6ac01Merge branch 'dcussans/8bit_fine_ts' into 'master'2020-05-13T18:03:49ZDavid Cussansdavid.cussans@bristol.ac.uk
Dcussans/8bit fine ts
See merge request <a href="/project/fmc-mtlu-gw/merge_requests/2" data-original="project/fmc-mtlu-gw!2" data-link="false" data-link-reference="false" data-project="10974" data-merge-request="48" data-reference-type="merge_request" data-container="body" data-placement="bottom" title="Dcussans/8bit fine ts" class="gfm gfm-merge_request has-tooltip">!2</a>https://ohwr.org/project/fmc-mtlu-gw/commit/27f96930b4e61b92c8c1d9c8e945acf468288427Minor mod to README.md2020-05-13T17:54:41ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/f66918f54957abb1d21e1c4a04a10e25610d9ca3Bug fixes in simulation. Bug fixes in rising/falling edge swap2020-03-03T10:26:32ZDavid CussansDavid.Cussans@bristol.ac.uk
generate_bfm_input - text fed into HREAD must be long enough to fill variable ( e.g. HREAD into 32 bit integer needs 8 chars )
dualSERDES_1to_4 - changed delay on delayed IDELAYE2 in order to balance up delays
triggerInputs_newTLU - fixed bug in code to swap between rising and falling edges
TLUaddrmap.xml - added new register for optional invert edge selection.
transactionGenerator_behavioural.vhd - simulation should now finish cleanly, rather than hanging in loophttps://ohwr.org/project/fmc-mtlu-gw/commit/dd0b9f42925c9c6906745e7cab612736da34ef80Bug fixes to allow synthesis. Adding trigger number to test bench2020-03-02T18:40:11ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/92a25243ae54cda6f3e55a44d598fd9ed79396a4Bug fixes in simulation. Bug fix in fine-grain time-stamp2020-03-02T16:33:56ZDavid CussansDavid.Cussans@bristol.ac.uk
Inspection "by eye" shows linear correlation between delay of pulse and
fine-grain timestamp.https://ohwr.org/project/fmc-mtlu-gw/commit/a590a053d7ca3dcb57aab283811bcb5a148a2446Adding bottom 3 bits of 40MHz time stamp to fine-grain timestamp2020-03-02T12:34:00ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/a59dc76e168559dd9886825dd1062cd276543e58Created a testbench for the trigger input block2020-02-28T16:50:11ZDavid CussansDavid.Cussans@bristol.ac.uk
Use AIDA_tlu/components/tlu/sim/cfg/triggerInputs_newTLU_tb.dep to build with ipbbhttps://ohwr.org/project/fmc-mtlu-gw/commit/b61af01ce75ee6a90d26190b17ba3e11f8bafe77Changed triggerInput test bench to use logic_clocks entity.2020-02-25T18:45:20ZDavid CussansDavid.Cussans@bristol.ac.uk
This led to some minor changes to logic_clocks. Hopefully making it more robust...https://ohwr.org/project/fmc-mtlu-gw/commit/def3889490d5d034a258094a8189a95c6f319f2bFixing typo in process sensitivity list in logic_clocks. Hopefully won't have…2020-02-25T17:28:40ZDavid CussansDavid.Cussans@bristol.ac.ukFixing typo in process sensitivity list in logic_clocks. Hopefully won't have affected function ....
https://ohwr.org/project/fmc-mtlu-gw/commit/fd44b29a59d1ecd940378826fafca956dfdbeccbWriting test bench for trigger inputs2020-02-25T17:27:51ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/dfc56e119523041f7ed0fe44b6c4a0dda1a6517aRemoving commented out code2020-02-25T15:29:08ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/d5da54ef61c4a808e99479a109f591468b46e76fMinor fix to build_tlu_firmware.sh so that it builds cleanly2020-02-25T12:16:28ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/481f68b175a6078103f4285fa17caad3b8262181Merge branch 'dcussans/ipbus1v6_update' into 'master'2020-02-25T11:23:51ZDavid Cussansdavid.cussans@bristol.ac.uk
Dcussans/ipbus1v6 update
See merge request <a href="/project/fmc-mtlu-gw/merge_requests/1" data-original="project/fmc-mtlu-gw!1" data-link="false" data-link-reference="false" data-project="10974" data-merge-request="31" data-reference-type="merge_request" data-container="body" data-placement="bottom" title="Dcussans/ipbus1v6 update" class="gfm gfm-merge_request has-tooltip">!1</a>https://ohwr.org/project/fmc-mtlu-gw/commit/678b4c6704ace5fb9d9f726cf63029626bd62373Minor tweaks to build script. Some tidying up.2020-02-25T11:18:11ZDavid CussansDavid.Cussans@bristol.ac.uk
Removing unused files.https://ohwr.org/project/fmc-mtlu-gw/commit/98468998aa61ad7baf7f57dc86aadb960da207a7Don't need to set priority of *.xdc file now it is changed to tcl file2020-02-24T22:36:01ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/a74e93c1adfbbd12203fdea6ec9c067c5000573eMore tidying up of TLU firmware.2020-02-24T20:37:19ZDavid CussansDavid.Cussans@bristol.ac.ukShould now build against IPBus v1.6https://ohwr.org/project/fmc-mtlu-gw/commit/b1027c627778fb8c5027cf11ef5f717c76287cd8Updating TLU code to use IPBus v1.6 ( to avoid "code rot" )2020-02-24T17:36:53ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/9eab5368dea902688d55f8d62eac6f012eea375cUpdate README.md2019-07-04T10:59:05ZPaolo Baessopaolo.baesso@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/cc585db706bef2a6ee20c19b0d884448fe9ef1c3Update README.md2019-07-04T10:57:26ZPaolo Baessopaolo.baesso@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/48e040c66d30ad2b61879313ea7e21e85e2d37f1Incrementing version number in build script2019-04-26T11:52:03ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/7a467e0cc34aaf3a8fc2e3db0ff7c622fcfee1b4Merge branch 'master' of https://ohwr.org/project/fmc-mtlu-gw2019-04-26T11:27:21ZDavid CussansDavid.Cussans@bristol.ac.ukhttps://ohwr.org/project/fmc-mtlu-gw/commit/b319d0cc2b6f67d1afb407b93836768bb5a912f7* Adjusting timing between 40MHz clock and strobes in logic_clocks_rtl.vhd2019-04-26T11:24:57ZDavid CussansDavid.Cussans@bristol.ac.uk* Incrementing version number ( now v24 )https://ohwr.org/project/fmc-mtlu-gw/commit/5444ee7aea884aed1772653297d30e5b5d95ea10Tidied up logic_clocks_rtl.vhd:2019-04-26T09:39:08ZDavid CussansDavid.Cussans@bristol.ac.uk* Removed unused code and signals.
* Changed way strobes are generated - use 40MHz clock as input. (Should be much more robust than previous mechanism)
Incremented version number to 23https://ohwr.org/project/fmc-mtlu-gw/commit/fc4ec4028241c6563661438c37d0902a75a0e5e6Tidying up whilst sorting out simulation.2019-04-17T14:57:16ZDavid CussansDavid.Cussans@bristol.ac.uk
deleting pc051a_infra_sim.{dep,vhd} - these files were never needed
deleting enclustra_ax3_pm3_infra.patch - made a copy, so don't need to patch
deleting enclustra_ax3_pm3_infra.vhd - duplicate copyhttps://ohwr.org/project/fmc-mtlu-gw/commit/cad3311bc76a4a559e5e230d94f61411d0576f21Working on getting TLU simulation to work2019-04-17T14:53:17ZDavid CussansDavid.Cussans@bristol.ac.uk
triggerLogic_rtl.vhd - changed not to need VHDL-2008
tlu_1e.dep - changed to correct order to work with ipbb sim. Added VHDL-2008 flags
top_tim.dep - top level dep file to build simulation
infra_sim.vhd - infrastructure ( Ethernet Mac + IPBus control ) for simulation. IPBB not able to ignore synthesis only files