Dcussans/8bit fine ts

See merge request !2

generate_bfm_input - text fed into HREAD must be long enough to fill variable ( e.g. HREAD into 32 bit integer needs 8 chars )

dualSERDES_1to_4 - changed delay on delayed IDELAYE2 in order to balance up delays
triggerInputs_newTLU - fixed bug in code to swap between rising and falling edges

TLUaddrmap.xml - added new register for optional invert edge selection.

transactionGenerator_behavioural.vhd - simulation should now finish cleanly, rather than hanging in loop

Inspection "by eye" shows linear correlation between delay of pulse and
fine-grain timestamp.

Use AIDA_tlu/components/tlu/sim/cfg/triggerInputs_newTLU_tb.dep to build with ipbb

This led to some minor changes to logic_clocks. Hopefully making it more robust...

Fixing typo in process sensitivity list in logic_clocks. Hopefully won't have affected function ....

Dcussans/ipbus1v6 update

See merge request !1

Removing unused files.

Should now build against IPBus v1.6

* Incrementing version number ( now v24 )

* Removed unused code and signals.
* Changed way strobes are generated - use 40MHz clock as input. (Should be much more robust than previous mechanism)
Incremented version number to 23

deleting pc051a_infra_sim.{dep,vhd} - these files were never needed
deleting enclustra_ax3_pm3_infra.patch - made a copy, so don't need to patch
deleting enclustra_ax3_pm3_infra.vhd - duplicate copy

triggerLogic_rtl.vhd - changed not to need VHDL-2008
tlu_1e.dep - changed to correct order to work with ipbb sim. Added VHDL-2008 flags
top_tim.dep - top level dep file to build simulation
infra_sim.vhd - infrastructure ( Ethernet Mac + IPBus control ) for simulation. IPBB not able to ignore synthesis only files

enclustra_ax3_pm3_infra.vhd has been copied to fmc-mtlu-gw repo.

adding g_BUILD_SIMULATED_MAC generic to choose between physical and simulated Phy

* Modifying enclustra_ax3_pm3_infra.dep to pick up modified
enclustra_ax3_pm3_infra.vhd from  fmc-mtlu-gw repo rather than ipbus repo

* Removing unused ( and confusing ) top_enclustra_ax3_pm3.vhd

* Editing top_enclustra_tlu_v1e.vhd to pass downn g_BUILD_SIMULATED_MAC

to have same relationship with the clock as when in AIDA mode

Bumped version to 22

Pulling tag 19

( trigger output two clock cycles of 40MHz, trigger number on reset line being clocked out at 160MHz)

* Added reset circuitry to DUTInterface_AIDA_rtl.vhd

* Added one extra register of clk4x ( 160MHz ) to aid with timing closure ( although Vivado not reporting negative slack - so have probably got timing contraints wrong :-o )

Hacking around trying to fix problems with IPBus ( DUT interfaces not responding to IPBus , Shutter not responding to IPBus ).
Added rst_ipb signal to syncreg_v block in DUT interfaces and shutter. Added debug.

 Now operates "correctly". Will push to repo, remove debug and try again ( in case debug is accidentally squashing a timing issue ... )

* Stretch FIFO reset in eventBuffer_rtl.vhd

* Incremented version number ( to 16 ) in top_enclustra_tlu_v1e.vhd

* Added a few lines to TLU_enclustra_v1e_setProcessingOrder.tcl to force processing order of XDC file and set VHDL type to 2008 on one file...

* Edited build script to execute a Vivado TCL script in order to set TLU_enclustra_v1e.xdc as "late" processing.