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AIDA-2020 TLU - Gateware
Commit fba19b1c authored by David Cussans's avatar David Cussans
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Added more registers to get signals when in AIDA+trig-num mode 

to have same relationship with the clock as when in AIDA mode

Bumped version to 22
parent 0d7cb8ca
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AIDA_tlu/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
View file @ fba19b1c
...@@ -29,8 +29,8 @@ use work.ipbus_reg_types.all; ...@@ -29,8 +29,8 @@ use work.ipbus_reg_types.all;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
--! @details --! @details
--! \n IPBus Address map: --! \n IPBus Address map:
--! \li 0x0 Control (bit-0 : high = shutter pulses on) --! \li 0x0 Control (bit-0 : high = shutter pulses on , bit-1 : high = use internal cycle generator, else wait for external signal)
--! \li 0x1 Select source --! \li 0x1 Select source ( from the 6 trigger inputs.
--! \li 0x2 Internal trig generator period ( units = number of strobe pulses) --! \li 0x2 Internal trig generator period ( units = number of strobe pulses)
--! \li 0x3 Shutter on time - time between input trigger being received and shutter asserted(T1) --! \li 0x3 Shutter on time - time between input trigger being received and shutter asserted(T1)
--! \li 0x4 Veto off time - time between input trigger and veto being de-asserted(T2) --! \li 0x4 Veto off time - time between input trigger and veto being de-asserted(T2)
...@@ -90,8 +90,6 @@ ARCHITECTURE rtl OF T0_Shutter_Iface IS ...@@ -90,8 +90,6 @@ ARCHITECTURE rtl OF T0_Shutter_Iface IS
signal s_ipbus_controlregs: ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0); signal s_ipbus_controlregs: ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0);
constant c_ipbus_qmask : ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0) := (others => (others => '1')); constant c_ipbus_qmask : ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0) := (others => (others => '1'));
-- constant c_T0_address : std_logic_vector(3 downto 0) := "1000"; --! Write 1 to bit 0 of this address to produce a enable shutters and produce T0 pulse
begin begin
...@@ -133,11 +131,10 @@ begin ...@@ -133,11 +131,10 @@ begin
rstb => open rstb => open
); );
-- s_enable_sequence <= ( s_ipbus_controlregs(0)(0) and s_run_active ) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1')); s_enable_sequence <= ( s_ipbus_controlregs(0)(0) and s_run_active) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1')); --! Write 1 to bit 0 of control reg. 0 to enable shutter
s_enable_sequence <= ( s_ipbus_controlregs(0)(0) and s_run_active) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
-- s_run_active <= s_ipbus_controlregs(8)(0); --! Set to 1 to issue T0 and start shutter -- s_run_active <= s_ipbus_controlregs(8)(0); --! Set to 1 to issue T0 and start shutter
s_enable_internal_cycle <= s_ipbus_controlregs(0)(1); s_enable_internal_cycle <= s_ipbus_controlregs(0)(1); --! Write 1 to bit 1 of control reg 0 to enable internal shutter generator ( otherwise waits for signal on input )
s_trigger_source_select <= s_ipbus_controlregs(1); s_trigger_source_select <= s_ipbus_controlregs(1);
s_internal_cycle_length <= s_ipbus_controlregs(2); s_internal_cycle_length <= s_ipbus_controlregs(2);
...@@ -146,33 +143,16 @@ begin ...@@ -146,33 +143,16 @@ begin
s_threshold_t2 <= s_ipbus_controlregs(4); s_threshold_t2 <= s_ipbus_controlregs(4);
s_threshold_t3 <= s_ipbus_controlregs(5); s_threshold_t3 <= s_ipbus_controlregs(5);
s_run_active <= s_ipbus_controlregs(6)(0); s_run_active <= s_ipbus_controlregs(6)(0); --! Writing to bit-0 of control reg 6 sets run active
run_active_o <= s_run_active; run_active_o <= s_run_active;
---- A bodge. I can't figure out which standard IPBus register generates a
---- pulse, so put this logic in parallel.
----------------------
--ipbus_generateT0: process (ipbus_clk_i)
--begin -- process ipbus_clk_i
--if rising_edge(ipbus_clk_i) then
-- if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
-- s_T0_ipbus <= '1'; -- set T0 signal high
-- else
-- s_T0_ipbus <= '0';
-- end if;
-- end if;
--end process ipbus_generateT0;
--! Retime T0 generated by IPBus onto clk_4x and align with strobe --! Retime T0 generated by IPBus onto clk_4x and align with strobe
cmp_T0_retime: entity work.stretchPulse4x cmp_T0_retime: entity work.stretchPulse4x
port map ( port map (
clk_4x_i => clk_4x_i, clk_4x_i => clk_4x_i,
clk_4x_strobe_i => clk_4x_strobe_i, clk_4x_strobe_i => clk_4x_strobe_i,
pulse_i => s_run_active, pulse_i => s_run_active,
-- pulse_i => s_T0_ipbus,
pulse_o => T0_o); pulse_o => T0_o);
END rtl; END rtl;
AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_AIDA_rtl.vhd
View file @ fba19b1c
...@@ -76,6 +76,8 @@ ARCHITECTURE rtl OF DUTInterface_AIDA IS ...@@ -76,6 +76,8 @@ ARCHITECTURE rtl OF DUTInterface_AIDA IS
signal s_trigger_number_guard_sr : std_logic_vector( (g_NUM_TRIGNUM_BITS_TO_CLOCKOUT+g_NUM_TRIGNUM_GUARDBITS) -1 downto 0) := (others => '0'); --! Loaded with "ones" to indicate busy shifting trigger number signal s_trigger_number_guard_sr : std_logic_vector( (g_NUM_TRIGNUM_BITS_TO_CLOCKOUT+g_NUM_TRIGNUM_GUARDBITS) -1 downto 0) := (others => '0'); --! Loaded with "ones" to indicate busy shifting trigger number
signal s_busy_clocking_trigger_number : std_logic := '0'; --! High when shifting trigger number signal s_busy_clocking_trigger_number : std_logic := '0'; --! High when shifting trigger number
signal reset_or_clk_to_dut_d1, reset_or_clk_to_dut_d2, reset_or_clk_to_dut_d3 , reset_or_clk_to_dut_d4 : std_logic := '0';
BEGIN BEGIN
...@@ -164,6 +166,12 @@ BEGIN ...@@ -164,6 +166,12 @@ BEGIN
end if; end if;
end process p_dut_trig_retime; end process p_dut_trig_retime;
-- Delay input reset/T0 signal. ( Have put in one cycle of clk4x , so need to delay by 3 cycles )
--! DUT interface puts one cycle of clk4x extra latency. So, need to delay T0 by 3 cycles in order to move into sync with output clock
reset_or_clk_to_dut_d1 <= reset_or_clk_to_dut_i when rising_edge(clk_4x_logic_i);
reset_or_clk_to_dut_d2 <= reset_or_clk_to_dut_d1 when rising_edge(clk_4x_logic_i);
reset_or_clk_to_dut_d3 <= reset_or_clk_to_dut_d2 when rising_edge(clk_4x_logic_i);
reset_or_clk_to_dut_d4 <= reset_or_clk_to_dut_d3 when rising_edge(clk_4x_logic_i);
-- purpose: register for internal signals and output signals -- purpose: register for internal signals and output signals
-- type : combinational -- type : combinational
...@@ -185,7 +193,7 @@ BEGIN ...@@ -185,7 +193,7 @@ BEGIN
s_dut_reset_or_clk <= s_trigger_number_sr(0); -- Clock out trigger number LSB first. s_dut_reset_or_clk <= s_trigger_number_sr(0); -- Clock out trigger number LSB first.
else else
-- Copy reset/clk signal straight through -- Copy reset/clk signal straight through
s_dut_reset_or_clk <= reset_or_clk_to_dut_i; s_dut_reset_or_clk <= reset_or_clk_to_dut_d4;
end if; end if;
-- Add registers to help timing closture -- Add registers to help timing closture
......
AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl.vhd
View file @ fba19b1c
...@@ -94,6 +94,7 @@ ARCHITECTURE rtl OF DUTInterfaces IS ...@@ -94,6 +94,7 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_clk_to_DUT , s_busy_from_dut , s_dut_veto , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); signal s_clk_to_DUT , s_busy_from_dut , s_dut_veto , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
signal s_shutter_to_dut_d1 : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
signal s_clk_from_dut_eudet , s_busy_from_dut_eudet , s_dut_veto_eudet , s_reset_or_clk_to_dut_eudet , s_trigger_to_dut_eudet , s_shutter_to_dut_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); signal s_clk_from_dut_eudet , s_busy_from_dut_eudet , s_dut_veto_eudet , s_reset_or_clk_to_dut_eudet , s_trigger_to_dut_eudet , s_shutter_to_dut_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
signal s_clk_to_DUT_AIDA , s_busy_from_dut_aida , s_dut_veto_aida , s_reset_or_clk_to_dut_aida , s_trigger_to_dut_aida , s_shutter_to_dut_aida : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); signal s_clk_to_DUT_AIDA , s_busy_from_dut_aida , s_dut_veto_aida , s_reset_or_clk_to_dut_aida , s_trigger_to_dut_aida , s_shutter_to_dut_aida : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs used. 1 = active signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs used. 1 = active
...@@ -191,7 +192,7 @@ BEGIN ...@@ -191,7 +192,7 @@ BEGIN
reset_to_dut <= s_reset_or_clk_to_dut and s_DUT_mask; reset_to_dut <= s_reset_or_clk_to_dut and s_DUT_mask;
shutter_to_dut <= s_shutter_to_dut ; shutter_to_dut <= s_shutter_to_dut_d1 ;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Instantiate interfaces to DUTs -- Instantiate interfaces to DUTs
...@@ -274,6 +275,9 @@ BEGIN ...@@ -274,6 +275,9 @@ BEGIN
s_shutter_to_dut <= ( s_shutter_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_shutter_to_dut_aida and s_DUT_aida_eudet_mode) ; s_shutter_to_dut <= ( s_shutter_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_shutter_to_dut_aida and s_DUT_aida_eudet_mode) ;
s_reset_or_clk_to_dut <= ( s_reset_or_clk_to_dut_aida and s_DUT_aida_eudet_mode) ; --! reset_or_clk line stays low if in EUDET mode s_reset_or_clk_to_dut <= ( s_reset_or_clk_to_dut_aida and s_DUT_aida_eudet_mode) ; --! reset_or_clk line stays low if in EUDET mode
-- Delay shutter to ease timing
s_shutter_to_dut_d1 <= s_shutter_to_dut;
end if; end if;
end process p_signal_mux; end process p_signal_mux;
......
AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ fba19b1c
...@@ -51,7 +51,7 @@ use work.ipbus.ALL; ...@@ -51,7 +51,7 @@ use work.ipbus.ALL;
entity top is entity top is
generic( generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000020"; -- Firmware revision. Remember to change this as needed. constant FW_VERSION : unsigned(31 downto 0):= X"1e000022"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3 g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4 g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4 g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......
AIDA_tlu/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
View file @ fba19b1c
...@@ -25,3 +25,4 @@ set_property PACKAGE_PIN P18 [get_ports i2c_sda_b] ...@@ -25,3 +25,4 @@ set_property PACKAGE_PIN P18 [get_ports i2c_sda_b]
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
View file @ fba19b1c
...@@ -200,3 +200,4 @@ set_input_delay -clock [get_clocks clk_ipb_i] -max 17.000 [get_ports i2c_sda_b] ...@@ -200,3 +200,4 @@ set_input_delay -clock [get_clocks clk_ipb_i] -max 17.000 [get_ports i2c_sda_b]
# set_false_path -to [get_pins {infra/ipbus/udp_if/clock_crossing_if/we_buf_reg[0]/D}] # set_false_path -to [get_pins {infra/ipbus/udp_if/clock_crossing_if/we_buf_reg[0]/D}]
AIDA_tlu/scripts/build_tlu_firmware.sh
View file @ fba19b1c
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
# Put which branch of Git to use here... # Put which branch of Git to use here...
IPBUS_BRANCH="-b v1.3" IPBUS_BRANCH="-b v1.3"
TLU_BRANCH="-b 1e000020" TLU_BRANCH="-b 1e000022"
mkdir work mkdir work
cd work cd work
......
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