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AIDA-2020 TLU - Gateware
Commit f8306f74 authored by David Cussans's avatar David Cussans
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README 0 → 100755
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Firmware for AIDA miniTLU
-------------------------
Needs "IPBus" to communuicate via Ethernet to host.
To build firmware
Check out AIDA mTLU firmware from OHWR:
http://svn.ohwr.org/fmc-mtlu/trunk/firmware fmc-tlu-mtlu-firmware
Check out IPBus firmware from HEPForge:
svn co http://cactus.hepforge.org/svn/tags/IPbusFirmware_pre_131_RAL IPbusFirmware
Copy ise_project directory ( it will be where all the files produced by the ISE tools will end up ):
cp -r fmc-tlu-mtlu-firmware/ise_projects/fmc_tlu_top_sp601 .
move into the newly created directory:
cd fmc_tlu_top_sp601
Create some soft links to the IPBus and FMC-TLU directories:
ln -s ../IPbusFirmware_pre_131_RAL/firmware ipbus-firmware
ln -s ../fmc-tlu-mtlu-firmware .
Run setup script to create a directory to store output from CoreGen
./setup_ipcore_dir.sh
Run ise
The messages about missing IPCores need to be solved by:
Start the core generator GUI from the Tools menu. Double check that coregen has the correct part settings (doesn't always work), and select:
'Project' -> 'Regenerate all project IP'
And then wait a while.
Exit coregen GUI once done.
\ No newline at end of file
config/ise14/sp601/coregen.cgp 0 → 100644
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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx16
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET package = csg324
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
config/ise14/sp601/file_list 0 → 100644
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hdl ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
include ipbus/firmware/ethernet/cfg/file_list_s6_extphy
include ipbus/firmware/ipbus_core/cfg/file_list
config/ise14/sp601/setup_project.tcl 0 → 100644
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project new single_cbc2_fmc
project set family spartan6
project set device xc6slx16
project set package csg324
project set speed -3
project set "Enable Multi-Threading" "2" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
project set "Enable Multi-Threading" "2" -process "Place & Route"
project set "Enable BitStream Compression" TRUE -process "Generate Programming File"
# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl
# Just list files by hand for now. Can't get addfiles.tcl to work.
#xfile add ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
# IPBus Ethernet for gig_eth_pcs_pma_v11_5
xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
# Add cores for Ethernet
exec cp ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
exec cp ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
xfile add ipcore_dir/mac_fifo_axi4.xco
cd ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
cd ..
# Xilinx ISE setup fragment for ipbus core
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_registers.vhd
xfile add external/opencores_i2c/i2c_master_top.vhd
# Add CBC2 files
xfile add cbc2/firmware/hdl/i2c_master_rtl.vhd
xfile add cbc2/firmware/hdl/slaves.vhd
xfile add cbc2/firmware/hdl/clocks_s6_extphy.vhd
xfile add cbc2/firmware/hdl/ipbus_addr_decode.vhd
xfile add cbc2/firmware/hdl/top_sp605_extphy.vhd
xfile add cbc2/firmware/hdl/cbc2_interface.vhd
xfile add cbc2/firmware/hdl/i2c_trig.vhd
# Add user constraints file
xfile add cbc2/firmware/ucf/sp601_extphy_pc045b_1hybrid.ucf
project close
hdl_designer/fmc_mTLU/fmc_mTLU.hdp 0 → 100644
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[DesignChecker]
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck
[ModelSim]
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/work
[QuestaSim]
simprim = /software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/vhdl/questasim/10.0d/lin64/simprim
unisim = /software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/vhdl/questasim/10.0d/lin64/unisim
xilinxcorelib = /software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/vhdl/questasim/10.0d/lin64/xilinxcorelib
[XilinxISE]
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/ise
[hdl]
exemplar = $HDS_HOME/examples/exemplar/hdl
hds_package_library = $HDS_HOME/hdl_libs/hds_package_library/hdl
renoir_package_library = $HDS_HOME/hdl_libs/renoir_package_library/hdl
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/hdl
[hds]
exemplar = $HDS_HOME/examples/exemplar/hds
hds_package_library = $HDS_HOME/hdl_libs/hds_package_library/hds
renoir_package_library = $HDS_HOME/hdl_libs/renoir_package_library/hds
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/hds
[hds_settings]
default_library = work
design_root = work.top_extphy(struct)top_extphy/struct.bd
project_description = Firmware for AIDA Mini-TLU in FMC format
version = 2
[library_files_inclusion]
simprim = all
unisim = all
work = specify
xilinxcorelib = all
[library_type]
exemplar = regular
hds_package_library = regular
renoir_package_library = regular
simprim = downstream_only
unisim = downstream_only
work = regular
xilinxcorelib = downstream_only
[shared]
others = $HDS_TEAM_HOME/shared.hdp
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/DUTInterfaces_rtl.vhd 0 → 100644
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--=============================================================================
--! @file DUTInterfaces_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:09:50 11/09/12
--
--! @version v0.1
--
--! @details
--! Address map:\n
--! 5-bit decoded
--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
--! - mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--!
--
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
library unisim;
use unisim.VComponents.all;
ENTITY DUTInterfaces IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_IPBUS_WIDTH : positive := 32
);
PORT(
busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic;
clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
--shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
-- Declarations
END ENTITY DUTInterfaces ;
--
ARCHITECTURE rtl OF DUTInterfaces IS
signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0); -- OR tree
signal s_veto : std_logic;
signal s_strobe_4x_logic_d1 : std_logic;
signal s_busy_from_dut , s_clk_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut: std_logic_vector(g_NUM_DUTS-1 downto 0);
BEGIN
-----------------------------------------------------------------------------
-- IPBus. Dummy for now.
-----------------------------------------------------------------------------
ipbus_o.ipb_err <= '0';
ipbus_o.ipb_ack <= ipbus_i.ipb_strobe;
ipbus_o.ipb_rdata <= ( others => '1');
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
duts: for dut in 1 to g_NUM_DUTS generate
busy_IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => s_busy_from_dut(dut-1), -- Buffer output
I => busy_from_dut_p_i(dut-1), -- Diff_p buffer input (connect directly to top-level port)
IB => busy_from_dut_n_i(dut-1) -- Diff_n buffer input (connect directly to top-level port)
);
-- busy_IBUFDS_inst : IBUF
-- generic map (
-- IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-- IOSTANDARD => "DEFAULT")
-- port map (
-- O => s_busy_from_dut(dut-1), -- Buffer output
-- I => busy_from_dut_p_i(dut-1) -- Buffer input (connect directly to top-level port)
-- );
trig_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => trigger_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => trigger_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_trigger_to_dut(dut-1) -- Buffer input
);
-- trig_OBUFDS_inst : OBUF
-- generic map (
-- DRIVE => 12,
-- IOSTANDARD => "DEFAULT",
-- SLEW => "SLOW")
-- port map (
-- O => trigger_to_dut_p_o(dut-1), -- Buffer output (connect directly to top-level port)
-- I => s_trigger_to_dut(dut-1) -- Buffer input
-- );
-- shut_OBUFDS_inst : OBUF
-- generic map (
-- DRIVE => 12,
-- IOSTANDARD => "DEFAULT",
-- SLEW => "SLOW")
-- port map (
-- O => shutter_to_dut_p_o(dut-1), -- Buffer output (connect directly to top-level port)
-- I => s_shutter_to_dut(dut-1) -- Buffer input
-- );
clk_rst_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => reset_or_clk_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => reset_or_clk_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_reset_or_clk_to_dut(dut-1) -- Buffer input
);
-- clk_rst_OBUFDS_inst : OBUF
-- generic map (
-- DRIVE => 12,
-- IOSTANDARD => "DEFAULT",
-- SLEW => "SLOW")
-- port map (
-- O => reset_or_clk_to_dut_p_o(dut-1), -- Buffer output (connect directly to top-level port)
-- I => s_reset_or_clk_to_dut(dut-1) -- Buffer input
-- );
s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
s_busy_from_dut(dut-1);
end generate duts;
s_veto <= s_intermediate_busy_or(g_NUM_DUTS);
-- purpose: register for internal signals and output signals
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
-- outputs: veto_o
register_signals: process (clk_4x_logic_i , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
veto_o <= s_veto;
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
s_trigger_to_dut <= ( others => trigger_i );
--shutter_to_dut <= ( others => shutter_i );
end if;
end process register_signals;
END ARCHITECTURE rtl;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/GPP_ipb_rtl.vhd 0 → 100644
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hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/GPP_rtl.vhd 0 → 100644
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hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/IPBusInterface_rtl.vhd 0 → 100644
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--=============================================================================
--! @file IPBusInterface_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.IPBusInterface.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 16:06:57 11/09/12
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.emac_hostbus_decl.all;
ENTITY IPBusInterface IS
GENERIC(
NUM_EXT_SLAVES : positive := 5
);
PORT(
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals
sysclk_n_i : IN std_logic;
sysclk_p_i : IN std_logic; -- ! 200 MHz xtal clock
clocks_locked_o : OUT std_logic;
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
ipb_clk_o : OUT std_logic; -- ! IPBus clock to slaves
ipb_rst_o : OUT std_logic; -- ! IPBus reset to slaves
ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals
onehz_o : OUT std_logic;
phy_rstb_o : OUT std_logic;
dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
clk_logic_xtal_o : OUT std_logic
);
-- Declarations
END ENTITY IPBusInterface ;
--
ARCHITECTURE rtl OF IPBusInterface IS
--! Number of slaves inside the IPBusInterface block.
constant c_NUM_INTERNAL_SLAVES : positive := 2;
signal clk125, locked, rst_125, rst_ipb: STD_LOGIC;
signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
signal ipb_master_out : ipb_wbus;
signal ipb_master_in : ipb_rbus;
signal mac_addr: std_logic_vector(47 downto 0);
signal ip_addr: std_logic_vector(31 downto 0);
signal s_ipb_clk : std_logic;
signal hostbus_in: emac_hostbus_in;
signal hostbus_out: emac_hostbus_out;
signal s_ipbw_internal: ipb_wbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_ipbr_internal: ipb_rbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_sysclk : std_logic;
BEGIN
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_s6_extphy port map(
sysclk_p => sysclk_p_i,
sysclk_n => sysclk_n_i,
clk_logic_xtal_o => clk_logic_xtal_o,
clko_125 => clk125,
clko_ipb => s_ipb_clk,
locked => clocks_locked_o,
rsto_125 => rst_125,
rsto_ipb => rst_ipb,
onehz => onehz_o
);
-- Connect IPBus clock and reset to output ports.
ipb_clk_o <= s_ipb_clk;
ipb_rst_o <= rst_ipb;
-- leds <= ('0', '0', locked, onehz);
-- Ethernet MAC core and PHY interface
-- In this version, consists of hard MAC core and GMII interface to external PHY
-- Can be replaced by any other MAC / PHY combination
eth: entity work.eth_s6_gmii port map(
clk125 => clk125,
rst => rst_125,
gmii_gtx_clk => gmii_gtx_clk_o,
gmii_tx_en => gmii_tx_en_o,
gmii_tx_er => gmii_tx_er_o,
gmii_txd => gmii_txd_o,
gmii_rx_clk => gmii_rx_clk_i,
gmii_rx_dv => gmii_rx_dv_i,
gmii_rx_er => gmii_rx_er_i,
gmii_rxd => gmii_rxd_i,
txd => mac_txd,
txdvld => mac_txdvld,
txack => mac_txack,
rxd => mac_rxd,
rxclko => mac_rxclko,
rxdvld => mac_rxdvld,
rxgoodframe => mac_rxgoodframe,
rxbadframe => mac_rxbadframe,
hostbus_in => hostbus_in,
hostbus_out => hostbus_out
);
phy_rstb_o <= '1';
-- ipbus control logic
ipbus: entity work.ipbus_ctrl_udponly port map(
ipb_clk => s_ipb_clk,
rst_ipb => rst_ipb,
rst_macclk => rst_125,
mac_txclk => clk125,
mac_rxclk => mac_rxclko,
mac_rxd => mac_rxd,
mac_rxdvld => mac_rxdvld,
mac_rxgoodframe => mac_rxgoodframe,
mac_rxbadframe => mac_rxbadframe,
mac_txd => mac_txd,
mac_txdvld => mac_txdvld,
mac_txack => mac_txack,
ipb_out => ipb_master_out,
ipb_in => ipb_master_in,
mac_addr => mac_addr,
ip_addr => ip_addr
);
mac_addr <= X"020ddba115" & dip_switch_i & X"0"; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c8" & dip_switch_i & X"0"; -- 192.168.200.X
fabric: entity work.ipbus_fabric
generic map(NSLV => NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES)
port map(
ipb_clk => s_ipb_clk,
rst => rst_ipb,
ipb_in => ipb_master_out,
ipb_out => ipb_master_in,
ipb_to_slaves => s_ipbw_internal,
ipb_from_slaves => s_ipbr_internal
);
ipbw_o <= s_ipbw_internal(NUM_EXT_SLAVES-1 downto 0);
s_ipbr_internal(NUM_EXT_SLAVES-1 downto 0) <= ipbr_i;
-- Slave: firmware ID
firmware_id: entity work.ipbus_ver
port map(
ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-2),
ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-2)
);
-- Hostbus slave. Need to connect or IPBus_pre131_ral won't work...
-- No point in passing host bus out in/out of block.
hostbus_interface: entity work.ipbus_emac_hostbus
port map(
clk => s_ipb_clk,
reset => rst_ipb,
ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
hostbus_out => hostbus_in,
hostbus_in => hostbus_out);
END ARCHITECTURE rtl;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/Reg_2clks.vhd 0 → 100644
View file @ f8306f74
----------------------------------------------------------------------------------
-- Company: Universidade de Santiago de Compostela
-- Engineer: Alvaro Dosil
--
-- Create Date: 31/07/2012
-- Module Name: Reg_2clks - Behavioral
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
-------------------------------------------------------
--! @file
--! @brief Synchronization module 1b
--! @author Alvaro Dosil
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Reg_2clks is
port(
clk_i : in std_logic; --! Synchronous clock
async_i : in std_logic; --! Asynchronous input data
sync_o : out std_logic --! Synchronous output data
);
end Reg_2clks;
--! @brief
--! @details Synchronize 1 bit of data
architecture Behavioral of Reg_2clks is
signal sreg : std_logic_vector(1 downto 0);
attribute TIG : string;
attribute IOB : string;
attribute ASYNC_REG : string;
attribute SHIFT_EXTRACT : string;
attribute HBLKNM : string;
attribute TIG of async_i : signal is "TRUE";
attribute IOB of async_i : signal is "FALSE";
attribute ASYNC_REG of sreg : signal is "TRUE";
attribute SHIFT_EXTRACT of sreg : signal is "NO";
attribute HBLKNM of sreg : signal is "sync_reg";
begin
process (clk_i)
begin
if rising_edge(clk_i) then
sync_o <= sreg(1);
sreg <= sreg(0) & async_i;
end if;
end process;
end Behavioral;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arp.v.rlnk 0 → 100644
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/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/arp.v
\ No newline at end of file
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hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/bus_arb.vhd.rlnk 0 → 100644
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/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/bus_arb.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/clocks_s6_extphy.vhd 0 → 100644
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-- clocks_s6_extphy
--
-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
-- Includes reset logic for ipbus
--
-- Dave Newbold, April 2011
--
-- $Id$
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.VComponents.all;
entity clocks_s6_extphy is port(
sysclk_p, sysclk_n: in std_logic;
-- dummy_sysclk : in std_logic;
clk_logic_xtal_o : out std_logic;
clko_125: out std_logic;
clko_ipb: out std_logic;
locked: out std_logic;
rsto_125: out std_logic;
rsto_ipb: out std_logic;
onehz: out std_logic
);
end clocks_s6_extphy;
architecture rtl of clocks_s6_extphy is
signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk , sysclk_in: std_logic;
signal d25, d25_d, dcm_locked: std_logic;
signal rst: std_logic := '1';
signal s_xtal_dcm_locked: std_logic;
signal s_clk_logic_xtal : std_logic;
-- signal clk_400: std_logic;
component clock_divider_s6 port(
clk: in std_logic;
d25: out std_logic;
d28: out std_logic
);
end component;
begin
ibufgds0: IBUFGDS port map(
i => sysclk_p,
ib => sysclk_n,
o => sysclk
);
-- -- Add global clock buffer in sysclk path.
-- bufg_sysclk : BUFG port map (
-- i => sysclk_in,
-- o => sysclk);
bufg_125: BUFG port map(
i => clk_125_i,
o => clk_125_b
);
clko_125 <= clk_125_b;
bufg_ipb: BUFG port map(
i => clk_ipb_i,
o => clk_ipb_b
);
bufg_clk_logic_xtal: BUFG port map(
i => s_clk_logic_xtal,
o => clk_logic_xtal_o
);
clko_ipb <= clk_ipb_b;
dcm0: DCM_CLKGEN
generic map(
CLKIN_PERIOD => 5.0,
CLKFX_MULTIPLY => 5,
CLKFX_DIVIDE => 8,
CLKFXDV_DIVIDE => 4
)
port map(
clkin => sysclk,
clkfx => clk_125_i,
clkfxdv => clk_ipb_i,
locked => dcm_locked,
rst => '0'
);
clkdiv: clock_divider_s6 port map(
clk => sysclk,
d25 => d25,
d28 => onehz
);
process(sysclk)
begin
if rising_edge(sysclk) then
d25_d <= d25;
if d25='1' and d25_d='0' then
rst <= not dcm_locked;
end if;
end if;
end process;
locked <= dcm_locked;
process(clk_ipb_b)
begin
if rising_edge(clk_ipb_b) then
rsto_ipb <= rst;
end if;
end process;
process(clk_125_b)
begin
if rising_edge(clk_125_b) then
rsto_125 <= rst;
end if;
end process;
sys40_gen : BUFIO2
generic map (
DIVIDE => 5, -- DIVCLK divider (1-8)
DIVIDE_BYPASS => FALSE) -- Bypass the divider circuitry (TRUE/FALSE)
port map (
I => SysClk, -- 1-bit input: Clock input (connect to IBUFG)
DIVCLK => s_clk_logic_xtal, -- 1-bit output: Divided clock output
IOCLK => open, -- 1-bit output: I/O output clock
SERDESSTROBE => open); -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
-- Generate 40MHz clock from 200MHz crystal
-- dcmXTAL: DCM_CLKGEN
-- generic map(
-- CLKIN_PERIOD => 5.0,
-- CLKFX_MULTIPLY => 2,
-- CLKFX_DIVIDE => 10,
-- CLKFXDV_DIVIDE => 2
-- )
-- port map(
-- clkin => sysclk,
-- clkfx => s_clk_logic_xtal,
-- clkfxdv => open,
-- locked => s_xtal_dcm_locked,
-- rst => '0'
-- );
--
end rtl;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/dpram_8x12_32x10_dpram_8x12_32x10_a.vhd 0 → 100644
View file @ f8306f74
-- Coregen VHDL wrapper file modified by HDL Designer
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file dpram_8x12_32x10.vhd when simulating
-- the core, dpram_8x12_32x10. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY dpram_8x12_32x10 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END dpram_8x12_32x10;
ARCHITECTURE dpram_8x12_32x10_a OF dpram_8x12_32x10 IS
-- hds translate_off
-- synthesis translate_off
COMPONENT wrapped_dpram_8x12_32x10
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_dpram_8x12_32x10 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 1,
c_disable_warn_bhv_range => 1,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 1024,
c_read_width_a => 8,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "NONE",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 1024,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 32,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
-- hds translate_on
BEGIN
-- hds translate_off
-- synthesis translate_off
U0 : wrapped_dpram_8x12_32x10
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
-- hds translate_on
END dpram_8x12_32x10_a;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/dualSERDES_1to4_rtl.vhd 0 → 100644
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hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/emac_hostbus_decl.vhd.rlnk 0 → 100644
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/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/emac_hostbus_decl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eth_s6_1000basex.vhd.rlnk 0 → 100644
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/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/eth_s6_1000basex.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eth_s6_gmii.vhd.rlnk 0 → 100644
View file @ f8306f74
/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/eth_s6_gmii.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventBuffer_rtl.vhd 0 → 100644
View file @ f8306f74
--=============================================================================
--! @file eventBuffer_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.eventBuffer.rtl
--
--! @brief Stores input words (64bits) for readout over IPBus. \n
--! Uses a FIFO ( 64bits at input, 32 bits at output )\n
--! Address map:\n
--! 0x0000 - FIFO data\n
--! 0x0001 - FIFO fill level\n
--! 0x0010 - FIFO status/control:\n
--! Writing Bit-0 resets pointers.\n
--! Reading bit-1 returns "prog_full" flag
--
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:24:50 11/13/12
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
ENTITY eventBuffer IS
GENERIC(
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_WRITE_COUNTER_WIDTH : positive := 13;
g_READ_COUNTER_WIDTH : positive := 14
);
PORT(
clk_4x_logic_i : IN std_logic;
data_strobe_i : IN std_logic; -- Indicates data to transfer
event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic;
trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not yet used.
buffer_full_o : OUT std_logic; --! Goes high when event buffer almost full
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
);
-- Declarations
END ENTITY eventBuffer ;
--
ARCHITECTURE rtl OF eventBuffer IS
-- write addr count width = 13 , read addr count = 14.
--! Counters for input and ouput to/from FIFO
signal s_wr_data_count , s_wr_data_count_reg : std_logic_vector(g_WRITE_COUNTER_WIDTH-1 downto 0) := (others =>'0');
signal s_rd_data_count : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
signal s_fifo_fill_level : unsigned(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_write_strobe : std_logic := '0';
signal s_rst_fifo : std_logic := '0'; -- ! Take high to reset FIFO pointers.
signal s_fifo_prog_full : std_logic := '0'; -- ! Controlled by programmable-full flag of FIFO core
signal s_fifo_rd_en : std_logic := '0'; -- ! Take high to clock data out of FIFO
signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- ! Output from FIFO ( fall-through mode)
signal s_fifo_valid : std_logic := '1'; -- ! High when data in FIFO
signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
BEGIN
-----------------------------------------------------------------------------
-- IPBus IO
-----------------------------------------------------------------------------
--! Generate FIFO read enable
s_fifo_rd_en <= '1' when ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '0' and ipbus_i.ipb_addr(1 downto 0) = "00" else '0';
--! Generate IPBus ACK
ipbus_o.ipb_ack <= (ipbus_i.ipb_strobe and not s_fifo_rd_en) or (s_fifo_valid and s_fifo_rd_en);
ipbus_o.ipb_err <= '0';
--! Multiplex output data.
with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
s_fifo_dout when "00",
X"0000" & "00" & std_logic_vector(s_fifo_fill_level) when "01",
X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty when "11",
(others => '1') when others;
ipbus_write: process (ipbus_clk_i)
begin -- process ipbus_write
if rising_edge(ipbus_clk_i) then
if ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_addr(1 downto 0) = "10" and ipbus_i.ipb_write = '1' then
s_rst_fifo <= '1';
else
s_rst_fifo <= '0';
end if;
end if;
end process ipbus_write;
-----------------------------------------------------------------------------
-- FIFO and fill-level calculation
-----------------------------------------------------------------------------
-- Instantiate a buffer to store the data. 64-bit on input, 32-bit on output.
event_fifo : entity work.tlu_event_fifo
PORT MAP (
rst => s_rst_fifo,
wr_clk => clk_4x_logic_i,
rd_clk => ipbus_clk_i,
din => event_data_i,
wr_en => data_strobe_i,
rd_en => s_fifo_rd_en,
dout => s_fifo_dout,
full => s_fifo_full,
almost_full => s_fifo_almost_full,
empty => s_fifo_empty,
almost_empty => s_fifo_almost_empty,
rd_data_count => s_rd_data_count,
wr_data_count => s_wr_data_count,
prog_full => s_fifo_prog_full
);
buffer_full_o <= s_fifo_prog_full;
-- Transfer write-data-count to read clock domain
register_counter_inst : entity work.registerCounter
generic map (
g_DATA_WIDTH => g_WRITE_COUNTER_WIDTH)
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_wr_data_count,
data_o => s_wr_data_count_reg,
clk_output_i => ipbus_clk_i
);
----! Calculate the number of words in the FIFO .
---- (only valid if no buffer overflow.)
---- Each input word (64 bits) is the same as two output words (32 bits) so
---- multiply s_wr_data_count by 2 before subraction
--! wr_data_count and rd_data_count provide exactly the same information but in different clock domains
---- s_fifo_fill_level <= (unsigned(std_logic_vector(s_wr_data_count_reg) & "0") - unsigned(s_rd_data_count));
s_fifo_fill_level <= unsigned(s_rd_data_count);
END ARCHITECTURE rtl;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventFormatter_rtl.vhd 0 → 100644
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hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd 0 → 100644
View file @ f8306f74
--=============================================================================
--! @file fmcTLU_pkg.vhd
--=============================================================================
---
--! @brief VHDL Package Header fmc_mTLU_lib.fmcTLU
--
--! @author phdgc
--! @date 16:44:31 11/08/12
--
-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE fmcTLU IS
constant c_NUM_TIME_BITS : natural := 5;
constant c_NUM_TRIG_INPUTS : natural := 4;
constant c_EVENT_DATA_WIDTH : natural := 32;
--subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
--type t_triggerTimeArray is array(natural range <>) of t_triggerTime;
type t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
END fmcTLU;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd 0 → 100644
View file @ f8306f74
--=============================================================================
--! @file fmcTLU_pkg_body.vhd
--=============================================================================
---
--! @brief VHDL Package Body fmc_mTLU_lib.fmcTLU
--
--! @author phdgc
--! @date 16:45:08 11/08/12
--
-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
PACKAGE BODY fmcTLU IS
END fmcTLU;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/gbe_rxpacketbuffer.v.rlnk 0 → 100644
View file @ f8306f74
/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/gbe_rxpacketbuffer.v
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--=============================================================================
--! @file i2c_master_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture work.i2c_master.rtl
--
--! @brief Wraps the Wishbone I2C master in a wrapper where the IPBus signals\n
--! are bundled together in a record\n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 17:22:12 11/30/12
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
ENTITY i2c_master IS
PORT(
i2c_scl_i : IN std_logic;
i2c_sda_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
i2c_scl_enb_o : OUT std_logic;
i2c_sda_enb_o : OUT std_logic;
ipbus_o : OUT ipb_rbus -- signals from slave to IPBus core
);
-- Declarations
END ENTITY i2c_master ;
--
ARCHITECTURE rtl OF i2c_master IS
--signal s_i2c_scl, s_i2c_scl_o, s_i2c_scl_enb, s_i2c_sda, s_i2c_sda_enb : std_logic ;
BEGIN
--i2c_scl_b <= s_i2c_scl when (s_i2c_scl_enb = '0') else 'Z';
--i2c_sda_b <= s_i2c_sda when (s_i2c_sda_enb = '0') else 'Z';
i2c_interface: entity work.i2c_master_top port map(
wb_clk_i => ipbus_clk_i,
wb_rst_i => ipbus_reset_i,
arst_i => '1',
wb_adr_i => ipbus_i.ipb_addr(2 downto 0),
wb_dat_i => ipbus_i.ipb_wdata(7 downto 0),
wb_dat_o => ipbus_o.ipb_rdata(7 downto 0),
wb_we_i => ipbus_i.ipb_write,
wb_stb_i => ipbus_i.ipb_strobe,
wb_cyc_i => '1',
wb_ack_o => ipbus_o.ipb_ack,
wb_inta_o => open,
scl_pad_i => i2c_scl_i,
scl_pad_o => open,
scl_padoen_o => i2c_scl_enb_o,
sda_pad_i => i2c_sda_i,
sda_pad_o => open,
sda_padoen_o => i2c_sda_enb_o
);
ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
END ARCHITECTURE rtl;
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-- Address decode logic for ipbus fabric
--
-- This file has been AUTOGENERATED from the address table - do not hand edit
--
-- We assume the synthesis tool is clever enough to recognise exclusive conditions
-- in the if statement.
--
-- Dave Newbold, February 2011
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.ipbus.all;
package ipbus_addr_decode is
function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
end ipbus_addr_decode;
package body ipbus_addr_decode is
function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
variable sel : integer;
begin
if std_match(addr, "-----------------------0001-----") then
sel := 0; -- DUTInterfaces / base 00000020 / mask 0000001f
elsif std_match(addr, "-----------------------0010-----") then
sel := 1; -- triggerInputs / base 00000040 / mask 0000001f
elsif std_match(addr, "-----------------------0011-----") then
sel := 2; -- triggerLogic / base 00000060 / mask 0000001f
elsif std_match(addr, "-----------------------0100-----") then
sel := 3; -- eventBuffer / base 00000080 / mask 0000001f
elsif std_match(addr, "-----------------------0101-----") then
sel := 4; -- logic_clocks / base 000000a0 / mask 0000001f
elsif std_match(addr, "-----------------------0110-----") then
sel := 5; -- i2c_master / base 000000c0 / mask 00000007
elsif std_match(addr, "-----------------------0111-----") then
sel := 6; -- Trigger_Generator / base 000000e0 / mask 0000001f
elsif std_match(addr, "-----------------------1000-----") then
sel := 7; -- Shutter_Generator / base 00000100 / mask 0000001f
elsif std_match(addr, "-----------------------1001-----") then
sel := 8; -- Spill_Generator / base 00000120 / mask 0000001f
elsif std_match(addr, "-----------------------1010-----") then
sel := 9; -- Event_Formatter / base 00000140 / mask 0000001f
elsif std_match(addr, "-----------------------0000---0-") then
sel := 10; -- version / base 00000000 / mask 00000000
elsif std_match(addr, "-----------------------0000---1-") then
sel := 11; -- emac_hostbus / base 00000002 / mask 00000001
else
sel := 99;
end if;
return sel;
end ipbus_addr_sel;
end ipbus_addr_decode;
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-- Generic ipbus slave config register for testing
--
-- generic addr_width defines number of significant address bits
--
-- We use one cycle of read / write latency to ease timing (probably not necessary)
-- The q outputs change immediately on write (no latency).
--
-- Dave Newbold, March 2011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.ipbus.all;
use work.emac_hostbus_decl.all;
entity ipbus_emac_hostbus is
port(
clk: in std_logic;
reset: in std_logic;
ipbus_in: in ipb_wbus;
ipbus_out: out ipb_rbus;
hostbus_out: out emac_hostbus_in;
hostbus_in: in emac_hostbus_out
);
end ipbus_emac_hostbus;
architecture rtl of ipbus_emac_hostbus is
signal emac1sel, mdiocyc, acyc, dcyc, dcyc_d: std_logic;
signal addr: std_logic_vector(9 downto 0);
begin
ipbus_out.ipb_rdata <= hostbus_in.hostrddata when ipbus_in.ipb_addr(0) = '0'
else X"0000" & "000" & emac1sel & mdiocyc & '0' & addr;
acyc <= ipbus_in.ipb_strobe and ipbus_in.ipb_addr(0);
dcyc <= ipbus_in.ipb_strobe and not ipbus_in.ipb_addr(0);
process(clk)
begin
if rising_edge(clk) then
if acyc = '1' and ipbus_in.ipb_write = '1' then
emac1sel <= ipbus_in.ipb_wdata(12);
mdiocyc <= ipbus_in.ipb_wdata(11);
addr <= ipbus_in.ipb_wdata(9 downto 0);
end if;
dcyc_d <= dcyc;
end if;
end process;
hostbus_out.hostwrdata <= ipbus_in.ipb_wdata;
hostbus_out.hostaddr <= addr;
hostbus_out.hostemac1sel <= emac1sel;
hostbus_out.hostclk <= clk;
hostbus_out.hostmiimsel <= not (dcyc or (dcyc_d and ipbus_in.ipb_write)) or mdiocyc;
hostbus_out.hostopcode(1) <= not ipbus_in.ipb_write;
hostbus_out.hostopcode(0) <= ipbus_in.ipb_write;
hostbus_out.hostreq <= dcyc and mdiocyc and hostbus_in.hostmiimrdy;
ipbus_out.ipb_ack <= acyc or (dcyc and dcyc_d and (hostbus_in.hostmiimrdy or not mdiocyc));
ipbus_out.ipb_err <= '0';
end rtl;
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-- Version register, returns a fixed value
--
-- To be replaced by a more coherent versioning mechanism later
--
-- Dave Newbold, August 2011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity ipbus_ver is
port(
ipbus_in: in ipb_wbus;
ipbus_out: out ipb_rbus
);
end ipbus_ver;
architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a5e3" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
end rtl;
-- Build log
--
-- build 0x1000 : 22/08/11 : Starting build ID
-- build 0x1001 : 29/08/11 : Version for SPI testing
-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
-- build 0x1003 : buggy
-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
-- build 0x1006 : 26/10/11 : trying with jumbo frames
-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
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--=============================================================================
--! @file pulseClockDomainCrossing_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture worklib.pulseClockDomainCrossing.rtl
--
--! @brief Takes a pulse synchronized with one clock and produces a
--! pulse synchronized to another clock.
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date September/2012
--
--! @version v0.1
--
--! @details A "ring" of D-type flip-flops is used to transfer a strobe
--! from the input clock domain to the output clock domain and then back again.
--! The time taken to transit from input to output is approximately
--! two clock cycles of clock_output_i .
--! After an additional two cycles of clk_input_i another pulse can be sent
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pulseClockDomainCrossing is
port (
clk_input_i : in std_logic; --! clock for input
pulse_i : in std_logic; --! input pulse. Active high
clk_output_i: in std_logic; --! clock for output
pulse_o : out std_logic --! Single cycle pulse synchronized to clock_output_i
);
end pulseClockDomainCrossing;
architecture rtl of pulseClockDomainCrossing is
signal s_pulse_out , s_pulse_out_d1 , s_pulse_out_d2 , s_pulse_out_d3 , s_pulse_out_d4 , s_pulse_back_d1 , s_pulse_back_d2: std_logic := '0';
begin -- rtl
-- purpose: registers and flip-flop on clk_input_i
p_input_clock_logic: process (clk_input_i)
begin
if rising_edge(clk_input_i) then
-- Register signals coming from output clock domain back to the
-- input clock domain
s_pulse_back_d1 <= s_pulse_out_d2;
s_pulse_back_d2 <= s_pulse_back_d1;
-- JK flip-flop
if (s_pulse_back_d2 = '1') then
s_pulse_out <= '0';
elsif (pulse_i = '1') then
s_pulse_out <= '1';
end if;
end if;
end process p_input_clock_logic;
-- purpose: registers and flip-flop on clk_output_o
p_output_clock_logic: process (clk_output_i)
begin
if rising_edge(clk_output_i) then
-- Register signal on input clock domain onto output clock domain
s_pulse_out_d1 <= s_pulse_out;
s_pulse_out_d2 <= s_pulse_out_d1;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_d4 <= s_pulse_out_d3;
-- Generate single clock-cycle pulse on pulse_o
pulse_o <= s_pulse_out_d3 and ( not s_pulse_out_d4 );
end if;
end process p_output_clock_logic;
end rtl;
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--=============================================================================
--! @file registerCounter_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture worklib.registerCounter.rtl
--
--! @brief Regularly transfers the input to the output.\n
--! One clock for input , one clock for output\n
--! Can't just put entire bus through a couple of register stages,\n
--! Since this will just swap meta-stability issues for race issues.
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 24/Nov/12
--
--! @version v0.1
--
--! @details A six stage "ring oscillator" is used to generate two strobes.
--! One reads data into a register. The other registers the data to the output
--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
--! We could use gray-scale and put through registers, but this method
--! should work well enough at the expense of latency.\n
--! \n
--! The time taken for an edge to travel round the complete loop is
--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
--! that depend on the relative phase of clk_read_i and clk_write_i
--!
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity registerCounter is
generic (
g_DATA_WIDTH : positive := 15); -- ! Width of counter
port (
clk_input_i : in std_logic; -- ! clock for input
data_i : in std_logic_vector(g_DATA_WIDTH-1 downto 0); -- ! data to transfer to output
data_o : out std_logic_vector(g_DATA_WIDTH-1 downto 0); -- ! Data now in clk_read_i domain
clk_output_i : in std_logic); -- ! clock for output
end registerCounter;
architecture rtl of registerCounter is
signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0'; -- stages in "ring oscillator" used to generate strobes
signal s_registered_data : std_logic_vector(data_i'range) := ( others => '0'); -- ! Register to store data between clock domains
signal s_read_strobe , s_write_strobe : std_logic := '0'; -- ! Strobes high to register data from input and to output
begin -- rtl
-- purpose: part of "ring oscillator" transfering strobe between clock domains
-- type : combinational
-- inputs : clk_read_i
-- outputs:
p_gen_capture_strobe: process (clk_input_i)
begin -- process p_gen_capture_strobe
if rising_edge(clk_input_i) then
s_ring_d0 <= not s_ring_d5;
s_ring_d1 <= s_ring_d0;
s_ring_d2 <= s_ring_d1;
if s_read_strobe = '1' then
s_registered_data <= data_i;
end if;
end if;
end process p_gen_capture_strobe;
s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe with
--width one clk_read_i
-- purpose: part of "ring oscillator" transfering strobe between clock domains
-- type : combinational
-- inputs : clk_output_i
-- outputs:
p_gen_output_strobe: process (clk_output_i)
begin -- process p_gen_output_strobe
if rising_edge(clk_output_i) then
s_ring_d3 <= s_ring_d2;
s_ring_d4 <= s_ring_d3;
s_ring_d5 <= s_ring_d4;
if s_write_strobe = '1' then
data_o <= s_registered_data;
end if;
end if;
end process p_gen_output_strobe;
s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate a strobe
--
end rtl;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sdpram_8x11_sdpram_8x11_a.vhd 0 → 100644
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-- Coregen VHDL wrapper file modified by HDL Designer
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file sdpram_8x11.vhd when simulating
-- the core, sdpram_8x11. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY sdpram_8x11 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END sdpram_8x11;
ARCHITECTURE sdpram_8x11_a OF sdpram_8x11 IS
-- hds translate_off
-- synthesis translate_off
COMPONENT wrapped_sdpram_8x11
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_sdpram_8x11 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 1,
c_disable_warn_bhv_range => 1,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "NONE",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
-- hds translate_on
BEGIN
-- hds translate_off
-- synthesis translate_off
U0 : wrapped_sdpram_8x11
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
-- hds translate_on
END sdpram_8x11_a;
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----------------------------------------------------------------------------------
-- Company: Universidade de Santiago de Compostela
-- Engineer: Alvaro Dosil
--
-- Create Date: 15/08/2012
-- Module Name: Conf_Regs - Behavioral
-- Revision 1.00 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
-------------------------------------------------------
--! @file
--! @brief Synchronization module 32b
--! @author Alvaro Dosil
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sync_reg is
generic(g_Data_width : positive := 32);
port(
clk_i : in std_logic; --! synchronous clock
Async_i : in std_logic_vector(g_Data_width-1 downto 0); --! Asynchronous input data
Sync_o : out std_logic_vector(g_Data_width-1 downto 0)); --! Synchronous output data
end sync_reg;
--! @brief
--! @details Synchronize words (n bits)of data
architecture Behavioral of sync_reg is
signal s_async_i : std_logic_vector(g_Data_width-1 downto 0);
signal s_sync_o : std_logic_vector(g_Data_width-1 downto 0);
begin
loop0: for i in 0 to g_Data_width-1 generate
begin
reg: entity work.Reg_2clks
port map(
clk_i => clk_i,
async_i => s_async_i(i),
sync_o => s_sync_o(i));
end generate;
s_async_i <= Async_i;
Sync_o <= s_sync_o;
end Behavioral;
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--=============================================================================
--! @file top_extphy_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.top_extphy.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:11:55 11/09/12
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY top_extphy IS
GENERIC(
NUM_DUTS : positive := 3;
NUM_TRIG_INPUTS : positive := 4
);
PORT(
busy_i : IN std_logic_vector (NUM_DUTS-1 DOWNTO 0);
cfd_discr_i : IN std_logic_vector (NUM_TRIG_INPUTS-1 DOWNTO 0);
dut_clk : IN std_logic_vector (NUM_DUTS-1 DOWNTO 0);
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
sysclk_n_i : IN std_logic;
sysclk_p_i : IN std_logic; -- ! 200 MHz xtal clock
threshold_discr_i : IN std_logic_vector (NUM_TRIG_INPUTS-1 DOWNTO 0);
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
i2c_scl_o : OUT std_logic;
leds_o : OUT std_logic_vector (3 DOWNTO 0);
phy_rstb_o : OUT std_logic;
reset_or_clk_o : OUT std_logic_vector (NUM_DUTS-1 DOWNTO 0);
triggers_o : OUT std_logic_vector (NUM_DUTS-1 DOWNTO 0);
i2c_sda_d : INOUT std_logic
);
-- Declarations
END ENTITY top_extphy ;
--
ARCHITECTURE rtl OF top_extphy IS
BEGIN
END ARCHITECTURE rtl;
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--=============================================================================
--! @file triggerInputs_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
--
--! @brief Measures arrival time of trigger pulses using two deserializers
--! clocked on 14x clock ( 640MHz) \n
--! Based on TDC code by Alvaro Dosil\n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--!
--
--! @date 15:43:57 11/08/12
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
USE work.fmcTLU.all;
library unisim ;
use unisim.vcomponents.all;
ENTITY triggerInputs IS
GENERIC(
g_NUM_INPUTS : natural := 1
);
PORT(
cfd_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
clk_4x_logic : IN std_logic; -- ! Rising edge active
strobe_4x_logic_i : IN std_logic; -- ! Pulses high once every 4 cycles of clk_4x_logic
threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); -- ! Copy of input trigger level. High bits CFD, Low threshold
edge_rising_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
edge_falling_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
edge_rising_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edge_falling_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when falling edge
ipbus_clk_i : IN std_logic;
ipbus_reset_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
clk_16x_logic_i : IN std_logic; --! 640MHz clock ( 16x 40MHz )
strobe_16x_logic_i : IN std_logic --! Pulses one cycle every 4 of 16x clock.
);
-- Declarations
END ENTITY triggerInputs ;
--
ARCHITECTURE rtl OF triggerInputs IS
signal s_rst_iserdes, s_rst_iserdes_ipb : std_logic := '0'; --! Reset ISERDES and calibrate IODELAY
signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0); -- ! inputs from comparator
type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
signal s_deserialized_threshold_data , s_deserialized_cfd_data : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
signal s_serdes_reset : std_logic := '0'; -- ! Take high to reset serdes and initiate IODELAY calibration
signal s_cfd_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
signal s_CFD_rising_edge : std_logic_vector(g_NUM_INPUTS-1 downto 0);
signal s_CFD_falling_edge : std_logic_vector(g_NUM_INPUTS-1 downto 0);
signal s_threshold_previous_late_bit : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0'); -- last bit to arrive from previous 4
signal s_CFD_previous_late_bit : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0'); -- last bit to arrive from previous 4
signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal
BEGIN
ipbus_write: process (ipbus_clk_i)
begin -- process ipb_clk_i
if rising_edge(ipbus_clk_i) then
s_rst_iserdes_ipb <= '0';
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
case ipbus_i.ipb_addr(2 downto 0) is
when "000" => s_rst_iserdes_ipb <= ipbus_i.ipb_wdata(0) ; -- Calibrate IODELAY and reset ISERDES
when others => null;
end case;
end if;
s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
end if;
end process ipbus_write;
-----------------------------------------------------------------------------
-- IPBUS read
-----------------------------------------------------------------------------
ipbus_o.ipb_rdata <= (others => '1');
ipbus_o.ipb_ack <= s_ipbus_ack;
ipbus_o.ipb_err <= '0';
-- Change clock domain
p_signals_clk_domain: process (clk_4x_logic )
begin -- process p_internal_triggers
if rising_edge(clk_4x_logic) then
s_rst_iserdes <= s_rst_iserdes_ipb;
end if;
end process;
-----------------------------------------------------------------------------
-- Connect up trigger inputs to deserializers and a LUT to determine
-- arrival time
-----------------------------------------------------------------------------
trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
thresholdInputBuffer: IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "LVDS_25")
port map (
O => s_threshold_discr_input(triggerInput),
I => threshold_discr_p_i(triggerInput),
IB => threshold_discr_n_i(triggerInput)
);
thresholdDeserializer: entity work.dualSERDES_1to4
port map (
serdes_reset_i => s_rst_iserdes,
data_i => s_threshold_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
strobe_i => strobe_16x_logic_i,
data_o => s_deserialized_threshold_data(triggerInput)
);
thresholdLUT : entity work.arrivalTimeLUT
port map (
clk_4x_logic_i => clk_4x_logic,
strobe_4x_logic_i => strobe_4x_logic_i,
deserialized_data_i => s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput),
first_rising_edge_time_o => edge_rising_times_o(triggerInput), --trigger_times_o(triggerInput),
last_falling_edge_time_o => edge_falling_times_o(triggerInput), --open,
rising_edge_o => edge_rising_o(triggerInput), --trigger_o(triggerInput),
falling_edge_o => edge_falling_o(triggerInput),
multiple_edges_o => open
);
CFDInputBuffer: IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "LVDS_25")
port map (
O => s_CFD_discr_input(triggerInput),
I => CFD_discr_p_i(triggerInput),
IB => CFD_discr_n_i(triggerInput)
);
CFDDeserializer: entity work.dualSERDES_1to4
port map (
serdes_reset_i => s_rst_iserdes,
data_i => s_CFD_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
strobe_i => strobe_16x_logic_i,
data_o => s_deserialized_CFD_data(triggerInput)
);
CFDLUT : entity work.arrivalTimeLUT
port map (
clk_4x_logic_i => clk_4x_logic,
strobe_4x_logic_i => strobe_4x_logic_i,
deserialized_data_i => s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput),
first_rising_edge_time_o => s_cfd_trigger_times(triggerInput),
last_falling_edge_time_o => open,
rising_edge_o => s_CFD_rising_edge(triggerInput),
falling_edge_o => s_CFD_falling_edge(triggerInput),
multiple_edges_o => open
);
p_register_delayed_bits : process ( clk_4x_logic )
begin
if rising_edge(clk_4x_logic) then
s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
end if ;
end process;
end generate trigger_input_loop;
trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_CFD_discr_input;
END ARCHITECTURE rtl;
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DEFAULT atom 1
}
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}
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}
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}
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}
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}
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}
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