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AIDA-2020 TLU - Gateware
Commit e006730b authored by David Cussans's avatar David Cussans
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Introduction.markdown 0 → 100644
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Introduction to AIDA FMC Mini-TLU {#mainpage}
=================================
The TLU provides different parts of a Particle Physics Beam-Test
system with the information they need to synchronize data taken with
different detectors. The detectors are also refered to as Devices
Under Test (DUT).
Functions of TLU
----------------
- Trigger.
The TLU can combine signals from detectors in the beam-line ( often
scintillation detectors ) to produce a trigger that is sent to the
different DUT. Each DUT can indicate to the TLU that it is busy and
unable to take any further data.
- Particle Timestamping
The arrival time of every pulse from the beam-detectors is recorded.
- Clock and Synchronization Signals.
The TLU produces clock and synchronization signals that allow the
internal counters of different DUT to be sychronized.
N.B. Not all the functions of the TLU may be used in a given beam-test
system. For example, it is common to only use the Trigger/Busy
function of the TLU.
Firmare Structure
-----------------
The firmware is almost exclusively written in VHDL. The top level
entitity is [top_extphy](top_extphy_struct)
The HDL-Designer package by Mentor graphics has been used to develop
some of the code, mainly the top-level structure. However, is is not
necessary to use HDL-Designer to build the firmware. In fact the VHDL
files produced by HDL-Designer can also be edited "by hand" without
using the tool.
Building Firmware
-----------------
Instructions on building the firmware are found
[here](@ref buildingfirmware).
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Firmware for AIDA miniTLU
-------------------------
Needs "IPBus" to communuicate via Ethernet to host.
To build firmware
Check out AIDA mTLU firmware from OHWR:
http://svn.ohwr.org/fmc-mtlu/trunk/firmware fmc-tlu-mtlu-firmware
Check out IPBus firmware from HEPForge:
svn co http://cactus.hepforge.org/svn/tags/IPbusFirmware_pre_131_RAL IPbusFirmware
Copy ise_project directory ( it will be where all the files produced by the ISE tools will end up ):
cp -r fmc-tlu-mtlu-firmware/ise_projects/fmc_tlu_top_sp601 .
move into the newly created directory:
cd fmc_tlu_top_sp601
Create some soft links to the IPBus and FMC-TLU directories:
ln -s ../IPbusFirmware_pre_131_RAL/firmware ipbus-firmware
ln -s ../fmc-tlu-mtlu-firmware .
Run setup script to create a directory to store output from CoreGen
./setup_ipcore_dir.sh
Run ise
The messages about missing IPCores need to be solved by:
Start the core generator GUI from the Tools menu. Double check that coregen has the correct part settings (doesn't always work), and select:
'Project' -> 'Regenerate all project IP'
And then wait a while.
Exit coregen GUI once done.
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Firmware for AIDA miniTLU {#buildingfirmware}
=========================
Uses the "IPBus" system to communuicate via Ethernet to host.
Needs Xilinx ISE tools to build. The scripts assume ISE 14.6 or newer.
Needs a licence for the Xilinx Gigabit ethernet soft core (
tri_mode_eth_mac ) if using an external Physical interface chip
(e.g. for "Copper" Ethernet interface).
Needs "IPBus" to communuicate via Ethernet to host.
Scripts developed on a Linux PC. Need to use custom scripts because the
standard Xilinx auto-generated ones "contaminate" directories that are under
version-management control with files generated by core regeneration process.
Firmware build scripts may work under Windows/Cygwin or Windows/MinGW
but not tested.
To build firmware:
1. Install Xilinx ISE 14.6 (or newer) and set up the environment variables.
2. Create a working directory somewhere , <working_directory>
3. <pre> cd <working_directory> </pre>
4. Get a copy of the build scripts:
+ <pre> svn cat http://svn.ohwr.org/fmc-mtlu/branches/dgc_scripted_build_ipbus2/firmware/scripts/setup_workspace.sh > setup_workspace.sh </pre>
+ <pre> svn cat http://svn.ohwr.org/fmc-mtlu/branches/dgc_scripted_build_ipbus2/firmware/scripts/build_bitstream.sh > build_bitstream.sh </pre>
+ Edit setup_workspace.sh to reflect which FPGA carrier board you want to build the firmware for.Currently supported boards: Xilinx SP601 , Xilinx SP605 . Default is SP601
5. Execute the script to set-up the ISE project:
<pre> sh setup_workspace.sh </pre>
This will check out copies of the IPBus and AIDA mini-TLU repositories,
create a directory for the files produced by firmware synthesise
and create a Xilinx ISE project file.
6. Produce the bit-stream
+ either:
+ - Open the Xilinx project file at <working_directory>/workspace/fmc-mtlu.xise
+ - Select Tools->COREGEN
+ - When Coregen starts select Project->Upgrade and Regenerate all project IP ( this will take several minutes )
+ - Make sure the top-level file is selected and click on "Generate Programming File"
+ or:
+ - Execute the build_bitstream.sh script.
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
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......@@ -68,8 +68,11 @@ END ENTITY top_extphy ;
------------------------------------------------------------------------------- --
-- VHDL -- VHDL Architecture work.top_extphy.struct
--
--! @brief \n
--! \n
--! @brief Top level entity for FMC-based mini-TLU for AIDA
--! @details This VHDL file is generated by HDL-Designer. If you want to change
--! it, use HDL designer.
--! The ports to the top_extphy entity are physical input/output signals
--! to/from the FPGA.
--
--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (kipper.phy.bris.ac.uk))
--
......
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