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AIDA-2020 TLU - Gateware
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AIDA-2020 TLU - Gateware
Commits
ae0fe926
Commit
ae0fe926
authored
Apr 10, 2019
by
David Cussans
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Adding simulation file ( top_sim.vhd ) and associated *.dep file ( top_sim.dep )
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top_sim.dep
AIDA_tlu/projects/sim/firmware/cfg/top_sim.dep
+29
-0
top_sim.vhd
AIDA_tlu/projects/sim/firmware/hdl/top_sim.vhd
+174
-0
simulate_tlu_firmware.sh
AIDA_tlu/scripts/simulate_tlu_firmware.sh
+53
-0
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AIDA_tlu/projects/sim/firmware/cfg/top_sim.dep
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View file @
ae0fe926
#-------------------------------------------------------------------------------
#
# Copyright 2019 - University of Bristol
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# - - -
#
# Additional information about ipbus-firmare and the list of ipbus-firmware
# contacts are available at
#
# https://ipbus.web.cern.ch/ipbus
#
#-------------------------------------------------------------------------------
src top_sim.vhd
include -c AIDA_tlu/projects/TLU_v1e top_tlu_1e_a35.dep
AIDA_tlu/projects/sim/firmware/hdl/top_sim.vhd
0 → 100644
View file @
ae0fe926
-- Testbench created online at:
-- www.doulos.com/knowhow/perl/testbench_creation/
-- Copyright Doulos Ltd
-- SD, 03 November 2002
library
IEEE
;
use
IEEE
.
Std_logic_1164
.
all
;
use
IEEE
.
Numeric_Std
.
all
;
entity
top_tb
is
generic
(
g_NUM_DUTS
:
positive
:
=
4
;
g_NUM_TRIG_INPUTS
:
positive
:
=
6
);
end
;
architecture
bench
of
top_tb
is
component
top
generic
(
constant
FW_VERSION
:
unsigned
(
31
downto
0
):
=
X"1e000022"
;
g_NUM_DUTS
:
positive
:
=
4
;
g_NUM_TRIG_INPUTS
:
positive
:
=
6
;
g_NUM_EDGE_INPUTS
:
positive
:
=
6
;
g_NUM_EXT_SLAVES
:
positive
:
=
8
;
g_EVENT_DATA_WIDTH
:
positive
:
=
64
;
g_IPBUS_WIDTH
:
positive
:
=
32
;
g_SPILL_COUNTER_WIDTH
:
positive
:
=
12
;
g_BUILD_SIMULATED_MAC
:
integer
:
=
0
);
port
(
sysclk
:
in
std_logic
;
sysclk_50_o_p
:
out
std_logic
;
sysclk_50_o_n
:
out
std_logic
;
sysclk_40_i_p
:
in
std_logic
;
sysclk_40_i_n
:
in
std_logic
;
leds
:
out
std_logic_vector
(
3
downto
0
);
gpio
:
out
std_logic
;
rgmii_txd
:
out
std_logic_vector
(
3
downto
0
);
rgmii_tx_ctl
:
out
std_logic
;
rgmii_txc
:
out
std_logic
;
rgmii_rxd
:
in
std_logic_vector
(
3
downto
0
);
rgmii_rx_ctl
:
in
std_logic
;
rgmii_rxc
:
in
std_logic
;
phy_rstn
:
out
std_logic
;
i2c_scl_b
:
inout
std_logic
;
i2c_sda_b
:
inout
std_logic
;
i2c_reset
:
out
std_logic
;
clk_gen_rst
:
out
std_logic
;
busy_i
:
in
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
busy_o
:
out
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
cont_i
:
in
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
cont_o
:
out
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
spare_i
:
in
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
spare_o
:
out
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
triggers_i
:
in
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
triggers_o
:
out
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
dut_clk_i
:
in
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
dut_clk_o
:
out
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
threshold_discr_n_i
:
in
std_logic_vector
(
g_NUM_TRIG_INPUTS
-1
downto
0
);
threshold_discr_p_i
:
in
std_logic_vector
(
g_NUM_TRIG_INPUTS
-1
downto
0
)
);
end
component
;
signal
sysclk
,
sysclk_50
,
sysclk_40
:
std_logic
;
signal
sysclk_50_o_p
:
std_logic
;
signal
sysclk_50_o_n
:
std_logic
;
signal
sysclk_40_i_p
:
std_logic
;
signal
sysclk_40_i_n
:
std_logic
;
signal
leds
:
std_logic_vector
(
3
downto
0
);
signal
gpio
:
std_logic
;
signal
rgmii_txd
:
std_logic_vector
(
3
downto
0
);
signal
rgmii_tx_ctl
:
std_logic
;
signal
rgmii_txc
:
std_logic
;
signal
rgmii_rxd
:
std_logic_vector
(
3
downto
0
);
signal
rgmii_rx_ctl
:
std_logic
;
signal
rgmii_rxc
:
std_logic
;
signal
phy_rstn
:
std_logic
;
signal
i2c_scl_b
:
std_logic
;
signal
i2c_sda_b
:
std_logic
;
signal
i2c_reset
:
std_logic
;
signal
clk_gen_rst
:
std_logic
;
signal
busy_i
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
busy_o
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
cont_i
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
cont_o
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
spare_i
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
spare_o
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
triggers_i
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
triggers_o
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
dut_clk_i
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
dut_clk_o
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
threshold_discr_n_i
:
std_logic_vector
(
g_NUM_TRIG_INPUTS
-1
downto
0
);
signal
threshold_discr_p_i
:
std_logic_vector
(
g_NUM_TRIG_INPUTS
-1
downto
0
)
;
-- Simulate mis-match between nominal 50MHz clock freq and actual freq
constant
freqDrift
:
time
:
=
0
.
01
ns
;
constant
sysclk_period
:
time
:
=
20
ns
+
freqDrift
;
constant
sysclk_40_period
:
time
:
=
25
ns
;
signal
stop_the_clock
:
boolean
;
begin
-- Insert values for generic parameters !!
uut
:
top
generic
map
(
g_BUILD_SIMULATED_MAC
=>
1
)
port
map
(
sysclk
=>
sysclk
,
sysclk_50_o_p
=>
sysclk_50_o_p
,
sysclk_50_o_n
=>
sysclk_50_o_n
,
sysclk_40_i_p
=>
sysclk_40_i_p
,
sysclk_40_i_n
=>
sysclk_40_i_n
,
leds
=>
leds
,
gpio
=>
gpio
,
rgmii_txd
=>
rgmii_txd
,
rgmii_tx_ctl
=>
rgmii_tx_ctl
,
rgmii_txc
=>
rgmii_txc
,
rgmii_rxd
=>
rgmii_rxd
,
rgmii_rx_ctl
=>
rgmii_rx_ctl
,
rgmii_rxc
=>
rgmii_rxc
,
phy_rstn
=>
phy_rstn
,
i2c_scl_b
=>
i2c_scl_b
,
i2c_sda_b
=>
i2c_sda_b
,
i2c_reset
=>
i2c_reset
,
clk_gen_rst
=>
clk_gen_rst
,
busy_i
=>
busy_i
,
busy_o
=>
busy_o
,
cont_i
=>
cont_i
,
cont_o
=>
cont_o
,
spare_i
=>
spare_i
,
spare_o
=>
spare_o
,
triggers_i
=>
triggers_i
,
triggers_o
=>
triggers_o
,
dut_clk_i
=>
dut_clk_i
,
dut_clk_o
=>
dut_clk_o
,
threshold_discr_n_i
=>
threshold_discr_n_i
,
threshold_discr_p_i
=>
threshold_discr_p_i
);
stimulus
:
process
begin
-- Put initialisation code here
-- Put test bench stimulus code here
wait
;
stop_the_clock
<=
true
;
wait
;
end
process
;
sysclk_clock
:
process
begin
while
not
stop_the_clock
loop
sysclk
<=
'0'
,
'1'
after
sysclk_period
/
2
;
wait
for
sysclk_period
;
end
loop
;
wait
;
end
process
;
sysclk_40_clock
:
process
begin
while
not
stop_the_clock
loop
sysclk_40
<=
'0'
,
'1'
after
sysclk_40_period
/
2
;
wait
for
sysclk_40_period
;
end
loop
;
wait
;
end
process
;
sysclk_40_i_p
<=
sysclk_40
;
sysclk_40_i_n
<=
not
sysclk_40
;
end
;
AIDA_tlu/scripts/simulate_tlu_firmware.sh
0 → 100644
View file @
ae0fe926
#!/bin/sh
# Put which branch of Git to use here...
IPBUS_BRANCH
=
"-b v1.3"
TLU_BRANCH
=
"-b 1e000022"
mkdir
work
cd
work
# IPBB_VERSION="0.3.13"
IPBB_VERSION
=
"0.4.3"
curl
-L
https://github.com/ipbus/ipbb/archive/v
${
IPBB_VERSION
}
.tar.gz |
tar
xvz
# ( or git clone git@github.com:ipbus/ipbb.git )
source
ipbb-
${
IPBB_VERSION
}
/env.sh
ipbb init build
cd
build
ipbb add git https://github.com/ipbus/ipbus-firmware.git
${
IPBUS_BRANCH
}
ipbb add git https://ohwr.org/project/fmc-mtlu-gw.git
${
TLU_BRANCH
}
# For read/write load a valid ssh key and use the repo below ....
# ipbb add git ssh://git@ohwr.org/fmc-projects/fmc-mtlu/fmc-mtlu-gw.git
# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
echo
"Generating address table VHDL from XML file"
pushd
src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/addr_table
pwd
/opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode
-v
TLUaddrmap.xml
#copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/hdl/
mv
ipbus_decode_TLUaddrmap.vhd ../firmware/hdl/
popd
ipbb proj create sim TLU_1e_sim fmc-mtlu-gw:AIDA_tlu/projects/sim
-t
top_sim.dep
source
/software/CAD/setup_mentor2019.sh
ipbb sim setup-simlib ipcores fli
# First time or only if machine is rebooted
# Requires sudo rights
## ipbb sim virtualtap --ip 192.168.231.1
# Every time the sources
ipbb sim make-project
# Run the simulation
./vsim
-c
work.top
-do
‘run
-all
’
# In a different window
## ping 192.168.231.128
deactivate
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