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AIDA-2020 TLU - Gateware
Commit 8d792018 authored by David Cussans's avatar David Cussans
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Manual merge of scripted build branch back to trunk

parent 3b6bcc34
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Showing with 64 additions and 20767 deletions
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/IPBusInterface_rtl.vhd → hdl/common/IPBusInterface_rtl.vhd
View file @ 8d792018
......@@ -86,13 +86,15 @@ ARCHITECTURE rtl OF IPBusInterface IS
signal ipb_master_out : ipb_wbus;
signal ipb_master_in : ipb_rbus;
signal mac_addr: std_logic_vector(47 downto 0);
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
signal ip_addr: std_logic_vector(31 downto 0);
signal s_ipb_clk : std_logic;
signal hostbus_in: emac_hostbus_in;
signal hostbus_out: emac_hostbus_out;
signal s_ipbw_internal: ipb_wbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_ipbr_internal: ipb_rbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_sysclk : std_logic;
signal pkt_rx, pkt_tx, pkt_rx_led, pkt_tx_led, sys_rst: std_logic;
BEGIN
......@@ -120,52 +122,58 @@ BEGIN
-- In this version, consists of hard MAC core and GMII interface to external PHY
-- Can be replaced by any other MAC / PHY combination
eth: entity work.eth_s6_gmii port map(
clk125 => clk125,
rst => rst_125,
gmii_gtx_clk => gmii_gtx_clk_o,
gmii_tx_en => gmii_tx_en_o,
gmii_tx_er => gmii_tx_er_o,
gmii_txd => gmii_txd_o,
gmii_rx_clk => gmii_rx_clk_i,
gmii_rx_dv => gmii_rx_dv_i,
gmii_rx_er => gmii_rx_er_i,
gmii_rxd => gmii_rxd_i,
txd => mac_txd,
txdvld => mac_txdvld,
txack => mac_txack,
rxd => mac_rxd,
rxclko => mac_rxclko,
rxdvld => mac_rxdvld,
rxgoodframe => mac_rxgoodframe,
rxbadframe => mac_rxbadframe,
hostbus_in => hostbus_in,
hostbus_out => hostbus_out
);
eth: entity work.eth_s6_gmii port map(
clk125 => clk125,
rst => rst_125,
gmii_gtx_clk => gmii_gtx_clk_o,
gmii_tx_en => gmii_tx_en_o,
gmii_tx_er => gmii_tx_er_o,
gmii_txd => gmii_txd_o,
gmii_rx_clk => gmii_rx_clk_i,
gmii_rx_dv => gmii_rx_dv_i,
gmii_rx_er => gmii_rx_er_i,
gmii_rxd => gmii_rxd_i,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
phy_rstb_o <= '1';
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
generic map (
BUFWIDTH => 2)
port map(
mac_clk => clk125,
rst_macclk => rst_125,
ipb_clk => s_ipb_clk,
rst_ipb => rst_ipb,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_master_out,
ipb_in => ipb_master_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt_rx => pkt_rx,
pkt_tx => pkt_tx,
pkt_rx_led => pkt_rx_led,
pkt_tx_led => pkt_tx_led
);
ipbus: entity work.ipbus_ctrl_udponly port map(
ipb_clk => s_ipb_clk,
rst_ipb => rst_ipb,
rst_macclk => rst_125,
mac_txclk => clk125,
mac_rxclk => mac_rxclko,
mac_rxd => mac_rxd,
mac_rxdvld => mac_rxdvld,
mac_rxgoodframe => mac_rxgoodframe,
mac_rxbadframe => mac_rxbadframe,
mac_txd => mac_txd,
mac_txdvld => mac_txdvld,
mac_txack => mac_txack,
ipb_out => ipb_master_out,
ipb_in => ipb_master_in,
mac_addr => mac_addr,
ip_addr => ip_addr
);
mac_addr <= X"020ddba115" & dip_switch_i & X"0"; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c8" & dip_switch_i & X"0"; -- 192.168.200.X
......@@ -173,8 +181,6 @@ BEGIN
fabric: entity work.ipbus_fabric
generic map(NSLV => NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES)
port map(
ipb_clk => s_ipb_clk,
rst => rst_ipb,
ipb_in => ipb_master_out,
ipb_out => ipb_master_in,
ipb_to_slaves => s_ipbw_internal,
......@@ -191,17 +197,8 @@ BEGIN
ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-2),
ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-2)
);
-- Hostbus slave. Need to connect or IPBus_pre131_ral won't work...
-- No point in passing host bus out in/out of block.
hostbus_interface: entity work.ipbus_emac_hostbus
port map(
clk => s_ipb_clk,
reset => rst_ipb,
ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
hostbus_out => hostbus_in,
hostbus_in => hostbus_out);
-- N.B. Remove port to s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
-- No longer used by hostbus
END ARCHITECTURE rtl;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/DUTInterfaces_rtl.vhd.rlnk 0 → 100644
View file @ 8d792018
/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/GPP_ipb_rtl.vhd deleted 100644 → 0
View file @ 3b6bcc34
This diff is collapsed.
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/GPP_rtl.vhd deleted 100644 → 0
View file @ 3b6bcc34
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hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/IPBusInterface_rtl.vhd.rlnk 0 → 100644
View file @ 8d792018
/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arrivalTimeLUT_rtl.vhd.rlnk 0 → 100644
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/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/dpram_8x12_32x10_dpram_8x12_32x10_a.vhd deleted 100644 → 0
View file @ 3b6bcc34
-- Coregen VHDL wrapper file modified by HDL Designer
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file dpram_8x12_32x10.vhd when simulating
-- the core, dpram_8x12_32x10. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY dpram_8x12_32x10 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END dpram_8x12_32x10;
ARCHITECTURE dpram_8x12_32x10_a OF dpram_8x12_32x10 IS
-- hds translate_off
-- synthesis translate_off
COMPONENT wrapped_dpram_8x12_32x10
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_dpram_8x12_32x10 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 1,
c_disable_warn_bhv_range => 1,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 1024,
c_read_width_a => 8,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "NONE",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 1024,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 32,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
-- hds translate_on
BEGIN
-- hds translate_off
-- synthesis translate_off
U0 : wrapped_dpram_8x12_32x10
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
-- hds translate_on
END dpram_8x12_32x10_a;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/dualSERDES_1to4_rtl.vhd.rlnk 0 → 100644
View file @ 8d792018
/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventBuffer_rtl.vhd.rlnk 0 → 100644
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/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventFormatter_rtl.vhd.rlnk 0 → 100644
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/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/i2c_master_rtl.vhd.rlnk 0 → 100644
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/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_emac_hostbus.vhd deleted 100644 → 0
View file @ 3b6bcc34
-- Generic ipbus slave config register for testing
--
-- generic addr_width defines number of significant address bits
--
-- We use one cycle of read / write latency to ease timing (probably not necessary)
-- The q outputs change immediately on write (no latency).
--
-- Dave Newbold, March 2011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.ipbus.all;
use work.emac_hostbus_decl.all;
entity ipbus_emac_hostbus is
port(
clk: in std_logic;
reset: in std_logic;
ipbus_in: in ipb_wbus;
ipbus_out: out ipb_rbus;
hostbus_out: out emac_hostbus_in;
hostbus_in: in emac_hostbus_out
);
end ipbus_emac_hostbus;
architecture rtl of ipbus_emac_hostbus is
signal emac1sel, mdiocyc, acyc, dcyc, dcyc_d: std_logic;
signal addr: std_logic_vector(9 downto 0);
begin
ipbus_out.ipb_rdata <= hostbus_in.hostrddata when ipbus_in.ipb_addr(0) = '0'
else X"0000" & "000" & emac1sel & mdiocyc & '0' & addr;
acyc <= ipbus_in.ipb_strobe and ipbus_in.ipb_addr(0);
dcyc <= ipbus_in.ipb_strobe and not ipbus_in.ipb_addr(0);
process(clk)
begin
if rising_edge(clk) then
if acyc = '1' and ipbus_in.ipb_write = '1' then
emac1sel <= ipbus_in.ipb_wdata(12);
mdiocyc <= ipbus_in.ipb_wdata(11);
addr <= ipbus_in.ipb_wdata(9 downto 0);
end if;
dcyc_d <= dcyc;
end if;
end process;
hostbus_out.hostwrdata <= ipbus_in.ipb_wdata;
hostbus_out.hostaddr <= addr;
hostbus_out.hostemac1sel <= emac1sel;
hostbus_out.hostclk <= clk;
hostbus_out.hostmiimsel <= not (dcyc or (dcyc_d and ipbus_in.ipb_write)) or mdiocyc;
hostbus_out.hostopcode(1) <= not ipbus_in.ipb_write;
hostbus_out.hostopcode(0) <= ipbus_in.ipb_write;
hostbus_out.hostreq <= dcyc and mdiocyc and hostbus_in.hostmiimrdy;
ipbus_out.ipb_ack <= acyc or (dcyc and dcyc_d and (hostbus_in.hostmiimrdy or not mdiocyc));
ipbus_out.ipb_err <= '0';
end rtl;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/logic_clocks_rtl.vhd.rlnk 0 → 100644
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/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sdpram_8x11_sdpram_8x11_a.vhd deleted 100644 → 0
View file @ 3b6bcc34
-- Coregen VHDL wrapper file modified by HDL Designer
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file sdpram_8x11.vhd when simulating
-- the core, sdpram_8x11. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY sdpram_8x11 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END sdpram_8x11;
ARCHITECTURE sdpram_8x11_a OF sdpram_8x11 IS
-- hds translate_off
-- synthesis translate_off
COMPONENT wrapped_sdpram_8x11
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_sdpram_8x11 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 1,
c_disable_warn_bhv_range => 1,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "NONE",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
-- hds translate_on
BEGIN
-- hds translate_off
-- synthesis translate_off
U0 : wrapped_sdpram_8x11
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
-- hds translate_on
END sdpram_8x11_a;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/triggerInputs_rtl.vhd.rlnk 0 → 100644
View file @ 8d792018
/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
\ No newline at end of file
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/triggerLogic_rtl.vhd.rlnk 0 → 100644
View file @ 8d792018
/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
\ No newline at end of file
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