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AIDA-2020 TLU - Gateware
Commit 4c6e52ca authored by Thomas Blake's avatar Thomas Blake
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First commit of changes for digilent nexys video from technician at Warwick

parent 57f8638c
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Showing with 257 additions and 5 deletions
AIDA_tlu/components/tlu/firmware/hdl/eventFormatter_rtl.vhd
View file @ 4c6e52ca
......@@ -164,6 +164,10 @@ ARCHITECTURE rtl OF eventFormatter IS
signal s_captured_trigger_times : t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Array of trigger times,captured when trigger
signal abc: ipb_reg_v(1 downto 0);
BEGIN
-----------------------------------------------------------------------------
......@@ -203,12 +207,16 @@ BEGIN
s_coarse_timestamp_ipbus(1) when "011",
(others => '1') when others;
abc <= ( "0000000000000000" & s_coarse_timestamp(s_coarse_timestamp'left downto 32) , s_coarse_timestamp(31 downto 0) );
cmp_timestampDomainCross : entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => 2 )
port map (
clk_input_i => clk_4x_logic_i,
data_i => ( "0000000000000000" & s_coarse_timestamp(s_coarse_timestamp'left downto 32) , s_coarse_timestamp(31 downto 0) ) ,
data_i => abc,
data_o => s_coarse_timestamp_ipbus,
clk_output_i => ipbus_clk_i
);
......
AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ 4c6e52ca
......@@ -51,7 +51,7 @@ use work.ipbus.ALL;
entity top is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000025"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"1e000027"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......@@ -62,15 +62,18 @@ entity top is
g_BUILD_SIMULATED_MAC :integer := 0
);
port(
-- Voltage regulator setting
vadj: out std_logic_vector(1 downto 0);
--Clock
osc_clk: in std_logic; --50 MHz clock input from FPGA
osc_clk: in std_logic; --100 MHz clock input from xtal osc
--clk_enclustra: in std_logic; --Enclustra onboard oscillator 50 MHz. Used for the IPBus block
sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins
sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins
sysclk_40_i_p: in std_logic;
sysclk_40_i_n: in std_logic;
--Misc
leds: out std_logic_vector(3 downto 0); -- status LEDs
leds: out std_logic_vector(7 downto 0); -- status LEDs
--dip_sw: in std_logic_vector(3 downto 0); -- switches
--cfg: in std_logic_vector(3 downto 0); -- switches
gpio: out std_logic; -- gpio pin on J1 (eventually make it inout)
......@@ -118,6 +121,7 @@ end top;
architecture rtl of top is
signal osc_clk_50MHz: std_logic;
signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, clk_200, sysclk_40, clk_encl_buf, userled: std_logic;
signal mac_addr: std_logic_vector(47 downto 0);
signal ip_addr: std_logic_vector(31 downto 0);
......@@ -175,6 +179,16 @@ architecture rtl of top is
signal ctrl, stat: ipb_reg_v(0 downto 0);
--My signals
--SIGNAL busy_toggle_o : std_logic_vector(g_NUM_DUTS-1 downto 0);
component clkinPLL
port
(-- Clock in ports
-- Clock out ports
clk_out1 : out std_logic;
clk_in1 : in std_logic
);
end component;
----------------------------------------------
----------------------------------------------
......@@ -420,6 +434,44 @@ architecture rtl of top is
begin
led_flash: process(osc_clk_50MHz)
variable t: natural:=0;
variable v: std_logic_vector(3 downto 0);
begin
if (rising_edge(osc_clk_50MHz)) then
t := t + 1;
if (t >= 250000000) then t := 0; end if;
if (t = 0) then
v := "0000";
elsif (t > 200000000) then
v := "1111";
elsif (t > 150000000) then
v := "0111";
elsif (t > 100000000) then
v := "0011";
elsif (t > 50000000) then
v := "0001";
end if;
leds(7 downto 4) <= v;
end if;
end process;
-- Enclustra board had 50MHz clock input whereas the Digilent has 100MHz input
-- use PLL to convert the 100MHz down to 50MHz so it is compatible with the original firmware
INPUT_CLK_PLL: clkinPLL port map (
clk_out1 => osc_clk_50MHz,
clk_in1 => osc_clk
);
Vadj <= "10"; -- set voltage regulator to 2.5V
--led_iic_test <= iic_test;
--Implicit instantiation of output tristate buffers.
......@@ -793,7 +845,7 @@ begin
IBUFG_inst: IBUFG
port map (
O => clk_encl_buf,
I => osc_clk -- clk_enclustra
I => osc_clk_50MHz -- clk_enclustra
);
------------------------------------------
......
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU.tcl 0 → 100755
View file @ 4c6e52ca
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
proc false_path {patt clk} {
set p [get_ports -quiet $patt -filter {direction != out}]
if {[llength $p] != 0} {
set_input_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != out}]
set_false_path -from [get_ports $patt -filter {direction != out}]
}
set p [get_ports -quiet $patt -filter {direction != in}]
if {[llength $p] != 0} {
set_output_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != in}]
set_false_path -to [get_ports $patt -filter {direction != in}]
}
}
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU.xdc 0 → 100755
View file @ 4c6e52ca
# System clock input (100MHz)
#voltage adjust pins
set_property IOSTANDARD LVCMOS25 [get_ports {vadj[*]}]
set_property PACKAGE_PIN AB17 [get_ports {vadj[1]}]
set_property PACKAGE_PIN AA13 [get_ports {vadj[0]}]
#
#create_clock -period 10.000 -name clk_enclustra [get_nets osc_clk_50MHz]
set_false_path -through [get_pins infra/clocks/rst_reg/Q]
set_false_path -through [get_nets infra/clocks/nuke_i]
set_property IOSTANDARD LVCMOS33 [get_ports osc_clk]
set_property PACKAGE_PIN R4 [get_ports osc_clk]
#set_property IOSTANDARD LVCMOS33 [get_ports {osc_clk}]
#set_property PACKAGE_PIN R4 [get_ports {osc_clk}]
set_property IOSTANDARD LVCMOS25 [get_ports {leds[*]}]
set_property SLEW SLOW [get_ports {leds[*]}]
set_property PACKAGE_PIN T14 [get_ports {leds[0]}]
set_property PACKAGE_PIN T15 [get_ports {leds[1]}]
set_property PACKAGE_PIN T16 [get_ports {leds[2]}]
set_property PACKAGE_PIN U16 [get_ports {leds[3]}]
set_property PACKAGE_PIN V15 [get_ports {leds[4]}]
set_property PACKAGE_PIN W16 [get_ports {leds[5]}]
set_property PACKAGE_PIN W15 [get_ports {leds[6]}]
set_property PACKAGE_PIN Y13 [get_ports {leds[7]}]
#false_path {leds[*]} clk_enclustra
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_*]
set_property PACKAGE_PIN Y12 [get_ports {rgmii_txd[0]}]
set_property PACKAGE_PIN W12 [get_ports {rgmii_txd[1]}]
set_property PACKAGE_PIN W11 [get_ports {rgmii_txd[2]}]
set_property PACKAGE_PIN Y11 [get_ports {rgmii_txd[3]}]
set_property PACKAGE_PIN V10 [get_ports rgmii_tx_ctl]
set_property PACKAGE_PIN AA14 [get_ports rgmii_txc]
set_property PACKAGE_PIN AB16 [get_ports {rgmii_rxd[0]}]
set_property PACKAGE_PIN AA15 [get_ports {rgmii_rxd[1]}]
set_property PACKAGE_PIN AB15 [get_ports {rgmii_rxd[2]}]
set_property PACKAGE_PIN AB11 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN W10 [get_ports rgmii_rx_ctl]
set_property PACKAGE_PIN V13 [get_ports rgmii_rxc]
set_property IOSTANDARD LVCMOS33 [get_ports phy_rstn]
set_property PACKAGE_PIN U7 [get_ports phy_rstn]
##false_path {phy_rstn} clk_enclustra
set_property IOSTANDARD LVCMOS25 [get_ports i2c_reset]
set_property PACKAGE_PIN E19 [get_ports i2c_reset]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl_b]
set_property PACKAGE_PIN W5 [get_ports i2c_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda_b]
set_property PACKAGE_PIN V5 [get_ports i2c_sda_b]
## Trigger inputs
#set_property IOSTANDARD LVCMOS18 [get_ports {threshold_discr_p_i[*]}]
#set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
#set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {threshold_discr_n_i[*]}]
set_property PACKAGE_PIN A15 [get_ports {threshold_discr_p_i[0]}]
set_property PACKAGE_PIN A16 [get_ports {threshold_discr_n_i[0]}]
set_property PACKAGE_PIN F13 [get_ports {threshold_discr_p_i[1]}]
set_property PACKAGE_PIN F14 [get_ports {threshold_discr_n_i[1]}]
set_property PACKAGE_PIN A13 [get_ports {threshold_discr_p_i[2]}]
set_property PACKAGE_PIN A14 [get_ports {threshold_discr_n_i[2]}]
set_property PACKAGE_PIN E13 [get_ports {threshold_discr_p_i[3]}]
set_property PACKAGE_PIN E14 [get_ports {threshold_discr_n_i[3]}]
set_property PACKAGE_PIN C13 [get_ports {threshold_discr_p_i[4]}]
set_property PACKAGE_PIN B13 [get_ports {threshold_discr_n_i[4]}]
set_property PACKAGE_PIN C14 [get_ports {threshold_discr_p_i[5]}]
set_property PACKAGE_PIN C15 [get_ports {threshold_discr_n_i[5]}]
## Miscellaneous I/O
set_property IOSTANDARD LVCMOS25 [get_ports clk_gen_rst]
set_property PACKAGE_PIN D19 [get_ports clk_gen_rst]
set_property IOSTANDARD LVCMOS25 [get_ports gpio]
set_property PACKAGE_PIN B16 [get_ports gpio]
## Crystal clock
set_property IOSTANDARD LVDS_25 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN J19 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN H19 [get_ports sysclk_40_i_n]
## Output clock (currently not working so set to 0)
set_property IOSTANDARD LVCMOS25 [get_ports sysclk_50_o_p]
set_property PACKAGE_PIN C18 [get_ports sysclk_50_o_p]
set_property IOSTANDARD LVCMOS25 [get_ports sysclk_50_o_n]
set_property PACKAGE_PIN C19 [get_ports sysclk_50_o_n]
## Inputs/Outputs for DUTs
set_property IOSTANDARD LVCMOS25 [get_ports {busy_o[*]}]
set_property PACKAGE_PIN L19 [get_ports {busy_o[0]}]
set_property PACKAGE_PIN K17 [get_ports {busy_o[1]}]
set_property PACKAGE_PIN J22 [get_ports {busy_o[2]}]
set_property PACKAGE_PIN L16 [get_ports {busy_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {triggers_o[*]}]
set_property PACKAGE_PIN M15 [get_ports {triggers_o[0]}]
set_property PACKAGE_PIN H20 [get_ports {triggers_o[1]}]
set_property PACKAGE_PIN K21 [get_ports {triggers_o[2]}]
set_property PACKAGE_PIN L14 [get_ports {triggers_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {cont_o[*]}]
set_property PACKAGE_PIN K18 [get_ports {cont_o[0]}]
set_property PACKAGE_PIN J20 [get_ports {cont_o[1]}]
set_property PACKAGE_PIN M18 [get_ports {cont_o[2]}]
set_property PACKAGE_PIN N18 [get_ports {cont_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {spare_o[*]}]
set_property PACKAGE_PIN N20 [get_ports {spare_o[0]}]
set_property PACKAGE_PIN M21 [get_ports {spare_o[1]}]
set_property PACKAGE_PIN N22 [get_ports {spare_o[2]}]
set_property PACKAGE_PIN M13 [get_ports {spare_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dut_clk_o[*]}]
set_property PACKAGE_PIN G17 [get_ports {dut_clk_o[0]}]
set_property PACKAGE_PIN B17 [get_ports {dut_clk_o[1]}]
set_property PACKAGE_PIN D17 [get_ports {dut_clk_o[2]}]
set_property PACKAGE_PIN A18 [get_ports {dut_clk_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {cont_i[*]}]
set_property PACKAGE_PIN K19 [get_ports {cont_i[0]}]
set_property PACKAGE_PIN J21 [get_ports {cont_i[1]}]
set_property PACKAGE_PIN L18 [get_ports {cont_i[2]}]
set_property PACKAGE_PIN N19 [get_ports {cont_i[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {spare_i[*]}]
set_property PACKAGE_PIN M20 [get_ports {spare_i[0]}]
set_property PACKAGE_PIN L21 [get_ports {spare_i[1]}]
set_property PACKAGE_PIN M22 [get_ports {spare_i[2]}]
set_property PACKAGE_PIN L13 [get_ports {spare_i[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {triggers_i[*]}]
set_property PACKAGE_PIN M16 [get_ports {triggers_i[0]}]
set_property PACKAGE_PIN G20 [get_ports {triggers_i[1]}]
set_property PACKAGE_PIN K22 [get_ports {triggers_i[2]}]
set_property PACKAGE_PIN L15 [get_ports {triggers_i[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {busy_i[*]}]
set_property PACKAGE_PIN L20 [get_ports {busy_i[0]}]
set_property PACKAGE_PIN J17 [get_ports {busy_i[1]}]
set_property PACKAGE_PIN H22 [get_ports {busy_i[2]}]
set_property PACKAGE_PIN K16 [get_ports {busy_i[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dut_clk_i[*]}]
set_property PACKAGE_PIN G18 [get_ports {dut_clk_i[0]}]
set_property PACKAGE_PIN B18 [get_ports {dut_clk_i[1]}]
set_property PACKAGE_PIN C17 [get_ports {dut_clk_i[2]}]
set_property PACKAGE_PIN A19 [get_ports {dut_clk_i[3]}]
# -------------------------------------------------------------------------------------------------
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
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