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AIDA-2020 TLU - Gateware
Commit 388a96dd authored by David Cussans's avatar David Cussans
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* Edited build script to execute a Vivado TCL script in order to set… 

* Edited build script to execute a Vivado TCL script in order to set TLU_enclustra_v1e.xdc as "late" processing.
parent af258cee
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Showing with 8 additions and 6 deletions
AIDA_tlu/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a35.dep
View file @ 388a96dd
...@@ -15,7 +15,5 @@ src top_enclustra_tlu_v1e.vhd ...@@ -15,7 +15,5 @@ src top_enclustra_tlu_v1e.vhd
src --cd ../ucf I2C_constr.xdc src --cd ../ucf I2C_constr.xdc
src --cd ../ucf TLU_enclustra_v1e.xdc src --cd ../ucf TLU_enclustra_v1e.xdc
setup --cd ../ucf TLU_enclustra_v1e_setProcessingOrder.tcl
#include -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_a35.dep #include -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_a35.dep
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
View file @ 388a96dd
...@@ -185,10 +185,10 @@ set_input_delay -clock [get_clocks clk_ipb_i] -max 17 [get_ports i2c_scl_b] ...@@ -185,10 +185,10 @@ set_input_delay -clock [get_clocks clk_ipb_i] -max 17 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15 [get_ports i2c_sda_b] set_input_delay -clock [get_clocks clk_ipb_i] -min 15 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17 [get_ports i2c_sda_b] set_input_delay -clock [get_clocks clk_ipb_i] -max 17 [get_ports i2c_sda_b]
# #
set_output_delay -clock [get_clocks clk_ipb_i] -min 1 [get_ports i2c_scl_b] #set_output_delay -clock [get_clocks clk_ipb_i] -min 1 [get_ports i2c_scl_b]
set_output_delay -clock [get_clocks clk_ipb_i] -max 30 [get_ports i2c_scl_b] #set_output_delay -clock [get_clocks clk_ipb_i] -max 30 [get_ports i2c_scl_b]
set_output_delay -clock [get_clocks clk_ipb_i] -min 1 [get_ports i2c_sda_b] #set_output_delay -clock [get_clocks clk_ipb_i] -min 1 [get_ports i2c_sda_b]
set_output_delay -clock [get_clocks clk_ipb_i] -max 30 [get_ports i2c_sda_b] #set_output_delay -clock [get_clocks clk_ipb_i] -max 30 [get_ports i2c_sda_b]
# Ad-hoc hack # Ad-hoc hack
......
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl
View file @ 388a96dd
set_property PROCESSING_ORDER LATE [get_files TLU_enclustra_v1e.xdc] set_property PROCESSING_ORDER LATE [get_files TLU_enclustra_v1e.xdc]
exit
AIDA_tlu/scripts/build_tlu_firmware.sh
View file @ 388a96dd
...@@ -47,10 +47,13 @@ ipbb proj create vivado TLU_1e fmc-mtlu-gw:AIDA_tlu/projects/TLU_v1e -t top_tlu_ ...@@ -47,10 +47,13 @@ ipbb proj create vivado TLU_1e fmc-mtlu-gw:AIDA_tlu/projects/TLU_v1e -t top_tlu_
cd proj/TLU_1e cd proj/TLU_1e
ipbb vivado project ipbb vivado project
# Set correct file as design "top" # Set correct file as design "top"
#echo "BUILD: Setting the correct design as top" #echo "BUILD: Setting the correct design as top"
#vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/cfg/set_top.tcl top/top.xpr #vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/cfg/set_top.tcl top/top.xpr
# Set TLU timing contraints *.xdc file to have "late" processing order
vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl top/top.xpr
echo "BUILD: ipbb impl" echo "BUILD: ipbb impl"
ipbb vivado impl ipbb vivado impl
......
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