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AIDA-2020 TLU - Gateware
Commits
1c3bdc36
Commit
1c3bdc36
authored
Feb 11, 2014
by
David Cussans
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23 changed files
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1092 additions
and
965 deletions
+1092
-965
top_extphy_struct.vhd
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+25
-28
.cache.dat
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat
+0
-0
_bus_arb.vhd.rlnk._fpf
...mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_bus_arb.vhd.rlnk._fpf
+1
-0
_emac_hostbus_decl.vhd.rlnk._fpf
...TLU_lib/hds/.hdlsidedata/_emac_hostbus_decl.vhd.rlnk._fpf
+1
-0
_eth_s6_1000basex.vhd.rlnk._fpf
...mTLU_lib/hds/.hdlsidedata/_eth_s6_1000basex.vhd.rlnk._fpf
+1
-0
_eth_s6_gmii.vhd.rlnk._fpf
.../fmc_mTLU_lib/hds/.hdlsidedata/_eth_s6_gmii.vhd.rlnk._fpf
+1
-0
_ipbus_bus_decl.vhd.rlnk._fpf
...c_mTLU_lib/hds/.hdlsidedata/_ipbus_bus_decl.vhd.rlnk._fpf
+1
-0
_ipbus_ctrl.vhd.rlnk._fpf
...U/fmc_mTLU_lib/hds/.hdlsidedata/_ipbus_ctrl.vhd.rlnk._fpf
+1
-0
_ipbus_ctrl_decl.vhd.rlnk._fpf
..._mTLU_lib/hds/.hdlsidedata/_ipbus_ctrl_decl.vhd.rlnk._fpf
+1
-0
_ipbus_ctrl_udponly.vhd.rlnk._fpf
...LU_lib/hds/.hdlsidedata/_ipbus_ctrl_udponly.vhd.rlnk._fpf
+1
-0
_ipbus_fabric.vhd.rlnk._fpf
...fmc_mTLU_lib/hds/.hdlsidedata/_ipbus_fabric.vhd.rlnk._fpf
+1
-0
_ipbus_package.vhd.rlnk._fpf
...mc_mTLU_lib/hds/.hdlsidedata/_ipbus_package.vhd.rlnk._fpf
+1
-0
_mac_arbiter.vhd.rlnk._fpf
.../fmc_mTLU_lib/hds/.hdlsidedata/_mac_arbiter.vhd.rlnk._fpf
+1
-0
_mac_arbiter_decl.vhd.rlnk._fpf
...mTLU_lib/hds/.hdlsidedata/_mac_arbiter_decl.vhd.rlnk._fpf
+1
-0
_transactor.vhd.rlnk._fpf
...U/fmc_mTLU_lib/hds/.hdlsidedata/_transactor.vhd.rlnk._fpf
+1
-0
_transactor_rx.vhd.rlnk._fpf
...mc_mTLU_lib/hds/.hdlsidedata/_transactor_rx.vhd.rlnk._fpf
+1
-0
_transactor_sm.vhd.rlnk._fpf
...mc_mTLU_lib/hds/.hdlsidedata/_transactor_sm.vhd.rlnk._fpf
+1
-0
_transactor_tx.vhd.rlnk._fpf
...mc_mTLU_lib/hds/.hdlsidedata/_transactor_tx.vhd.rlnk._fpf
+1
-0
_udp_shim.vhd.rlnk._fpf
...TLU/fmc_mTLU_lib/hds/.hdlsidedata/_udp_shim.vhd.rlnk._fpf
+1
-0
struct.bd
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd
+77
-58
struct.bd.bak
...signer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.bak
+887
-854
symbol.sb
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb
+45
-25
i2c_chipscope_debug.cdc
src/test/i2c_chipscope_debug.cdc
+41
-0
No files found.
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
View file @
1c3bdc36
-- VHDL Entity work.top_extphy.symbol
--
-- Created:
-- by - phdgc.users (
kipper
.phy.bris.ac.uk)
-- at - 1
8:45:17 07/24/13
-- by - phdgc.users (
fortis
.phy.bris.ac.uk)
-- at - 1
6:06:33 01/24/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.
1 (Build 6
)
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.
2b (Build 5
)
--
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
all
;
...
...
@@ -22,7 +22,7 @@ ENTITY top_extphy IS
);
PORT
(
busy_n_i
:
IN
std_logic_vector
(
g_NUM_DUTS
-1
DOWNTO
0
);
busy_p_i
:
IN
std_logic_vector
(
g_NUM_DUTS
-1
DOWNTO
0
);
busy_p_i
:
IN
std_logic_vector
(
g_NUM_DUTS
-1
DOWNTO
0
);
--! Busy lines from DUTs ( active high )
cfd_discr_n_i
:
IN
std_logic_vector
(
g_NUM_TRIG_INPUTS
-1
DOWNTO
0
);
cfd_discr_p_i
:
IN
std_logic_vector
(
g_NUM_TRIG_INPUTS
-1
DOWNTO
0
);
dip_switch_i
:
IN
std_logic_vector
(
3
DOWNTO
0
);
...
...
@@ -32,7 +32,7 @@ ENTITY top_extphy IS
gmii_rx_dv_i
:
IN
std_logic
;
gmii_rx_er_i
:
IN
std_logic
;
gmii_rxd_i
:
IN
std_logic_vector
(
7
DOWNTO
0
);
sysclk_n_i
:
IN
std_logic
;
--
! 200 MHz xtal clock
sysclk_n_i
:
IN
std_logic
;
--! 200 MHz xtal clock
sysclk_p_i
:
IN
std_logic
;
threshold_discr_n_i
:
IN
std_logic_vector
(
g_NUM_TRIG_INPUTS
-1
DOWNTO
0
);
threshold_discr_p_i
:
IN
std_logic_vector
(
g_NUM_TRIG_INPUTS
-1
DOWNTO
0
);
...
...
@@ -46,9 +46,9 @@ ENTITY top_extphy IS
reset_or_clk_n_o
:
OUT
std_logic_vector
(
g_NUM_DUTS
-1
DOWNTO
0
);
reset_or_clk_p_o
:
OUT
std_logic_vector
(
g_NUM_DUTS
-1
DOWNTO
0
);
triggers_n_o
:
OUT
std_logic_vector
(
g_NUM_DUTS
-1
DOWNTO
0
);
triggers_p_o
:
OUT
std_logic_vector
(
g_NUM_DUTS
-1
DOWNTO
0
);
triggers_p_o
:
OUT
std_logic_vector
(
g_NUM_DUTS
-1
DOWNTO
0
);
--! Trigger lines to DUT
extclk_n_b
:
INOUT
std_logic
;
extclk_p_b
:
INOUT
std_logic
;
-- either external clock in, or a clock being driven out
extclk_p_b
:
INOUT
std_logic
;
--
!
either external clock in, or a clock being driven out
i2c_scl_b
:
INOUT
std_logic
;
i2c_sda_b
:
INOUT
std_logic
);
...
...
@@ -68,15 +68,12 @@ END ENTITY top_extphy ;
------------------------------------------------------------------------------- --
-- VHDL -- VHDL Architecture work.top_extphy.struct
--
--! @brief Top level entity for FMC-based mini-TLU for AIDA
--! @details This VHDL file is generated by HDL-Designer. If you want to change
--! it, use HDL designer.
--! The ports to the top_extphy entity are physical input/output signals
--! to/from the FPGA.
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (
kipper
.phy.bris.ac.uk))
--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (
fortis
.phy.bris.ac.uk))
--
--! @date 1
8:45:17 07/24/13
--! @date 1
6:18:26 01/24/14
--
--! @version v0.1
--
...
...
@@ -98,7 +95,7 @@ END ENTITY top_extphy ;
--------------------------------------------------------------------------------
--
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.
1 (Build 6
)
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.
2b (Build 5
)
--
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
all
;
...
...
@@ -120,7 +117,7 @@ ARCHITECTURE struct OF top_extphy IS
-- Internal signal declarations
SIGNAL
buffer_full_o
:
std_logic
;
--! Goes high when event buffer almost full
SIGNAL
clk_16x_logic
:
std_logic
;
-- 640MHz clock
SIGNAL
clk_4x_logic
:
std_logic
;
--
! normally 160MHz
SIGNAL
clk_4x_logic
:
std_logic
;
--! normally 160MHz
SIGNAL
clk_logic_xtal
:
std_logic
;
-- ! 40MHz clock from onboard xtal
SIGNAL
data_strobe
:
std_logic
;
-- goes high when data ready to load into event buffer
SIGNAL
edge_fall_i
:
std_logic_vector
(
g_NUM_EDGE_INPUTS
-1
DOWNTO
0
);
-- ! High when falling edge
...
...
@@ -129,16 +126,16 @@ ARCHITECTURE struct OF top_extphy IS
SIGNAL
edge_rise_time_i
:
t_triggerTimeArray
(
g_NUM_EDGE_INPUTS
-1
DOWNTO
0
);
-- Array of edge times ( w.r.t. logic_strobe)
SIGNAL
event_data
:
std_logic_vector
(
g_EVENT_DATA_WIDTH
-1
DOWNTO
0
);
SIGNAL
event_number_o
:
std_logic_vector
(
g_IPBUS_WIDTH
-1
DOWNTO
0
);
-- starts at one. Increments for each post_veto_trigger
SIGNAL
ipbr
:
ipb_rbus_array
(
g_NUM_EXT_SLAVES
-1
DOWNTO
0
);
--
! IPBus read signals
SIGNAL
ipbr
:
ipb_rbus_array
(
g_NUM_EXT_SLAVES
-1
DOWNTO
0
);
--! IPBus read signals
SIGNAL
ipbus_clk
:
std_logic
;
SIGNAL
ipbus_clk_i
:
std_logic
;
SIGNAL
ipbus_reset
:
std_logic
;
SIGNAL
ipbus_rst
:
std_logic
;
-- ! IPBus reset to slaves
SIGNAL
ipbw
:
ipb_wbus_array
(
g_NUM_EXT_SLAVES
-1
DOWNTO
0
);
--
! IBus write signals
SIGNAL
ipbw
:
ipb_wbus_array
(
g_NUM_EXT_SLAVES
-1
DOWNTO
0
);
--! IBus write signals
SIGNAL
logic_clocks_reset
:
std_logic
;
-- Goes high to reset counters etc. Sync with clk_4x_logic
SIGNAL
logic_reset
:
std_logic
;
-- Goes high to reset counters etc. Sync with clk_4x_logic
SIGNAL
overall_trigger
:
std_logic
;
-- goes high to load trigger data
SIGNAL
overall_veto
:
std_logic
;
--
! Halts triggers when high
SIGNAL
overall_trigger
:
std_logic
;
--
!
goes high to load trigger data
SIGNAL
overall_veto
:
std_logic
;
--! Halts triggers when high
SIGNAL
s_i2c_scl_enb
:
std_logic
;
SIGNAL
s_i2c_sda_enb
:
std_logic
;
SIGNAL
shutter_cnt_i
:
std_logic_vector
(
g_SPILL_COUNTER_WIDTH
-1
DOWNTO
0
);
...
...
@@ -151,7 +148,7 @@ ARCHITECTURE struct OF top_extphy IS
SIGNAL
trigger_count
:
std_logic_vector
(
g_IPBUS_WIDTH
-1
DOWNTO
0
);
SIGNAL
trigger_times
:
t_triggerTimeArray
(
g_NUM_TRIG_INPUTS
-1
DOWNTO
0
);
-- ! trigger arrival time ( w.r.t. logic_strobe)
SIGNAL
triggers
:
std_logic_vector
(
g_NUM_TRIG_INPUTS
-1
DOWNTO
0
);
SIGNAL
veto_o
:
std_logic
;
-- goes high when one or more DUT are busy
SIGNAL
veto_o
:
std_logic
;
--
!
goes high when one or more DUT are busy
-- Component Declarations
...
...
@@ -368,25 +365,25 @@ BEGIN
-- ModuleWare code(v1.
9
) for instance 'I9' of 'gnd'
-- ModuleWare code(v1.
12
) for instance 'I9' of 'gnd'
logic_clocks_reset
<=
'0'
;
-- ModuleWare code(v1.
9
) for instance 'I10' of 'gnd'
-- ModuleWare code(v1.
12
) for instance 'I10' of 'gnd'
trigger_cnt_i
<=
(
OTHERS
=>
'0'
);
-- ModuleWare code(v1.
9
) for instance 'I11' of 'gnd'
-- ModuleWare code(v1.
12
) for instance 'I11' of 'gnd'
spill_i
<=
'0'
;
-- ModuleWare code(v1.
9
) for instance 'I12' of 'gnd'
-- ModuleWare code(v1.
12
) for instance 'I12' of 'gnd'
spill_cnt_i
<=
(
OTHERS
=>
'0'
);
-- ModuleWare code(v1.
9
) for instance 'I13' of 'gnd'
-- ModuleWare code(v1.
12
) for instance 'I13' of 'gnd'
shutter_i
<=
'0'
;
-- ModuleWare code(v1.
9
) for instance 'I14' of 'gnd'
-- ModuleWare code(v1.
12
) for instance 'I14' of 'gnd'
shutter_cnt_i
<=
(
OTHERS
=>
'0'
);
-- ModuleWare code(v1.
9
) for instance 'I8' of 'sor'
-- ModuleWare code(v1.
12
) for instance 'I8' of 'sor'
overall_veto
<=
buffer_full_o
OR
veto_o
;
-- Instance port mappings.
...
...
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat
View file @
1c3bdc36
No preview for this file type
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_bus_arb.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_emac_hostbus_decl.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_eth_s6_1000basex.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_eth_s6_gmii.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_ipbus_bus_decl.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_ipbus_ctrl.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_ipbus_ctrl_decl.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_ipbus_ctrl_udponly.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_ipbus_fabric.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_ipbus_package.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_mac_arbiter.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_mac_arbiter_decl.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_transactor.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_transactor_rx.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_transactor_sm.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_transactor_tx.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.hdlsidedata/_udp_shim.vhd.rlnk._fpf
View file @
1c3bdc36
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_93
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd
View file @
1c3bdc36
...
...
@@ -267,7 +267,7 @@ libraryRefs [
]
)
version
"30.1"
appVersion
"2012.
1 (Build 6
)"
appVersion
"2012.
2b (Build 5
)"
noEmbeddedEditors
1
model
(
BlockDiag
VExpander
(
VariableExpander
...
...
@@ -314,15 +314,15 @@ value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_des
)
(
vvPair
variable
"date"
value
"0
7/24/13
"
value
"0
1/24/14
"
)
(
vvPair
variable
"day"
value
"
Wed
"
value
"
Fri
"
)
(
vvPair
variable
"day_long"
value
"
Wednes
day"
value
"
Fri
day"
)
(
vvPair
variable
"dd"
...
...
@@ -349,12 +349,28 @@ variable "f_noext"
value
"struct"
)
(
vvPair
variable
"graphical_source_author"
value
"phdgc"
)
(
vvPair
variable
"graphical_source_date"
value
"01/24/14"
)
(
vvPair
variable
"graphical_source_group"
value
"users"
)
(
vvPair
variable
"graphical_source_time"
value
"16:06:33"
)
(
vvPair
variable
"group"
value
"users"
)
(
vvPair
variable
"host"
value
"
kipper
.phy.bris.ac.uk"
value
"
fortis
.phy.bris.ac.uk"
)
(
vvPair
variable
"language"
...
...
@@ -386,7 +402,7 @@ value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
)
(
vvPair
variable
"mm"
value
"0
7
"
value
"0
1
"
)
(
vvPair
variable
"module_name"
...
...
@@ -394,11 +410,11 @@ value "top_extphy"
)
(
vvPair
variable
"month"
value
"J
ul
"
value
"J
an
"
)
(
vvPair
variable
"month_long"
value
"J
ul
y"
value
"J
anuar
y"
)
(
vvPair
variable
"p"
...
...
@@ -466,7 +482,7 @@ value "struct"
)
(
vvPair
variable
"time"
value
"1
8:45:0
6"
value
"1
6:15:5
6"
)
(
vvPair
variable
"unit"
...
...
@@ -478,7 +494,7 @@ value "phdgc"
)
(
vvPair
variable
"version"
value
"2012.
1 (Build 6
)"
value
"2012.
2b (Build 5
)"
)
(
vvPair
variable
"view"
...
...
@@ -486,11 +502,11 @@ value "struct"
)
(
vvPair
variable
"year"
value
"201
3
"
value
"201
4
"
)
(
vvPair
variable
"yy"
value
"1
3
"
value
"1
4
"
)
]
)
...
...
@@ -1714,7 +1730,7 @@ uid 1205,0
decl
(
Decl
n
"clk_4x_logic"
t
"std_logic"
eolc
"! normally 160MHz"
eolc
"
--
! normally 160MHz"
o
33
suid
26
,
0
)
...
...
@@ -1723,8 +1739,8 @@ uid 1206,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,45700,
200
00,46600"
st
"SIGNAL clk_4x_logic : std_logic --
! normally 160MHz
xt
"-10000,45700,
195
00,46600"
st
"SIGNAL clk_4x_logic : std_logic --! normally 160MHz
"
)
)
...
...
@@ -1770,7 +1786,7 @@ decl (Decl
n
"ipbw"
t
"ipb_wbus_array"
b
"(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
eolc
"! IBus write signals"
eolc
"
--
! IBus write signals"
o
47
suid
41
,
0
)
...
...
@@ -1779,8 +1795,8 @@ uid 1589,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,58300,38
5
00,59200"
st
"SIGNAL ipbw : ipb_wbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0) --
! IBus write signals
xt
"-10000,58300,38
0
00,59200"
st
"SIGNAL ipbw : ipb_wbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0) --! IBus write signals
"
)
)
...
...
@@ -1790,7 +1806,7 @@ decl (Decl
n
"ipbr"
t
"ipb_rbus_array"
b
"(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
eolc
"! IPBus read signals"
eolc
"
--
! IPBus read signals"
o
42
suid
42
,
0
)
...
...
@@ -1799,8 +1815,8 @@ uid 1669,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,53800,38
5
00,54700"
st
"SIGNAL ipbr : ipb_rbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0) --
! IPBus read signals
xt
"-10000,53800,38
0
00,54700"
st
"SIGNAL ipbr : ipb_rbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0) --! IPBus read signals
"
)
)
...
...
@@ -1809,7 +1825,7 @@ uid 1808,0
decl
(
Decl
n
"overall_trigger"
t
"std_logic"
eolc
"goes high to load trigger data"
eolc
"
--!
goes high to load trigger data"
o
50
suid
61
,
0
)
...
...
@@ -1818,8 +1834,8 @@ uid 1809,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,61000,2
65
00,61900"
st
"SIGNAL overall_trigger : std_logic -- goes high to load trigger data
xt
"-10000,61000,2
70
00,61900"
st
"SIGNAL overall_trigger : std_logic --
!
goes high to load trigger data
"
)
)
...
...
@@ -1828,7 +1844,7 @@ uid 1810,0
decl
(
Decl
n
"overall_veto"
t
"std_logic"
eolc
"! Halts triggers when high"
eolc
"
--
! Halts triggers when high"
o
51
suid
62
,
0
)
...
...
@@ -1837,8 +1853,8 @@ uid 1811,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,61900,24
5
00,62800"
st
"SIGNAL overall_veto : std_logic --
! Halts triggers when high
xt
"-10000,61900,24
0
00,62800"
st
"SIGNAL overall_veto : std_logic --! Halts triggers when high
"
)
)
...
...
@@ -2902,7 +2918,7 @@ uid 4655,0
decl
(
Decl
n
"extclk_p_b"
t
"std_logic"
eolc
"either external clock in, or a clock being driven out"
eolc
"
--!
either external clock in, or a clock being driven out"
o
28
suid
105
,
0
)
...
...
@@ -2911,8 +2927,8 @@ uid 4656,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,40300,3
45
00,41200"
st
"extclk_p_b : std_logic -- either external clock in, or a clock being driven out
xt
"-10000,40300,3
50
00,41200"
st
"extclk_p_b : std_logic --
!
either external clock in, or a clock being driven out
"
)
)
...
...
@@ -3071,7 +3087,7 @@ m 1
decl
(
Decl
n
"dout"
t
"std_logic"
eolc
"! Halts triggers when high"
eolc
"
--
! Halts triggers when high"
o
51
suid
1
,
0
)
...
...
@@ -3179,7 +3195,7 @@ thePort (LogicalPort
decl
(
Decl
n
"din1"
t
"std_logic"
eolc
"goes high when one or more DUT are busy"
eolc
"
--!
goes high when one or more DUT are busy"
o
64
suid
3
,
0
)
...
...
@@ -3470,7 +3486,7 @@ uid 4982,0
decl
(
Decl
n
"veto_o"
t
"std_logic"
eolc
"goes high when one or more DUT are busy"
eolc
"
--!
goes high when one or more DUT are busy"
o
64
suid
116
,
0
)
...
...
@@ -3479,8 +3495,8 @@ uid 4983,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,73600,31
0
00,74500"
st
"SIGNAL veto_o : std_logic -- goes high when one or more DUT are busy
xt
"-10000,73600,31
5
00,74500"
st
"SIGNAL veto_o : std_logic --
!
goes high when one or more DUT are busy
"
)
)
...
...
@@ -3656,7 +3672,7 @@ uid 6678,0
decl
(
Decl
n
"sysclk_n_i"
t
"std_logic"
eolc
"! 200 MHz xtal clock"
eolc
"
--
! 200 MHz xtal clock"
o
12
suid
130
,
0
)
...
...
@@ -3665,8 +3681,8 @@ uid 6679,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,25900,1
80
00,26800"
st
"sysclk_n_i : std_logic --
! 200 MHz xtal clock
xt
"-10000,25900,1
75
00,26800"
st
"sysclk_n_i : std_logic --! 200 MHz xtal clock
"
)
)
...
...
@@ -3721,6 +3737,7 @@ decl (Decl
n
"triggers_p_o"
t
"std_logic_vector"
b
"(g_NUM_DUTS-1 DOWNTO 0)"
eolc
"--! Trigger lines to DUT"
o
26
suid
131
,
0
)
...
...
@@ -3729,8 +3746,8 @@ uid 6715,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,38500,
210
00,39400"
st
"triggers_p_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
xt
"-10000,38500,
335
00,39400"
st
"triggers_p_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
--! Trigger lines to DUT
"
)
)
...
...
@@ -3786,6 +3803,7 @@ decl (Decl
n
"busy_p_i"
t
"std_logic_vector"
b
"(g_NUM_DUTS-1 DOWNTO 0)"
eolc
"--! Busy lines from DUTs ( active high )"
o
2
suid
132
,
0
)
...
...
@@ -3794,8 +3812,8 @@ uid 6729,0
va
(
VaSet
font
"courier,8,0"
)
xt
"-10000,16900,
210
00,17800"
st
"busy_p_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
xt
"-10000,16900,
415
00,17800"
st
"busy_p_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
--! Busy lines from DUTs ( active high )
"
)
)
...
...
@@ -10599,8 +10617,7 @@ va (VaSet
font
"courier,8,0"
)
xt
"26000,124100,51000,125000"
st
"g_NUM_INPUTS = g_NUM_TRIG_INPUTS ( natural )
"
st
"g_NUM_INPUTS = g_NUM_TRIG_INPUTS ( natural ) "
)
header
""
)
...
...
@@ -15049,8 +15066,8 @@ tm "BdCompilerDirectivesTextMgr"
]
associable
1
)
windowSize
"
735,11,2582,1119
"
viewArea
"
34275,101162,154363,170449
"
windowSize
"
312,57,2159,1165
"
viewArea
"
93186,-22041,281149,86408
"
cachedDiagramExtent
"-13000,0,360964,484495"
pageSetupInfo
(
PageSetupInfo
fileName
"/automount/users/phdgc/hdl_designer_test_print_1.ps"
...
...
@@ -15072,7 +15089,7 @@ bestFit 1
)
hasePageBreakOrigin
1
pageBreakOrigin
"-13000,0"
lastUid
11
628
,
0
lastUid
11
795
,
0
defaultCommentText
(
CommentText
shape
(
Rectangle
layer
0
...
...
@@ -16327,7 +16344,7 @@ m 4
decl
(
Decl
n
"clk_4x_logic"
t
"std_logic"
eolc
"! normally 160MHz"
eolc
"
--
! normally 160MHz"
o
33
suid
26
,
0
)
...
...
@@ -16365,7 +16382,7 @@ decl (Decl
n
"ipbw"
t
"ipb_wbus_array"
b
"(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
eolc
"! IBus write signals"
eolc
"
--
! IBus write signals"
o
47
suid
41
,
0
)
...
...
@@ -16379,7 +16396,7 @@ decl (Decl
n
"ipbr"
t
"ipb_rbus_array"
b
"(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
eolc
"! IPBus read signals"
eolc
"
--
! IPBus read signals"
o
42
suid
42
,
0
)
...
...
@@ -16392,7 +16409,7 @@ m 4
decl
(
Decl
n
"overall_trigger"
t
"std_logic"
eolc
"goes high to load trigger data"
eolc
"
--!
goes high to load trigger data"
o
50
suid
61
,
0
)
...
...
@@ -16405,7 +16422,7 @@ m 4
decl
(
Decl
n
"overall_veto"
t
"std_logic"
eolc
"! Halts triggers when high"
eolc
"
--
! Halts triggers when high"
o
51
suid
62
,
0
)
...
...
@@ -16505,7 +16522,7 @@ m 2
decl
(
Decl
n
"extclk_p_b"
t
"std_logic"
eolc
"either external clock in, or a clock being driven out"
eolc
"
--!
either external clock in, or a clock being driven out"
o
28
suid
105
,
0
)
...
...
@@ -16584,7 +16601,7 @@ m 4
decl
(
Decl
n
"veto_o"
t
"std_logic"
eolc
"goes high when one or more DUT are busy"
eolc
"
--!
goes high when one or more DUT are busy"
o
64
suid
116
,
0
)
...
...
@@ -16644,7 +16661,7 @@ port (LogicalPort
decl
(
Decl
n
"sysclk_n_i"
t
"std_logic"
eolc
"! 200 MHz xtal clock"
eolc
"
--
! 200 MHz xtal clock"
o
12
suid
130
,
0
)
...
...
@@ -16658,6 +16675,7 @@ decl (Decl
n
"triggers_p_o"
t
"std_logic_vector"
b
"(g_NUM_DUTS-1 DOWNTO 0)"
eolc
"--! Trigger lines to DUT"
o
26
suid
131
,
0
)
...
...
@@ -16670,6 +16688,7 @@ decl (Decl
n
"busy_p_i"
t
"std_logic_vector"
b
"(g_NUM_DUTS-1 DOWNTO 0)"
eolc
"--! Busy lines from DUTs ( active high )"
o
2
suid
132
,
0
)
...
...
@@ -17493,7 +17512,7 @@ uid 384,0
*
638
(
MRCItem
litem
&
497
pos
7
dimension
80
dimension
711
uid
385
,
0
)
]
...
...
@@ -17744,7 +17763,7 @@ uid 411,0
*
676
(
MRCItem
litem
&
650
pos
6
dimension
80
dimension
602
uid
412
,
0
)
]
...
...
@@ -17761,5 +17780,5 @@ vaOverrides [
uid
386
,
0
type
1
)
activeModelName
"BlockDiag"
activeModelName
"BlockDiag
:CDM
"
)
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.bak
View file @
1c3bdc36
This diff is collapsed.
Click to expand it.
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb
View file @
1c3bdc36
...
...
@@ -16,7 +16,7 @@ libraryRefs [
]
)
version
"25.1"
appVersion
"2012.
1 (Build 6
)"
appVersion
"2012.
2b (Build 5
)"
model
(
Symbol
commonDM
(
CommonDM
ldm
(
LogicalDM
...
...
@@ -197,6 +197,7 @@ decl (Decl
n
"triggers_p_o"
t
"std_logic_vector"
b
"(g_NUM_DUTS-1 DOWNTO 0)"
eolc
"--! Trigger lines to DUT"
o
26
suid
12
,
0
)
...
...
@@ -209,6 +210,7 @@ decl (Decl
n
"busy_p_i"
t
"std_logic_vector"
b
"(g_NUM_DUTS-1 DOWNTO 0)"
eolc
"--! Busy lines from DUTs ( active high )"
o
2
suid
13
,
0
)
...
...
@@ -245,7 +247,7 @@ port (LogicalPort
decl
(
Decl
n
"sysclk_n_i"
t
"std_logic"
eolc
"! 200 MHz xtal clock"
eolc
"
--
! 200 MHz xtal clock"
o
12
suid
20
,
0
)
...
...
@@ -258,7 +260,7 @@ m 2
decl
(
Decl
n
"extclk_p_b"
t
"std_logic"
eolc
"either external clock in, or a clock being driven out"
eolc
"
--!
either external clock in, or a clock being driven out"
o
28
suid
23
,
0
)
...
...
@@ -1024,15 +1026,15 @@ value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_des
)
(
vvPair
variable
"date"
value
"0
7/24/13
"
value
"0
1/24/14
"
)
(
vvPair
variable
"day"
value
"
Wed
"
value
"
Fri
"
)
(
vvPair
variable
"day_long"
value
"
Wednes
day"
value
"
Fri
day"
)
(
vvPair
variable
"dd"
...
...
@@ -1059,12 +1061,28 @@ variable "f_noext"
value
"symbol"
)
(
vvPair
variable
"graphical_source_author"
value
"phdgc"
)
(
vvPair
variable
"graphical_source_date"
value
"01/24/14"
)
(
vvPair
variable
"graphical_source_group"
value
"users"
)
(
vvPair
variable
"graphical_source_time"
value
"16:06:33"
)
(
vvPair
variable
"group"
value
"users"
)
(
vvPair
variable
"host"
value
"
kipper
.phy.bris.ac.uk"
value
"
fortis
.phy.bris.ac.uk"
)
(
vvPair
variable
"language"
...
...
@@ -1096,7 +1114,7 @@ value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
)
(
vvPair
variable
"mm"
value
"0
7
"
value
"0
1
"
)
(
vvPair
variable
"module_name"
...
...
@@ -1104,11 +1122,11 @@ value "top_extphy"
)
(
vvPair
variable
"month"
value
"J
ul
"
value
"J
an
"
)
(
vvPair
variable
"month_long"
value
"J
ul
y"
value
"J
anuar
y"
)
(
vvPair
variable
"p"
...
...
@@ -1176,7 +1194,7 @@ value "symbol"
)
(
vvPair
variable
"time"
value
"1
8:01:38
"
value
"1
6:06:33
"
)
(
vvPair
variable
"unit"
...
...
@@ -1188,7 +1206,7 @@ value "phdgc"
)
(
vvPair
variable
"version"
value
"2012.
1 (Build 6
)"
value
"2012.
2b (Build 5
)"
)
(
vvPair
variable
"view"
...
...
@@ -1196,11 +1214,11 @@ value "symbol"
)
(
vvPair
variable
"year"
value
"201
3
"
value
"201
4
"
)
(
vvPair
variable
"yy"
value
"1
3
"
value
"1
4
"
)
]
)
...
...
@@ -1754,8 +1772,8 @@ uid 205,0
va
(
VaSet
font
"courier,8,0"
)
xt
"44000,24300,
800
00,25200"
st
"triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
xt
"44000,24300,
925
00,25200"
st
"triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
--! Trigger lines to DUT
"
)
thePort
(
LogicalPort
...
...
@@ -1764,6 +1782,7 @@ decl (Decl
n
"triggers_p_o"
t
"std_logic_vector"
b
"(g_NUM_DUTS-1 DOWNTO 0)"
eolc
"--! Trigger lines to DUT"
o
26
suid
12
,
0
)
...
...
@@ -1801,8 +1820,8 @@ uid 210,0
va
(
VaSet
font
"courier,8,0"
)
xt
"44000,2700,
800
00,3600"
st
"busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
xt
"44000,2700,
1005
00,3600"
st
"busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
--! Busy lines from DUTs ( active high )
"
)
thePort
(
LogicalPort
...
...
@@ -1810,6 +1829,7 @@ decl (Decl
n
"busy_p_i"
t
"std_logic_vector"
b
"(g_NUM_DUTS-1 DOWNTO 0)"
eolc
"--! Busy lines from DUTs ( active high )"
o
2
suid
13
,
0
)
...
...
@@ -1941,15 +1961,15 @@ uid 343,0
va
(
VaSet
font
"courier,8,0"
)
xt
"44000,11700,7
70
00,12600"
st
"sysclk_n_i : IN std_logic ; --
! 200 MHz xtal clock
xt
"44000,11700,7
65
00,12600"
st
"sysclk_n_i : IN std_logic ; --! 200 MHz xtal clock
"
)
thePort
(
LogicalPort
decl
(
Decl
n
"sysclk_n_i"
t
"std_logic"
eolc
"! 200 MHz xtal clock"
eolc
"
--
! 200 MHz xtal clock"
o
12
suid
20
,
0
)
...
...
@@ -1988,8 +2008,8 @@ uid 949,0
va
(
VaSet
font
"courier,8,0"
)
xt
"44000,26100,9
35
00,27000"
st
"extclk_p_b : INOUT std_logic ; -- either external clock in, or a clock being driven out
xt
"44000,26100,9
40
00,27000"
st
"extclk_p_b : INOUT std_logic ; --
!
either external clock in, or a clock being driven out
"
)
thePort
(
LogicalPort
...
...
@@ -1997,7 +2017,7 @@ m 2
decl
(
Decl
n
"extclk_p_b"
t
"std_logic"
eolc
"either external clock in, or a clock being driven out"
eolc
"
--!
either external clock in, or a clock being driven out"
o
28
suid
23
,
0
)
...
...
@@ -3376,7 +3396,7 @@ xt "42000,0,42000,0"
tm
"SyDeclarativeTextMgr"
)
)
lastUid
20
18
,
0
lastUid
20
41
,
0
okToSyncOnLoad
1
OkToSyncGenericsOnLoad
1
activeModelName
"Symbol:CDM"
...
...
src/test/i2c_chipscope_debug.cdc
0 → 100644
View file @
1c3bdc36
#ChipScope Core Inserter Project File Version 3.0
#Tue Jul 23 13:58:01 BST 2013
Project.device.designInputFile=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/top_extphy_cs.ngc
Project.device.designOutputFile=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/top_extphy_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/_ngo
Project.device.useSRL16=true
Project.filter.dimension=7
Project.filter<0>=*i2c*
Project.filter<1>=*sda*
Project.filter<2>=i2c*
Project.filter<3>=ipbus_clk*
Project.filter<4>=*wb_clk*
Project.filter<5>=wb_clk*
Project.filter<6>=
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=8
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=false
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=8
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=0
Project.unit<0>.type=ilapro
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