Generation Settings

Automatic Type conversionoptimal
Component declarationsyes
Configurationsembedded statements
add pragmas
exclude view name

Declarations

Ports:

busy_i            : std_logic_vector(NUM_DUTS-1 DOWNTO 0)
cfd_discr_i       : std_logic_vector(NUM_TRIG_INPUTS-1 DOWNTO 0)
dut_clk           : std_logic_vector(NUM_DUTS-1 DOWNTO 0)
gmii_gtx_clk_o    : std_logic
gmii_rx_clk_i     : std_logic
gmii_rx_dv_i      : std_logic
gmii_rx_er_i      : std_logic
gmii_rxd_i        : std_logic_vector(7 DOWNTO 0)
gmii_tx_en_o      : std_logic
gmii_tx_er_o      : std_logic
gmii_txd_o        : std_logic_vector(7 DOWNTO 0)
i2c_scl_o         : std_logic
i2c_sda_d         : std_logic
leds_o            : std_logic_vector(3 DOWNTO 0)
phy_rstb_o        : std_logic
reset_or_clk_o    : std_logic_vector(NUM_DUTS-1 DOWNTO 0)
threshold_discr_i : std_logic_vector(NUM_TRIG_INPUTS-1 DOWNTO 0)
triggers_o        : std_logic_vector(NUM_DUTS-1 DOWNTO 0)
sysclk_p_i        : std_logic -- ! 200 MHz xtal clock
sysclk_n_i        : std_logic
leds              : std_logic_vector(3 DOWNTO 0)
dip_switch        : std_logic_vector(3 DOWNTO 0)

Diagram Signals:

SIGNAL clk_4x_logic      : std_logic -- ! normally 160MHz
SIGNAL logic_strobe      : std_logic -- ! Pulses high once every 4 cycles of clk_4x_logic
SIGNAL ipb_clk           : std_logic -- ! IPBus clock to slaves
SIGNAL ipb_rst           : std_logic -- ! IPBus reset to slaves
SIGNAL ipbus_clk         : std_logic
SIGNAL ipbus_reset       : std_logic
SIGNAL ipbw              : ipb_wbus_array(NUM_SLAVES-2 DOWNTO 0) -- ! IBus write signals
SIGNAL ipbr              : ipb_rbus_array(NUM_SLAVES-2 DOWNTO 0) -- ! IPBus read signals
SIGNAL dut_veto          : std_logic -- goes high when one or more DUT are busy
SIGNAL overall_trigger   : std_logic -- goes high to load trigger data
SIGNAL overall_veto      : std_logic -- ! Halts triggers when high
SIGNAL triggers          : std_logic_vector(NUM_TRIG_INPUTS-1 DOWNTO 0) -- ! High when trigger from input conector active
SIGNAL trigger_count     : std_logic_vector(IPBUS_WIDTH-1 DOWNTO 0)
SIGNAL data_strobe       : std_logic -- goes high when data ready to load into event buffer
SIGNAL trigger_times     : t_triggerTimeArray(NUM_TRIG_INPUTS-1 DOWNTO 0) -- ! trigger arrival time ( w.r.t. logic_strobe)
SIGNAL event_data        : std_logic_vector(EVENT_DATA_WIDTH-1 DOWNTO 0)

Pre User:


Post User:


Package List

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY work;
USE work.ipbus.all;
USE work.emac_hostbus_decl.all;

USE work.fmcTLU.all;

Bundles