pulse_shaper Project Status (02/23/2011 - 17:42:33)
Project File: mTLU.xise Parser Errors: No Errors
Module Name: pulse_shaper Implementation State: Placed and Routed
Target Device: xc6slx16-2csg324
  • Errors:
 
Product Version:ISE 12.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 18 18,224 1%  
    Number used as Flip Flops 18      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 16 9,112 1%  
    Number used as logic 16 9,112 1%  
        Number using O6 output only 16      
        Number using O5 output only 0      
        Number using O5 and O6 0      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
Number of occupied Slices 22 2,278 1%  
Number of LUT Flip Flop pairs used 26      
    Number with an unused Flip Flop 8 26 30%  
    Number with an unused LUT 10 26 38%  
    Number of fully used LUT-FF pairs 8 26 30%  
    Number of unique control sets 17      
    Number of slice register sites lost
        to control set restrictions
118 18,224 1%  
Number of bonded IOBs 19 232 8%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.21      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Feb 23 10:50:27 2011   
Translation ReportCurrentWed Feb 23 10:50:29 2011   
Map ReportCurrentWed Feb 23 10:50:38 2011   
Place and Route ReportCurrentWed Feb 23 10:50:46 2011   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentWed Feb 23 10:50:51 2011   
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Place and Route Simulation Model ReportCurrentWed Feb 23 17:42:32 2011

Date Generated: 02/23/2011 - 17:42:33