fmc_tlu_sp601 Project Status (02/23/2011 - 16:54:39)
Project File: mTLU.xise Parser Errors: No Errors
Module Name: fmc_tlu_sp601 Implementation State: Placed and Routed
Target Device: xc6slx16-2csg324
  • Errors:
No Errors
Product Version:ISE 12.4
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 4 18,224 1%  
    Number used as Flip Flops 4      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 5 9,112 1%  
    Number used as logic 2 9,112 1%  
        Number using O6 output only 2      
        Number using O5 output only 0      
        Number using O5 and O6 0      
        Number used as ROM 0      
    Number used as Memory 3 2,176 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 3      
            Number using O6 output only 3      
            Number using O5 output only 0      
            Number using O5 and O6 0      
Number of occupied Slices 5 2,278 1%  
Number of LUT Flip Flop pairs used 6      
    Number with an unused Flip Flop 2 6 33%  
    Number with an unused LUT 1 6 16%  
    Number of fully used LUT-FF pairs 3 6 50%  
    Number of unique control sets 4      
    Number of slice register sites lost
        to control set restrictions
25 18,224 1%  
Number of bonded IOBs 8 232 3%  
    Number of LOCed IOBs 2 8 25%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 0 16 0%  
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 1.42      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Feb 24 16:17:31 2011000
Translation ReportCurrentFri Feb 25 15:51:14 2011000
Map ReportCurrentFri Feb 25 15:51:24 2011008 Infos (0 new)
Place and Route ReportCurrentFri Feb 25 15:51:33 2011000
Power Report     
Post-PAR Static Timing ReportCurrentFri Feb 25 15:51:38 2011002 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Place and Route Simulation Model ReportOut of DateFri Feb 25 16:05:26 2011

Date Generated: 02/25/2011 - 17:45:42