-- Coregen VHDL wrapper file modified by HDL Designer

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: P.40xd
--  \   \         Application: netgen
--  /   /         Filename: soft_emac_gmii_4_5.vhd
-- /___/   /\     Timestamp: Tue Nov 13 11:30:31 2012
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -w -sim -ofmt vhdl ./tmp/_cg/soft_emac_gmii_4_5.ngc ./tmp/_cg/soft_emac_gmii_4_5.vhd 
-- Device	: 6slx16csg324-2
-- Input file	: ./tmp/_cg/soft_emac_gmii_4_5.ngc
-- Output file	: ./tmp/_cg/soft_emac_gmii_4_5.vhd
-- # of Entities	: 1
-- Design Name	: soft_emac_gmii_4_5
-- Xilinx	: /automount/software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Command Line Tools User Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------


-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity soft_emac_gmii_4_5 is
  port (
    emacclientrxdvld : out STD_LOGIC; 
    hostmiimsel : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    emacphymdtri : out STD_LOGIC; 
    emacclientrxbadframe : out STD_LOGIC; 
    emacphymdout : out STD_LOGIC; 
    emacclienttxack : out STD_LOGIC; 
    hostmiimrdy : out STD_LOGIC; 
    emacclientrxstatsvld : out STD_LOGIC; 
    speedis10100 : out STD_LOGIC; 
    hostreq : in STD_LOGIC := 'X'; 
    emacphytxer : out STD_LOGIC; 
    phyemacmdin : in STD_LOGIC := 'X'; 
    emacclientrxgoodframe : out STD_LOGIC; 
    clientemacpausereq : in STD_LOGIC := 'X'; 
    corehassgmii : in STD_LOGIC := 'X'; 
    clientemactxdvld : in STD_LOGIC := 'X'; 
    rxgmiimiiclk : in STD_LOGIC := 'X'; 
    emacphytxen : out STD_LOGIC; 
    emacphymclkout : out STD_LOGIC; 
    phyemacrxdv : in STD_LOGIC := 'X'; 
    txgmiimiiclk : in STD_LOGIC := 'X'; 
    phyemacrxer : in STD_LOGIC := 'X'; 
    hostclk : in STD_LOGIC := 'X'; 
    clientemactxunderrun : in STD_LOGIC := 'X'; 
    emacclienttxstatsvld : out STD_LOGIC; 
    speedis100 : out STD_LOGIC; 
    emacclientrxstats : out STD_LOGIC_VECTOR ( 27 downto 0 ); 
    hostopcode : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    clientemacpauseval : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    hostrddata : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    clientemactxifgdelay : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    clientemactxd : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    hostaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    emacclienttxstats : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    phyemacrxd : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    hostwrdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    emacphytxd : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    emacclientrxd : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end soft_emac_gmii_4_5;

architecture STRUCTURE of soft_emac_gmii_4_5 is

-- hds translate_off

  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal NlwRenamedSig_OI_emacclienttxstats_31_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_emacclienttxstats_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_emacclienttxstatsvld : STD_LOGIC; 
  signal NlwRenamedSig_OI_hostmiimrdy : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1311_2053 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift7_2052 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift6_2051 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift5_2050 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift4_2049 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift3_2048 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift2_2047 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift1_2046 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_131_2045 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_2044 : STD_LOGIC; 
  signal BU2_N324 : STD_LOGIC; 
  signal BU2_N323 : STD_LOGIC; 
  signal BU2_N322 : STD_LOGIC; 
  signal BU2_N321 : STD_LOGIC; 
  signal BU2_N320 : STD_LOGIC; 
  signal BU2_N319 : STD_LOGIC; 
  signal BU2_N318 : STD_LOGIC; 
  signal BU2_N317 : STD_LOGIC; 
  signal BU2_N316 : STD_LOGIC; 
  signal BU2_N315 : STD_LOGIC; 
  signal BU2_N314 : STD_LOGIC; 
  signal BU2_N313 : STD_LOGIC; 
  signal BU2_N312 : STD_LOGIC; 
  signal BU2_N311 : STD_LOGIC; 
  signal BU2_N309 : STD_LOGIC; 
  signal BU2_N307 : STD_LOGIC; 
  signal BU2_N305 : STD_LOGIC; 
  signal BU2_N303 : STD_LOGIC; 
  signal BU2_N301 : STD_LOGIC; 
  signal BU2_N299 : STD_LOGIC; 
  signal BU2_N297 : STD_LOGIC; 
  signal BU2_N295 : STD_LOGIC; 
  signal BU2_N293 : STD_LOGIC; 
  signal BU2_N291 : STD_LOGIC; 
  signal BU2_N289 : STD_LOGIC; 
  signal BU2_N287 : STD_LOGIC; 
  signal BU2_N285 : STD_LOGIC; 
  signal BU2_N283 : STD_LOGIC; 
  signal BU2_N281 : STD_LOGIC; 
  signal BU2_N279 : STD_LOGIC; 
  signal BU2_N277 : STD_LOGIC; 
  signal BU2_N275 : STD_LOGIC; 
  signal BU2_N273 : STD_LOGIC; 
  signal BU2_N271 : STD_LOGIC; 
  signal BU2_N269 : STD_LOGIC; 
  signal BU2_N267 : STD_LOGIC; 
  signal BU2_N265 : STD_LOGIC; 
  signal BU2_N261 : STD_LOGIC; 
  signal BU2_N259 : STD_LOGIC; 
  signal BU2_N257 : STD_LOGIC; 
  signal BU2_N255 : STD_LOGIC; 
  signal BU2_N253 : STD_LOGIC; 
  signal BU2_N247 : STD_LOGIC; 
  signal BU2_N245 : STD_LOGIC; 
  signal BU2_N244 : STD_LOGIC; 
  signal BU2_N243 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_rstpot_1981 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_rstpot_1980 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_rstpot_1979 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_rstpot_1978 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_1977 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_rstpot_1976 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_rstpot_1975 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_rstpot_1974 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_rstpot_1973 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_rstpot_1972 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_rstpot_1971 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_rstpot_1970 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_rstpot_1969 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_rstpot_1968 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_rstpot_1967 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_1966 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_rstpot_1965 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_GND_30_o_MUX_491_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_1963 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_GND_27_o_MUX_266_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH_1961 : STD_LOGIC; 
  signal BU2_N236 : STD_LOGIC; 
  signal BU2_N237 : STD_LOGIC; 
  signal BU2_N234 : STD_LOGIC; 
  signal BU2_N225 : STD_LOGIC; 
  signal BU2_N224 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_1955 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0189_inv : STD_LOGIC; 
  signal BU2_N219 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN_GND_27_o_MUX_441_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1951 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv2 : STD_LOGIC; 
  signal BU2_N217 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0088 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_RXD_REG_7_INV_427_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0324_inv11 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable4 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_rstpot_1944 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_GND_27_o_MUX_270_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_rstpot_1942 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_1941 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_rstpot_1938 : STD_LOGIC; 
  signal BU2_N215 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_rstpot_1936 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_1935 : STD_LOGIC; 
  signal BU2_N213 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0112_inv : STD_LOGIC; 
  signal BU2_N211 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0080_inv : STD_LOGIC; 
  signal BU2_N209 : STD_LOGIC; 
  signal BU2_N207 : STD_LOGIC; 
  signal BU2_N205 : STD_LOGIC; 
  signal BU2_N203 : STD_LOGIC; 
  signal BU2_N201 : STD_LOGIC; 
  signal BU2_N199 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_1924 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_glue_ce_1923 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_n0018_inv : STD_LOGIC; 
  signal BU2_N195 : STD_LOGIC; 
  signal BU2_N193 : STD_LOGIC; 
  signal BU2_N192 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_rstpot1_1918 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_rstpot1_1917 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_rstpot1_1916 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_rstpot1_1915 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_rstpot1_1914 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_rstpot1_1913 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1_1912 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_rstpot1_1911 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot1_1910 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_rstpot1_1909 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot1_1908 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_rstpot1_1907 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_rstpot1_1906 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_rstpot1_1905 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_rstpot1_1904 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_rstpot1_1903 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_rstpot1_1902 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_rstpot1_1901 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot1_1900 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_rstpot1_1899 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_1898 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_rstpot1_1897 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2_rstpot_1896 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_rstpot_1895 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_rstpot_1894 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_rstpot_1893 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot_1892 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG_rstpot_1891 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_14_rstpot_1890 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_15_rstpot_1889 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_13_rstpot_1888 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_12_rstpot_1887 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_11_rstpot_1886 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_10_rstpot_1885 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_7_rstpot_1884 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_9_rstpot_1883 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_8_rstpot_1882 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_6_rstpot_1881 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_5_rstpot_1880 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_4_rstpot_1879 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_3_rstpot_1878 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_0_rstpot_1877 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_2_rstpot_1876 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_1_rstpot_1875 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_rstpot_1874 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_rstpot_1873 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_rstpot_1872 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_GND_27_o_MUX_255_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_rstpot_1870 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_rstpot_1869 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0904_inv_1868 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_glue_set_1867 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_glue_set_1866 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set_1865 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1864 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_glue_set_1863 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_1862 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_glue_set_1861 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcast_match_1860 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcast_match_glue_set_1859 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_1858 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_glue_set_1857 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_glue_rst_1856 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28_glue_set_1855 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28_glue_set_1854 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_INT_glue_set_1853 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT_1852 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT_glue_set_1851 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0_glue_set_1850 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1_glue_set_1849 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2_glue_set_1848 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3_glue_set_1847 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4_glue_set_1846 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5_glue_set_1845 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6_glue_set_1844 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7_glue_set_1843 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8_glue_set_1842 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9_glue_set_1841 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10_glue_set_1840 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11_glue_set_1839 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12_glue_set_1838 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13_glue_set_1837 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_glue_set_1836 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_glue_set_1835 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_glue_set_1834 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_glue_set_1833 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_glue_set_1832 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0_glue_set_1831 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o2_1830 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o1_1829 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o2_1828 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o1_1827 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1826 : STD_LOGIC; 
  signal BU2_N190 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o113_1824 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o112_1823 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o111_1822 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o11 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable6_1820 : STD_LOGIC; 
  signal BU2_N188 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0412_inv1_1818 : STD_LOGIC; 
  signal BU2_N186 : STD_LOGIC; 
  signal BU2_N184 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1815 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1814 : STD_LOGIC; 
  signal BU2_N182 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable22_1812 : STD_LOGIC; 
  signal BU2_N180 : STD_LOGIC; 
  signal BU2_N174 : STD_LOGIC; 
  signal BU2_N172 : STD_LOGIC; 
  signal BU2_N168 : STD_LOGIC; 
  signal BU2_N160 : STD_LOGIC; 
  signal BU2_N154 : STD_LOGIC; 
  signal BU2_N152 : STD_LOGIC; 
  signal BU2_N150 : STD_LOGIC; 
  signal BU2_N148 : STD_LOGIC; 
  signal BU2_N146 : STD_LOGIC; 
  signal BU2_N144 : STD_LOGIC; 
  signal BU2_N142 : STD_LOGIC; 
  signal BU2_N138 : STD_LOGIC; 
  signal BU2_N136 : STD_LOGIC; 
  signal BU2_N132 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT281_1796 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT28 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT291_1794 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT29 : STD_LOGIC; 
  signal BU2_N126 : STD_LOGIC; 
  signal BU2_N124 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb81_1789 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb8 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb81_1786 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb8 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0108_inv_1784 : STD_LOGIC; 
  signal BU2_N122 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0072_1782 : STD_LOGIC; 
  signal BU2_N120 : STD_LOGIC; 
  signal BU2_N118 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1011_1779 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1010_1778 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING109_1777 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING108_1776 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING107_1775 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING106_1774 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING105_1773 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING104_1772 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING103_1771 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING102_1770 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING101_1769 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING10 : STD_LOGIC; 
  signal BU2_N116 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_9_1766 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_8_1765 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_7_1764 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_6_1763 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT29 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_5_1761 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT28 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_4_1759 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT27 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_3_1757 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT26 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT251_1755 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT25 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT24 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_2_1752 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT23 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT22 : STD_LOGIC; 
  signal BU2_N104 : STD_LOGIC; 
  signal BU2_N102 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_1_1747 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT12 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_15_1745 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_14_1744 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_13_1743 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_12_1742 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_11_1741 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_10_1740 : STD_LOGIC; 
  signal BU2_N90 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_0_1738 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61_1735 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o6 : STD_LOGIC; 
  signal BU2_N88 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT291_1732 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT29 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT281_1730 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT28 : STD_LOGIC; 
  signal BU2_N74 : STD_LOGIC; 
  signal BU2_N72 : STD_LOGIC; 
  signal BU2_N68 : STD_LOGIC; 
  signal BU2_N66 : STD_LOGIC; 
  signal BU2_N62 : STD_LOGIC; 
  signal BU2_N60 : STD_LOGIC; 
  signal BU2_N56 : STD_LOGIC; 
  signal BU2_N52 : STD_LOGIC; 
  signal BU2_N48 : STD_LOGIC; 
  signal BU2_N46 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH_GND_27_o_MUX_428_o : STD_LOGIC; 
  signal BU2_N44 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH_GND_27_o_MUX_424_o : STD_LOGIC; 
  signal BU2_N42 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH_GND_27_o_MUX_426_o : STD_LOGIC; 
  signal BU2_N40 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH_GND_27_o_MUX_430_o : STD_LOGIC; 
  signal BU2_N38 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_GND_27_o_MUX_432_o_1710 : STD_LOGIC; 
  signal BU2_N36 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1708 : STD_LOGIC; 
  signal BU2_N34 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12_1706 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11_1705 : STD_LOGIC; 
  signal BU2_N32 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv23_1703 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv21_1702 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0848_inv1_1701 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0856_inv_1700 : STD_LOGIC; 
  signal BU2_N22 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0834_inv_1698 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_1697 : STD_LOGIC; 
  signal BU2_N20 : STD_LOGIC; 
  signal BU2_N18 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o2_1693 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o1_1692 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_1_1690 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv2_1688 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0141_1687 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX : STD_LOGIC; 
  signal BU2_N16 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT161 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT163_1683 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT162_1682 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT51 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT53_1680 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT52_1679 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT192_1678 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT191_1677 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT19 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT32 : STD_LOGIC; 
  signal BU2_N14 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In13_1673 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In12_1672 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1671 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In11_1670 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT103 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT101_1668 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT10 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT121_1666 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT122_1665 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT12 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT141_1663 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT142_1662 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT14 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT71_1660 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT72_1659 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT7 : STD_LOGIC; 
  signal BU2_N10 : STD_LOGIC; 
  signal BU2_N8 : STD_LOGIC; 
  signal BU2_N6 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008141 : STD_LOGIC; 
  signal BU2_N2 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0100_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_GND_30_o_MUX_493_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_GND_30_o_MUX_507_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_1649 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_GND_30_o_MUX_509_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_1647 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_CRC_ENGINE_ERR_OR_208_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1645 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o21 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1643 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_CONTROL_MATCH_AND_335_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1640 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1639 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0305 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0298 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0290 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0292 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0314 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0311 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0294 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG_1628 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_INT_RD_DATA291 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_STATE_VAR_AND_456_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_STATE_VAR_1625 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONFIG_RD_WR : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0294 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0311 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0314 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0290 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0298 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0305 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0776_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0998_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_GND_27_o_MUX_229_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_GND_27_o_MUX_231_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_GND_27_o_MUX_233_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_GND_27_o_MUX_237_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_GND_27_o_MUX_343_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_GND_27_o_MUX_399_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH_GND_27_o_MUX_434_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_GND_27_o_MUX_443_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_GND_27_o_MUX_408_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID_1602 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1601 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_GND_27_o_MUX_341_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_GND_27_o_MUX_347_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_GND_27_o_MUX_349_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_GND_27_o_MUX_401_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID_GND_27_o_MUX_403_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_1595 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL_GND_27_o_MUX_439_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_1592 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_1591 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_1590 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH_1589 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH_1588 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH_1587 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH_1586 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_FRAME_GOOD_GND_27_o_MUX_286_o11 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv1_1582 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_1581 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_1580 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_GND_27_o_MUX_383_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1578 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_FCS_GND_27_o_MUX_278_o11 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_GND_27_o_MUX_298_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0888_inv11 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_1574 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_1573 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_1572 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_GND_27_o_MUX_345_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0912_inv1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0826_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0818_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_1559 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_7_11 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_GND_27_o_MUX_304_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_GND_27_o_MUX_263_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0084_inv1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In11_1548 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_Mux_26_o13 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1546 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1545 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1544 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_1542 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_1541 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R3_PWR_16_o_MUX_15_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R3_1539 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R3_PWR_16_o_MUX_15_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R3_1537 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R3_PWR_16_o_MUX_15_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R3_1535 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_1534 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_1533 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_1507 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GND_37_o_DATA_LENGTH_CNT_7_equal_1_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1505 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_EXCEEDED_MIN_LEN_OR_192_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1503 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1500 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_EXTENSION_FIELD_OR_203_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1498 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_SFD_FLAG_AND_339_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_CRC_ENGINE_ERR_OR_213_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1495 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO_1494 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_300_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1492 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_RXD_7_equal_10_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ONE_1490 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o_1489 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH_1488 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PWR_38_o_RXD_7_equal_16_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_1485 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_183_o_1484 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID_1483 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_DATA_WITH_FCS_MUX_702_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_1481 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_CRC_COMPUTE_OR_168_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_1477 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_1476 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_1475 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_1474 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_INT_1473 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_38_o_AND_331_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_1_GND_36_o_MUX_732_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_3_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_4_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_6_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_7_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_8_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_9_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_10_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_0_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_1_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_1_rt_1412 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_2_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_2_rt_1409 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_3_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_3_rt_1406 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_4_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_4_rt_1403 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_5_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_5_rt_1400 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_6_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_6_rt_1397 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_7_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_7_rt_1394 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_8_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_8_rt_1391 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_9_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_9_rt_1388 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_10_1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_10_rt_1385 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_11_rt_1382 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_12_rt_1379 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_13_rt_1376 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_14_rt_1373 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_lut_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_rt_1368 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_0_Q_1367 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_rt_1365 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_Q_1364 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_rt_1362 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_Q_1361 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_rt_1359 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_Q_1358 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_rt_1356 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_Q_1355 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_rt_1353 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_Q_1352 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_rt_1350 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_Q_1349 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_rt_1347 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_Q_1346 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_9_rt_1344 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_Q_1343 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_10_rt_1341 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_9_Q_1340 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_DV_REG6_MUX_599_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1337 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_ERR_REG5_END_EXT_AND_258_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1335 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DEST_ADDRESS_FIELD_AND_269_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_LEN_FIELD_AND_275_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1331 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DAT_FIELD_AND_278_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_END_DATA_OR_156_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PWR_37_o_FIELD_CONTROL_5_MUX_622_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_GND_35_o_FIELD_CONTROL_0_MUX_621_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_1_GND_35_o_MUX_626_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_2_GND_35_o_MUX_625_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_3_GND_35_o_MUX_624_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_4_GND_35_o_MUX_623_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VLAN_ENABLE_HELD_1307 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1306 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28_1305 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD_1304 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PAUSE_LT_CHECK_HELD_1303 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_CRC_MODE_HELD_1302 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1301 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_n0205_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RX_DV : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RX_ER : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_FLAG_1297 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_IFG_FLAG_1296 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_34_o_RX_ERR_REG6_AND_247_o_1294 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_EXTENSION_FLAG_1293 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GND_32_o_RX_DV_REG6_AND_249_o_1292 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FALSE_CARR_FLAG_1291 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG_1290 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1288 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1287 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1278 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_1260 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1259 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1258 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ERR_1257 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_FRAME_1256 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_1241 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_OUT_OF_BOUNDS_ERR_1240 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1239 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1238 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_1237 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BROADCASTADDRESSMATCH_DELAY : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG2_1218 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1_1216 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_31_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_30_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_29_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_28_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_27_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_26_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_25_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_24_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_23_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_22_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_21_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_20_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_19_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_18_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_17_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_16_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_15_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_14_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_13_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_12_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_11_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_10_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_9_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_8_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_7_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_6_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_4_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_3_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_3_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_4_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_6_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_7_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_8_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_9_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_10_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_11_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_12_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_13_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_14_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_15_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_16_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_17_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_18_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_19_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_20_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_21_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_22_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_23_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_24_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_25_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_26_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_27_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_28_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_29_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_30_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_31_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_32_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_33_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_34_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_35_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_36_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_37_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_38_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_39_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_40_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_41_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_42_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_43_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_44_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_45_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_46_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_47_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcastaddressmatch_1043 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcastaddressmatch_GND_44_o_MUX_1179_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pauseaddressmatch_1041 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pauseaddressmatch_GND_44_o_MUX_1187_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2_GND_44_o_mux_4_OUT_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2_GND_44_o_mux_4_OUT_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2_GND_44_o_mux_4_OUT_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0085_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_specialpauseaddressmatch_1032 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_specialpauseaddressmatch_GND_44_o_MUX_1171_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0091_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_TRISTATE_COMB_1027 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG1_1025 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_OUT_RISING : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_404_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT2 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT3 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT4 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT5_1011 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_408_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_FC_CE_1_INT_W_R_AND_444_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_29_1007 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_30_1006 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_27_1005 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_25_1004 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_24_1003 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_29_1000 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_27_999 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_TX_OUT_31_OR_226_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_TX_CE_1_INT_W_R_AND_443_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_3_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_4_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_6_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT2 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT3 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT4 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT5 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_DV_REG1_907 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_ER_REG1_898 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_3_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_4_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_6_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_7_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_8_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_9_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_10_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_11_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_12_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_13_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_14_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_15_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_16_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_17_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_18_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_19_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_20_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_21_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_22_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_23_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_24_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_25_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_26_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_27_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_28_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_29_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_30_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_31_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_818 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_INV_104_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_3_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_788 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_3_1_782 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_4_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_6_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_7_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_0_1_772 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_2_1_770 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_3_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_4_1_768 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable14 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_6_1_765 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_7_1_764 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_763 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_BROADCAST : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_761 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL_760 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN_745 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT2 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT2 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT5 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT3 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT4 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT6 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT7 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt_623 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt_620 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt_617 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt_614 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt_611 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt_608 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt_605 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt_602 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt_599 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt_596 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt_593 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt_590 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt_587 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_rt_584 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRC_MODE_582 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_CRC_MODE_INV_47_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_HALF_DUPLEX_580 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_VLAN_ENABLE_579 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_VLAN_ENABLE_OUT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_JUMBO_ENABLE_577 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_30_576 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE_575 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28_574 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_IFG_DEL_EN_573 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_25_572 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_Reset_OR_DriverANDClockEnable : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_570 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_GND_26_o_MUX_206_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_REG_566 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_565 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT2 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT3 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT4 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT5 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT6 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT7 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT8 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT9 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT10 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT11 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT12 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT13 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT14 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT15 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_val : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_in : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_GOOD_FRAME_IN3_OR_37_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_REQ_LOCAL : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_461 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN3_460 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2_459 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_0_393 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_1_391 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_2_389 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_3_387 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_4_385 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_5_383 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_6_381 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_7_379 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_8_377 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_9_375 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_10_373 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_11_371 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_12_369 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_13_367 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_14_365 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_15_363 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_343 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_REG_342 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_INV_8_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_340 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_Mux_26_o : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_3_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_4_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_6_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_7_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT2 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT3 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0147 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT4 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0174_inv_311 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_310 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_308 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_COMB : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_ACK_IN : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_0_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_1_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_2_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_3_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_4_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_5_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_6_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_7_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_8_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_9_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_10_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_11_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_12_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_13_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_14_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_15_Q : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT1_258 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT2 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT3 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT4_252 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv_251 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_234 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT_233 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_COMB : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_COMB : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_HALF_DUPLEX_SYNC : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_SYNC : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_in : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_HALF_DUPLEX_SYNC : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_SYNC : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync1 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_in : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R2_218 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R1_217 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R2_215 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R1_214 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R2_212 : STD_LOGIC; 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R1_211 : STD_LOGIC; 
  signal NLW_BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_Q15_UNCONNECTED : STD_LOGIC; 
  signal emacphytxd_2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal phyemacrxd_3 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal clientemactxd_4 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal clientemactxifgdelay_5 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal clientemacpauseval_6 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal emacclientrxd_7 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSig_OI_emacclientrxstats : STD_LOGIC_VECTOR ( 27 downto 26 ); 
  signal emacclientrxstats_8 : STD_LOGIC_VECTOR ( 25 downto 0 ); 
  signal hostopcode_9 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal hostaddr_10 : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal hostwrdata_11 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal hostrddata_12 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy : STD_LOGIC_VECTOR ( 13 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH : STD_LOGIC_VECTOR ( 13 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift : STD_LOGIC_VECTOR ( 47 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_OP_INT : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0 : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED : STD_LOGIC_VECTOR ( 7 downto 2 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1 : STD_LOGIC_VECTOR ( 13 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy : STD_LOGIC_VECTOR ( 13 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD : STD_LOGIC_VECTOR ( 47 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA : STD_LOGIC_VECTOR ( 7 downto 0 ); 

-- hds translate_on

begin

-- hds translate_off

  emacclientrxstats(27) <= NlwRenamedSig_OI_emacclientrxstats(27);
  emacclientrxstats(26) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclientrxstats(25) <= emacclientrxstats_8(25);
  emacclientrxstats(24) <= emacclientrxstats_8(24);
  emacclientrxstats(23) <= emacclientrxstats_8(23);
  emacclientrxstats(22) <= emacclientrxstats_8(22);
  emacclientrxstats(21) <= emacclientrxstats_8(21);
  emacclientrxstats(20) <= emacclientrxstats_8(20);
  emacclientrxstats(19) <= emacclientrxstats_8(19);
  emacclientrxstats(18) <= emacclientrxstats_8(18);
  emacclientrxstats(17) <= emacclientrxstats_8(17);
  emacclientrxstats(16) <= emacclientrxstats_8(16);
  emacclientrxstats(15) <= emacclientrxstats_8(15);
  emacclientrxstats(14) <= emacclientrxstats_8(14);
  emacclientrxstats(13) <= emacclientrxstats_8(13);
  emacclientrxstats(12) <= emacclientrxstats_8(12);
  emacclientrxstats(11) <= emacclientrxstats_8(11);
  emacclientrxstats(10) <= emacclientrxstats_8(10);
  emacclientrxstats(9) <= emacclientrxstats_8(9);
  emacclientrxstats(8) <= emacclientrxstats_8(8);
  emacclientrxstats(7) <= emacclientrxstats_8(7);
  emacclientrxstats(6) <= emacclientrxstats_8(6);
  emacclientrxstats(5) <= emacclientrxstats_8(5);
  emacclientrxstats(4) <= emacclientrxstats_8(4);
  emacclientrxstats(3) <= emacclientrxstats_8(3);
  emacclientrxstats(2) <= emacclientrxstats_8(2);
  emacclientrxstats(1) <= emacclientrxstats_8(1);
  emacclientrxstats(0) <= emacclientrxstats_8(0);
  hostopcode_9(1) <= hostopcode(1);
  hostopcode_9(0) <= hostopcode(0);
  clientemacpauseval_6(15) <= clientemacpauseval(15);
  clientemacpauseval_6(14) <= clientemacpauseval(14);
  clientemacpauseval_6(13) <= clientemacpauseval(13);
  clientemacpauseval_6(12) <= clientemacpauseval(12);
  clientemacpauseval_6(11) <= clientemacpauseval(11);
  clientemacpauseval_6(10) <= clientemacpauseval(10);
  clientemacpauseval_6(9) <= clientemacpauseval(9);
  clientemacpauseval_6(8) <= clientemacpauseval(8);
  clientemacpauseval_6(7) <= clientemacpauseval(7);
  clientemacpauseval_6(6) <= clientemacpauseval(6);
  clientemacpauseval_6(5) <= clientemacpauseval(5);
  clientemacpauseval_6(4) <= clientemacpauseval(4);
  clientemacpauseval_6(3) <= clientemacpauseval(3);
  clientemacpauseval_6(2) <= clientemacpauseval(2);
  clientemacpauseval_6(1) <= clientemacpauseval(1);
  clientemacpauseval_6(0) <= clientemacpauseval(0);
  hostrddata(31) <= hostrddata_12(31);
  hostrddata(30) <= hostrddata_12(30);
  hostrddata(29) <= hostrddata_12(29);
  hostrddata(28) <= hostrddata_12(28);
  hostrddata(27) <= hostrddata_12(27);
  hostrddata(26) <= hostrddata_12(26);
  hostrddata(25) <= hostrddata_12(25);
  hostrddata(24) <= hostrddata_12(24);
  hostrddata(23) <= hostrddata_12(23);
  hostrddata(22) <= hostrddata_12(22);
  hostrddata(21) <= hostrddata_12(21);
  hostrddata(20) <= hostrddata_12(20);
  hostrddata(19) <= hostrddata_12(19);
  hostrddata(18) <= hostrddata_12(18);
  hostrddata(17) <= hostrddata_12(17);
  hostrddata(16) <= hostrddata_12(16);
  hostrddata(15) <= hostrddata_12(15);
  hostrddata(14) <= hostrddata_12(14);
  hostrddata(13) <= hostrddata_12(13);
  hostrddata(12) <= hostrddata_12(12);
  hostrddata(11) <= hostrddata_12(11);
  hostrddata(10) <= hostrddata_12(10);
  hostrddata(9) <= hostrddata_12(9);
  hostrddata(8) <= hostrddata_12(8);
  hostrddata(7) <= hostrddata_12(7);
  hostrddata(6) <= hostrddata_12(6);
  hostrddata(5) <= hostrddata_12(5);
  hostrddata(4) <= hostrddata_12(4);
  hostrddata(3) <= hostrddata_12(3);
  hostrddata(2) <= hostrddata_12(2);
  hostrddata(1) <= hostrddata_12(1);
  hostrddata(0) <= hostrddata_12(0);
  clientemactxifgdelay_5(7) <= clientemactxifgdelay(7);
  clientemactxifgdelay_5(6) <= clientemactxifgdelay(6);
  clientemactxifgdelay_5(5) <= clientemactxifgdelay(5);
  clientemactxifgdelay_5(4) <= clientemactxifgdelay(4);
  clientemactxifgdelay_5(3) <= clientemactxifgdelay(3);
  clientemactxifgdelay_5(2) <= clientemactxifgdelay(2);
  clientemactxifgdelay_5(1) <= clientemactxifgdelay(1);
  clientemactxifgdelay_5(0) <= clientemactxifgdelay(0);
  clientemactxd_4(7) <= clientemactxd(7);
  clientemactxd_4(6) <= clientemactxd(6);
  clientemactxd_4(5) <= clientemactxd(5);
  clientemactxd_4(4) <= clientemactxd(4);
  clientemactxd_4(3) <= clientemactxd(3);
  clientemactxd_4(2) <= clientemactxd(2);
  clientemactxd_4(1) <= clientemactxd(1);
  clientemactxd_4(0) <= clientemactxd(0);
  hostmiimrdy <= NlwRenamedSig_OI_hostmiimrdy;
  speedis10100 <= NlwRenamedSig_OI_emacclientrxstats(26);
  hostaddr_10(9) <= hostaddr(9);
  hostaddr_10(8) <= hostaddr(8);
  hostaddr_10(7) <= hostaddr(7);
  hostaddr_10(6) <= hostaddr(6);
  hostaddr_10(5) <= hostaddr(5);
  hostaddr_10(4) <= hostaddr(4);
  hostaddr_10(3) <= hostaddr(3);
  hostaddr_10(2) <= hostaddr(2);
  hostaddr_10(1) <= hostaddr(1);
  hostaddr_10(0) <= hostaddr(0);
  emacclienttxstats(31) <= NlwRenamedSig_OI_emacclienttxstats_31_Q;
  emacclienttxstats(29) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(28) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(27) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(26) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(25) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(24) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(23) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(22) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(21) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(20) <= NlwRenamedSig_OI_emacclientrxstats(26);
  emacclienttxstats(2) <= NlwRenamedSig_OI_emacclienttxstats_2_Q;
  phyemacrxd_3(7) <= phyemacrxd(7);
  phyemacrxd_3(6) <= phyemacrxd(6);
  phyemacrxd_3(5) <= phyemacrxd(5);
  phyemacrxd_3(4) <= phyemacrxd(4);
  phyemacrxd_3(3) <= phyemacrxd(3);
  phyemacrxd_3(2) <= phyemacrxd(2);
  phyemacrxd_3(1) <= phyemacrxd(1);
  phyemacrxd_3(0) <= phyemacrxd(0);
  hostwrdata_11(31) <= hostwrdata(31);
  hostwrdata_11(30) <= hostwrdata(30);
  hostwrdata_11(29) <= hostwrdata(29);
  hostwrdata_11(28) <= hostwrdata(28);
  hostwrdata_11(27) <= hostwrdata(27);
  hostwrdata_11(26) <= hostwrdata(26);
  hostwrdata_11(25) <= hostwrdata(25);
  hostwrdata_11(24) <= hostwrdata(24);
  hostwrdata_11(23) <= hostwrdata(23);
  hostwrdata_11(22) <= hostwrdata(22);
  hostwrdata_11(21) <= hostwrdata(21);
  hostwrdata_11(20) <= hostwrdata(20);
  hostwrdata_11(19) <= hostwrdata(19);
  hostwrdata_11(18) <= hostwrdata(18);
  hostwrdata_11(17) <= hostwrdata(17);
  hostwrdata_11(16) <= hostwrdata(16);
  hostwrdata_11(15) <= hostwrdata(15);
  hostwrdata_11(14) <= hostwrdata(14);
  hostwrdata_11(13) <= hostwrdata(13);
  hostwrdata_11(12) <= hostwrdata(12);
  hostwrdata_11(11) <= hostwrdata(11);
  hostwrdata_11(10) <= hostwrdata(10);
  hostwrdata_11(9) <= hostwrdata(9);
  hostwrdata_11(8) <= hostwrdata(8);
  hostwrdata_11(7) <= hostwrdata(7);
  hostwrdata_11(6) <= hostwrdata(6);
  hostwrdata_11(5) <= hostwrdata(5);
  hostwrdata_11(4) <= hostwrdata(4);
  hostwrdata_11(3) <= hostwrdata(3);
  hostwrdata_11(2) <= hostwrdata(2);
  hostwrdata_11(1) <= hostwrdata(1);
  hostwrdata_11(0) <= hostwrdata(0);
  emacphytxd(7) <= emacphytxd_2(7);
  emacphytxd(6) <= emacphytxd_2(6);
  emacphytxd(5) <= emacphytxd_2(5);
  emacphytxd(4) <= emacphytxd_2(4);
  emacphytxd(3) <= emacphytxd_2(3);
  emacphytxd(2) <= emacphytxd_2(2);
  emacphytxd(1) <= emacphytxd_2(1);
  emacphytxd(0) <= emacphytxd_2(0);
  emacclientrxd(7) <= emacclientrxd_7(7);
  emacclientrxd(6) <= emacclientrxd_7(6);
  emacclientrxd(5) <= emacclientrxd_7(5);
  emacclientrxd(4) <= emacclientrxd_7(4);
  emacclientrxd(3) <= emacclientrxd_7(3);
  emacclientrxd(2) <= emacclientrxd_7(2);
  emacclientrxd(1) <= emacclientrxd_7(1);
  emacclientrxd(0) <= emacclientrxd_7(0);
  emacclienttxstatsvld <= NlwRenamedSig_OI_emacclienttxstatsvld;
  speedis100 <= NlwRenamedSig_OI_emacclientrxstats(26);
  VCC_0 : VCC
    port map (
      P => N1
    );
  GND_1 : GND
    port map (
      G => N0
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1311_2053,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1311 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_131_2045,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift7_2052,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1311_2053
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift6_2051,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift7_2052
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift5_2050,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift6_2051
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift4_2049,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift5_2050
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift3_2048,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift4_2049
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift2_2047,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift3_2048
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift1_2046,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift2_2047
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => NlwRenamedSig_OI_emacclientrxstats(27),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_shift1_2046
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_131 : FDE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_2044,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_131_2045
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(26),
      A2 => NlwRenamedSig_OI_emacclientrxstats(27),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_2044,
      Q15 => NLW_BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_Q15_UNCONNECTED
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n028416 : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n0284112 : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n028421 : LUT6
    generic map(
      INIT => X"1000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n028431 : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n028441 : LUT6
    generic map(
      INIT => X"1000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n028451 : LUT6
    generic map(
      INIT => X"1000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n028461 : LUT6
    generic map(
      INIT => X"0100000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n028471 : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n028481 : LUT6
    generic map(
      INIT => X"1000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n028491 : LUT6
    generic map(
      INIT => X"1000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n0284101 : LUT6
    generic map(
      INIT => X"0100000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n02841111 : LUT6
    generic map(
      INIT => X"1000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n0284121 : LUT6
    generic map(
      INIT => X"0100000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n0284131 : LUT6
    generic map(
      INIT => X"0100000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n0284141 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mram_n0284151 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT162_G : LUT6
    generic map(
      INIT => X"1101010110000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(14),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(6),
      O => BU2_N324
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT162_F : LUT6
    generic map(
      INIT => X"0400040404000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(14),
      O => BU2_N323
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT162 : MUXF7
    port map (
      I0 => BU2_N323,
      I1 => BU2_N324,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT161
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT52_G : LUT6
    generic map(
      INIT => X"1101010110000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(9),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(1),
      O => BU2_N322
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT52_F : LUT6
    generic map(
      INIT => X"0400040404000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(9),
      O => BU2_N321
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT52 : MUXF7
    port map (
      I0 => BU2_N321,
      I1 => BU2_N322,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT51
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT104_G : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(11),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(3),
      O => BU2_N320
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT104_F : LUT5
    generic map(
      INIT => X"88088000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(11),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(3),
      O => BU2_N319
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT104 : MUXF7
    port map (
      I0 => BU2_N319,
      I1 => BU2_N320,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT103
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0904_inv_G : LUT6
    generic map(
      INIT => X"FFFFFFFF888888A8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_N318
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0904_inv_F : LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAA888"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_1573,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_N317
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0904_inv : MUXF7
    port map (
      I0 => BU2_N317,
      I1 => BU2_N318,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_1574,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0904_inv_1868
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_glue_ce_G : LUT5
    generic map(
      INIT => X"FFFFAAA8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_565,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      O => BU2_N316
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_glue_ce_F : LUT6
    generic map(
      INIT => X"FFFFFFFFAAAA2220"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_565,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      O => BU2_N315
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_glue_ce : MUXF7
    port map (
      I0 => BU2_N315,
      I1 => BU2_N316,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_glue_ce_1923
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT33_G : LUT6
    generic map(
      INIT => X"DDA2DD8099A29980"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(40),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(24),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(8),
      O => BU2_N314
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT33_F : LUT6
    generic map(
      INIT => X"5499109954111011"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(16),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(32),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(0),
      O => BU2_N313
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT33 : MUXF7
    port map (
      I0 => BU2_N313,
      I1 => BU2_N314,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT32
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_rstpot_G : LUT4
    generic map(
      INIT => X"1054"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_1963,
      O => BU2_N312
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_rstpot_F : LUT6
    generic map(
      INIT => X"0400040444444444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_1963,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv1_1582,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I5 => N1,
      O => BU2_N311
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_rstpot : MUXF7
    port map (
      I0 => BU2_N311,
      I1 => BU2_N312,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv2,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_rstpot_1973
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_2_11_INV_0 : INV
    port map (
      I => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_0_11_INV_0 : INV
    port map (
      I => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_0_INV_0 : INV
    port map (
      I => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_lut_0_INV_0 : INV
    port map (
      I => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_lut_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut_0_INV_0 : INV
    port map (
      I => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0_glue_set : LUT6
    generic map(
      INIT => X"5555FFFF10000000"
    )
    port map (
      I0 => NlwRenamedSig_OI_emacclienttxstatsvld,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I4 => N1,
      I5 => NlwRenamedSig_OI_emacclienttxstats_31_Q,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0_glue_set_1831
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT4_SW1 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0314,
      O => BU2_N299
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT30_SW1 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      O => BU2_N291
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT30_SW1 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      O => BU2_N289
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT19_SW1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      O => BU2_N283
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT4_SW1 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0314,
      O => BU2_N279
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o2 : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => hostaddr_10(8),
      I1 => hostaddr_10(7),
      I2 => hostaddr_10(6),
      I3 => hostmiimsel,
      I4 => hostaddr_10(9),
      I5 => hostopcode_9(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_rstpot1 : LUT6
    generic map(
      INIT => X"1010101010105410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1259,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1498,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_CRC_ENGINE_ERR_OR_208_o,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_rstpot1_1917
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_rstpot1 : LUT6
    generic map(
      INIT => X"1010101054101010"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1258,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_CRC_ENGINE_ERR_OR_208_o,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1498,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_rstpot1_1916
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_rstpot : LUT5
    generic map(
      INIT => X"54540444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_1573,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_rstpot_1969
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_rstpot : LUT6
    generic map(
      INIT => X"5454545404040444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_rstpot_1968
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_rstpot : LUT5
    generic map(
      INIT => X"54540444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_1955,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_rstpot_1967
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_rstpot : LUT6
    generic map(
      INIT => X"FFFFFFFF2AFA2A2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_1595,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0912_inv1,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_rstpot_1974
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_rstpot : LUT6
    generic map(
      INIT => X"0444044455440444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_763,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I3 => N1,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_1941,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_761,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_rstpot_1971
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_GND_27_o_MUX_266_o1 : LUT4
    generic map(
      INIT => X"5410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_340,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_GND_27_o_MUX_266_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT12 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N309,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT12_SW1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      O => BU2_N309
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1 : LUT6
    generic map(
      INIT => X"0444444454444444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1826,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I3 => N1,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I5 => BU2_N307,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1_1912
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1_SW1 : LUT4
    generic map(
      INIT => X"FFFD"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1492,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable22_1812,
      O => BU2_N307
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_rstpot : LUT5
    generic map(
      INIT => X"11501050"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_1977,
      I3 => N1,
      I4 => BU2_N305,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_rstpot_1976
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_rstpot_SW1 : LUT5
    generic map(
      INIT => X"D5C05500"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_1574,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0888_inv11,
      O => BU2_N305
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set : LUT6
    generic map(
      INIT => X"BBBBBBBB00000800"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I1 => N1,
      I2 => BU2_N247,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      I4 => BU2_N303,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set_1865
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set_SW1 : LUT5
    generic map(
      INIT => X"FFFFEFFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1_1216,
      O => BU2_N303
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_glue_set : LUT6
    generic map(
      INIT => X"4444444E44444444"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1643,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FALSE_CARR_FLAG_1291,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_FLAG_1297,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I5 => BU2_N301,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_glue_set_1866
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_glue_set_SW1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1287,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1643,
      O => BU2_N301
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_rstpot_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      O => BU2_N259
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_rstpot1 : LUT6
    generic map(
      INIT => X"5400444404004444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1639,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I4 => N1,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1335,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_rstpot1_1906
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_rstpot_SW0 : LUT5
    generic map(
      INIT => X"FFBF5515"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_1941,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_1935,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_1977,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      O => BU2_N257
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_glue_set : LUT6
    generic map(
      INIT => X"20F0AAF020F020F0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I3 => N1,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1278,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1306,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_glue_set_1867
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_glue_set : LUT4
    generic map(
      INIT => X"AC8C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1671,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_glue_set_1835
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_glue_set : LUT5
    generic map(
      INIT => X"11F010F0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1259,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1258,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1864,
      I3 => N1,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID_1483,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_glue_set_1863
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT4 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N299,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_12_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT6 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      I5 => BU2_N297,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_14_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT6_SW1 : LUT4
    generic map(
      INIT => X"9669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0311,
      O => BU2_N297
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT23 : LUT6
    generic map(
      INIT => X"6699F0F09966F0F0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N295,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT23_SW1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0294,
      O => BU2_N295
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT27 : LUT6
    generic map(
      INIT => X"6699F0F09966F0F0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N293,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_4_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT27_SW1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0311,
      O => BU2_N293
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT30 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N291,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_7_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT30 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_7_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT27 : LUT6
    generic map(
      INIT => X"6699F0F09966F0F0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N287,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_4_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT27_SW1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0311,
      O => BU2_N287
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT23 : LUT6
    generic map(
      INIT => X"5AA5CCCCA55ACCCC"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N285,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT23_SW1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0294,
      O => BU2_N285
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT19 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(18),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I5 => BU2_N283,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_26_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT6 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      I5 => BU2_N281,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_14_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT6_SW1 : LUT4
    generic map(
      INIT => X"9669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0311,
      O => BU2_N281
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT4 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N279,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_12_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o_1_1 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostopcode_9(1),
      I2 => hostaddr_10(8),
      I3 => hostaddr_10(7),
      I4 => hostaddr_10(6),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_FC_CE_1_INT_W_R_AND_444_o_1_1 : LUT6
    generic map(
      INIT => X"0100000000000000"
    )
    port map (
      I0 => hostaddr_10(8),
      I1 => hostmiimsel,
      I2 => hostopcode_9(1),
      I3 => hostaddr_10(9),
      I4 => hostaddr_10(6),
      I5 => hostaddr_10(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_FC_CE_1_INT_W_R_AND_444_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_TX_CE_1_INT_W_R_AND_443_o2 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(8),
      I2 => hostmiimsel,
      I3 => hostopcode_9(1),
      I4 => hostaddr_10(7),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_TX_CE_1_INT_W_R_AND_443_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_1_1 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_1474,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1544,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1546,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      O => emacclientrxstats_8(23)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TXD81 : LUT5
    generic map(
      INIT => X"FD75A820"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(7),
      O => emacphytxd_2(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TXD71 : LUT5
    generic map(
      INIT => X"FD75A820"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(6),
      O => emacphytxd_2(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TXD61 : LUT5
    generic map(
      INIT => X"FD75A820"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(5),
      O => emacphytxd_2(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TXD51 : LUT5
    generic map(
      INIT => X"FD75A820"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(4),
      O => emacphytxd_2(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TXD41 : LUT5
    generic map(
      INIT => X"FD75A820"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(3),
      O => emacphytxd_2(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TXD31 : LUT5
    generic map(
      INIT => X"FD75A820"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(2),
      O => emacphytxd_2(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TXD21 : LUT5
    generic map(
      INIT => X"FD75A820"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(1),
      O => emacphytxd_2(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TXD11 : LUT5
    generic map(
      INIT => X"FD75A820"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(0),
      O => emacphytxd_2(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT191 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(26),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(26)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT161 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(23),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(23)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT151 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(22),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(22)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT141 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(21),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(21)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT131 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(20),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(20)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT111 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(19),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(19)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT101 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(18),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(18)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT91 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(17),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(17)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT81 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(16),
      I5 => hostaddr_10(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(16)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT293 : LUT6
    generic map(
      INIT => X"7DD7D77D28828228"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT291_1794,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT29,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_6_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT293 : LUT6
    generic map(
      INIT => X"7DD7D77D28828228"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT291_1732,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT29,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_6_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_CFL_GND_27_o_MUX_270_o11 : LUT6
    generic map(
      INIT => X"0000002000003030"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT_233,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_GND_27_o_MUX_270_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In11 : LUT6
    generic map(
      INIT => X"FFFFD0F000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_1924,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In11_1548,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In11_1670
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_TX_EN_REG1_GND_30_o_MUX_491_o11 : LUT6
    generic map(
      INIT => X"5555555555551110"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_1581,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_1580,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_GND_30_o_MUX_491_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_CRC_COMPUTE_OR_168_o1 : LUT5
    generic map(
      INIT => X"888888F8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_CRC_COMPUTE_OR_168_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT161 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_9_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT151 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_8_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT141 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_7_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT131 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_6_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT121 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT111 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_4_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT101 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_3_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT91 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT81 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT21 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_10_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT17 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT481 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(9),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(17),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_9_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT471 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(8),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(16),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_8_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT461 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(15),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_7_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT451 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(14),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_6_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT441 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT431 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_4_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT421 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_15_363,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_47_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT411 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_14_365,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_46_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT401 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_13_367,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_45_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT391 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_12_369,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_44_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT381 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_11_371,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_43_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT371 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_10_373,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_42_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT361 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_9_375,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_41_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT351 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_8_377,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_40_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT341 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(11),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_3_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT331 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_7_379,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(47),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_39_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT321 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_6_381,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(46),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_38_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT311 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_5_383,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(45),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_37_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT301 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_4_385,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(44),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_36_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT291 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_3_387,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(43),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_35_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT281 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_2_389,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(42),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_34_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT271 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_1_391,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(41),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_33_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT261 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_0_393,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(40),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_32_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT251 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(31),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(39),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_31_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT241 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(30),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(38),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_30_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT231 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT221 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(29),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(37),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_29_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT211 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(28),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(36),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_28_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT201 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(27),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(35),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_27_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT191 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(26),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(34),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_26_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT181 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(33),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_25_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT171 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(32),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_24_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT161 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(23),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(31),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_23_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT151 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(22),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(30),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_22_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT141 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(21),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(29),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_21_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT131 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(20),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(28),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_20_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT121 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT111 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(19),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(27),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_19_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT101 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(18),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(26),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_18_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT91 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(17),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(25),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_17_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT81 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(16),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(24),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_16_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT71 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(15),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(23),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_15_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT61 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(14),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(22),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_14_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT51 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(13),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(21),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_13_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT49 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(12),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(20),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_12_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT310 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(11),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(19),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_11_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT210 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(10),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(18),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_10_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_GND_44_o_rx_pause_addr_47_mux_11_OUT110 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_counter_2_GND_44_o_mux_4_OUT11 : LUT4
    generic map(
      INIT => X"7111"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2_GND_44_o_mux_4_OUT_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_counter_2_GND_44_o_mux_4_OUT21 : LUT5
    generic map(
      INIT => X"60000666"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2_GND_44_o_mux_4_OUT_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_counter_2_GND_44_o_mux_4_OUT31 : LUT6
    generic map(
      INIT => X"7800000000787878"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2_GND_44_o_mux_4_OUT_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_broadcastaddressmatch_GND_44_o_MUX_1179_o11 : LUT4
    generic map(
      INIT => X"AA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcast_match_1860,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcastaddressmatch_GND_44_o_MUX_1179_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_pauseaddressmatch_GND_44_o_MUX_1187_o11 : LUT4
    generic map(
      INIT => X"AA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_1858,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pauseaddressmatch_GND_44_o_MUX_1187_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_Mmux_specialpauseaddressmatch_GND_44_o_MUX_1171_o11 : LUT4
    generic map(
      INIT => X"AA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_1862,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_specialpauseaddressmatch_GND_44_o_MUX_1171_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_INV_8_o1 : LUT6
    generic map(
      INIT => X"FFFFFFFF77F77FFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_1924,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_340,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_INV_8_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_6_11 : LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_6_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_15_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(15),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(15),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv1 : LUT4
    generic map(
      INIT => X"AA80"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_n0205_inv1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_n0205_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val1 : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_14_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(14),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(14),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_13_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(13),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_12_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(12),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_11_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(11),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(11),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_10_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(10),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_9_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(9),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_8_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(8),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_7_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_6_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_5_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_4_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_3_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_2_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT194_SW1 : LUT6
    generic map(
      INIT => X"0101000101000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(7),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(15),
      O => BU2_N225
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT194_SW0 : LUT5
    generic map(
      INIT => X"00000400"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      O => BU2_N224
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT_xor_3_13 : LUT6
    generic map(
      INIT => X"0770707070707070"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o6,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61_1735,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT3
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_0_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_0_1738,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_0_rstpot_1877
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT122 : LUT6
    generic map(
      INIT => X"0400040404000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT121_1666
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT142 : LUT6
    generic map(
      INIT => X"0400040404000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT141_1663
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT72 : LUT6
    generic map(
      INIT => X"0400040404000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT71_1660
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable41 : LUT6
    generic map(
      INIT => X"FFFFFFFF00808080"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable4
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT_xor_0_11 : LUT3
    generic map(
      INIT => X"15"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61_1735,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o6,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT_xor_2_11 : LUT5
    generic map(
      INIT => X"07707070"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o6,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61_1735,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT2
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT_xor_1_11 : LUT4
    generic map(
      INIT => X"0770"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o6,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61_1735,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07522 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_1592,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_1955,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I5 => N1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_GND_27_o_MUX_255_o1 : LUT6
    generic map(
      INIT => X"000000008080A000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE_575,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_340,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_GND_27_o_MUX_255_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In12 : LUT5
    generic map(
      INIT => X"FFFFAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_1924,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In13_1673
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_1_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT_xor_5_11 : LUT6
    generic map(
      INIT => X"22221222AAAA5AAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o6,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(0),
      I4 => BU2_N277,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61_1735,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT5
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT_xor_5_11_SW0 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(4),
      O => BU2_N277
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_glue_rst : LUT6
    generic map(
      INIT => X"AAAAFFAAAAAA8AAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      I2 => BU2_N275,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_glue_rst_1856
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_glue_rst_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT_1852,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG_1628,
      O => BU2_N275
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_rstpot1 : LUT5
    generic map(
      INIT => X"10105410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1640,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_rstpot1_1907
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_rstpot : LUT6
    generic map(
      INIT => X"00002200F0F0F0F0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0856_inv_1700,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_rstpot_1979
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_rstpot : LUT5
    generic map(
      INIT => X"FEEE0444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_1591,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5_Q,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_GND_27_o_MUX_432_o_1710,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_rstpot_1970
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_RXD_REG_7_INV_427_o5 : LUT6
    generic map(
      INIT => X"FFFFFFFF7DBEFFFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I4 => BU2_N219,
      I5 => BU2_N201,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_RXD_REG_7_INV_427_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_rstpot1 : LUT6
    generic map(
      INIT => X"0444444405554444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1238,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1640,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      I4 => N1,
      I5 => BU2_N273,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_rstpot1_1913
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_rstpot1_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      O => BU2_N273
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n01473 : LUT6
    generic map(
      INIT => X"000002000000AA00"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_343,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_308,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I5 => BU2_N271,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0147
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n01473_SW0 : LUT6
    generic map(
      INIT => X"F0B0F0F0F0F0F0F0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => BU2_N271
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut_0_Q : LUT6
    generic map(
      INIT => X"7777777744407777"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I2 => BU2_N269,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut_0_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(6),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(7),
      O => BU2_N269
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot : LUT6
    generic map(
      INIT => X"FEEEAAAA0222AAAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1814,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I4 => N1,
      I5 => BU2_N267,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot_1892
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I5 => BU2_N182,
      O => BU2_N267
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_glue_set : LUT6
    generic map(
      INIT => X"02AA02AA02AAFFFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1546,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I3 => N1,
      I4 => BU2_N199,
      I5 => BU2_N265,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_glue_set_1833
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_glue_set_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      I2 => BU2_N234,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008141,
      I4 => BU2_N2,
      O => BU2_N265
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot1 : LUT6
    generic map(
      INIT => X"0515151500001000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1331,
      I4 => BU2_N261,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1815,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot1_1908
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot1_SW0 : LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o11,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o111_1822,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o112_1823,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o113_1824,
      O => BU2_N261
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_rstpot : LUT6
    generic map(
      INIT => X"1150105010501050"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_1966,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_761,
      I3 => N1,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT,
      I5 => BU2_N259,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_rstpot_1972
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT_xor_4_11 : LUT6
    generic map(
      INIT => X"000000006AAAAAAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT4
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_rstpot : LUT4
    generic map(
      INIT => X"1054"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_1941,
      I3 => BU2_N257,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_rstpot_1975
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_INT_glue_set : LUT6
    generic map(
      INIT => X"00202020FAFAFAFA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT_1852,
      I2 => NlwRenamedSig_OI_hostmiimrdy,
      I3 => BU2_N255,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(6),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_STATE_VAR_1625,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_INT_glue_set_1853
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_INT_glue_set_SW0 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_INT_RD_DATA291,
      I1 => hostmiimsel,
      I2 => hostreq,
      O => BU2_N255
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_rstpot : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONFIG_RD_WR,
      I4 => hostwrdata_11(31),
      I5 => hostaddr_10(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_rstpot_1894
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_rstpot : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      I1 => hostaddr_10(7),
      I2 => hostaddr_10(8),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONFIG_RD_WR,
      I4 => hostwrdata_11(31),
      I5 => hostaddr_10(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_rstpot_1893
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_glue_set : LUT6
    generic map(
      INIT => X"F444444444444444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0189_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_1898,
      I3 => clientemacpausereq,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In11_1548,
      I5 => N1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_glue_set_1834
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_14_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_14_1744,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_14_rstpot_1890
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_15_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_15_1745,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_15_rstpot_1889
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_13_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_13_1743,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_13_rstpot_1888
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_12_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_12_1742,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_12_rstpot_1887
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_11_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_11_1741,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_11_rstpot_1886
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_10_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_10_1740,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_10_rstpot_1885
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_7_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_7_1764,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(9),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_7_rstpot_1884
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_9_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_9_1766,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_9_rstpot_1883
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_8_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_8_1765,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_8_rstpot_1882
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_6_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_6_1763,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(10),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_6_rstpot_1881
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_5_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_5_1761,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(11),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_5_rstpot_1880
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_4_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_4_1759,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(12),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_4_rstpot_1879
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_3_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_3_1757,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(13),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_3_rstpot_1878
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_2_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_2_1752,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(14),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_2_rstpot_1876
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_1_rstpot : LUT5
    generic map(
      INIT => X"AAEAAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_1_1747,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_n0284(15),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_1_rstpot_1875
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28_glue_set : LUT5
    generic map(
      INIT => X"FFFFFBEA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_TX_CE_1_INT_W_R_AND_443_o,
      I2 => hostwrdata_11(28),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28_574,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_1542,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28_glue_set_1855
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28_glue_set : LUT5
    generic map(
      INIT => X"FFFFFBEA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      I2 => hostwrdata_11(28),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28_1305,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_1541,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28_glue_set_1854
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_rstpot : LUT6
    generic map(
      INIT => X"5454545404044404"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_1966,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID_1602,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_rstpot_1965
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot1 : LUT6
    generic map(
      INIT => X"1515150000150000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552,
      I2 => BU2_N253,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0084_inv1,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_565,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot1_1900
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot1_SW0 : LUT4
    generic map(
      INIT => X"AA2A"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      O => BU2_N253
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG_rstpot : LUT6
    generic map(
      INIT => X"AAEAAA2AAA2AAA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG_1628,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(6),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_INT_RD_DATA291,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG_rstpot_1891
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT_glue_set : LUT6
    generic map(
      INIT => X"F444444444444444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_STATE_VAR_AND_456_o,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT_1852,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_INT_RD_DATA291,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(6),
      I4 => hostmiimsel,
      I5 => hostreq,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT_glue_set_1851
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_rstpot : LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o6,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61_1735,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_rstpot_1874
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_rstpot : LUT5
    generic map(
      INIT => X"54440444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1708,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I3 => N1,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_rstpot_1980
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set_SW0 : LUT3
    generic map(
      INIT => X"BF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      O => BU2_N247
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot1 : LUT6
    generic map(
      INIT => X"0004444450544444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_1477,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH_1488,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I4 => N1,
      I5 => BU2_N245,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot1_1910
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot1_SW0 : LUT6
    generic map(
      INIT => X"FFFFFF1FFFFFFFFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pauseaddressmatch_1041,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_specialpauseaddressmatch_1032,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o1,
      O => BU2_N245
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2_rstpot : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_1574,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2_rstpot_1896
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_rstpot1 : LUT5
    generic map(
      INIT => X"10105410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_1260,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1498,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_rstpot1_1915
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_rstpot1 : LUT5
    generic map(
      INIT => X"10105410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_1237,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1503,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1814,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_rstpot1_1914
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_rstpot1 : LUT5
    generic map(
      INIT => X"10105410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG2_1218,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_rstpot1_1905
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_rstpot1 : LUT5
    generic map(
      INIT => X"45054000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1864,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1259,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_rstpot1_1904
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_rstpot1 : LUT5
    generic map(
      INIT => X"45054000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1864,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1258,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_rstpot1_1902
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_rstpot1 : LUT5
    generic map(
      INIT => X"10105410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1544,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_SYNC,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_HALF_DUPLEX_SYNC,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_rstpot1_1899
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_rstpot1 : LUT5
    generic map(
      INIT => X"10105410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_1898,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_SYNC,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_HALF_DUPLEX_SYNC,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_rstpot1_1897
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_rstpot : LUT6
    generic map(
      INIT => X"5151515540404000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_HALF_DUPLEX_580,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_1697,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_rstpot_1981
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_rstpot1 : LUT4
    generic map(
      INIT => X"5410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_234,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID_1483,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_rstpot1_1903
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_rstpot1 : LUT5
    generic map(
      INIT => X"10105410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => N1,
      I2 => NlwRenamedSig_OI_emacclienttxstats_2_Q,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH_1961,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_BROADCAST,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_rstpot1_1901
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_rstpot : LUT5
    generic map(
      INIT => X"54540444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_FCS_GND_27_o_MUX_278_o11,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_rstpot_1978
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_0_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut_7_Q : LUT4
    generic map(
      INIT => X"F533"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008144_SW2_G : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      O => BU2_N244
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008144_SW2_F : LUT6
    generic map(
      INIT => X"FFFFFFFFFF02FFFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      O => BU2_N243
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008144_SW2 : MUXF7
    port map (
      I0 => BU2_N243,
      I1 => BU2_N244,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      O => BU2_N236
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_rstpot_1981,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_rstpot_1938,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_rstpot_1873,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_1697
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_rstpot_1872,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_rstpot_1870,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_rstpot_1980,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1708
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_rstpot_1944,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_rstpot_1979,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_rstpot_1978,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_rstpot_1942,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_rstpot_1936,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_1935
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_rstpot_1976,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_1977
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_rstpot_1975,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_1941
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_rstpot_1869,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_rstpot_1974,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_1595
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_rstpot_1973,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2 : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_rstpot_1972,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_761
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_rstpot_1971,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_763
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_rstpot_1970,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_1591
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_rstpot_1969,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_1573
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_rstpot_1968,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_rstpot_1967,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_1955
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_rstpot_1965,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_1966
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1 : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0100_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_GND_30_o_MUX_491_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_1649
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1 : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0100_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_GND_30_o_MUX_493_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_1647
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0100_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_GND_30_o_MUX_507_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_1534
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0100_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_GND_30_o_MUX_509_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_1533
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0776_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_GND_27_o_MUX_231_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_1963
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0776_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_GND_27_o_MUX_233_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1951
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0776_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_GND_27_o_MUX_237_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_1559
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_GND_27_o_MUX_304_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_1572
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_GND_27_o_MUX_341_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_GND_27_o_MUX_345_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_788
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_GND_27_o_MUX_347_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1578
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_GND_27_o_MUX_349_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_GND_27_o_MUX_383_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_GND_27_o_MUX_401_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_1581
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID_GND_27_o_MUX_403_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID_1602
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0998_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH_GND_27_o_MUX_424_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH_1587
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0998_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH_GND_27_o_MUX_426_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH_1586
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0998_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH_GND_27_o_MUX_428_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH_1588
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0998_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH_GND_27_o_MUX_430_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH_1589
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0998_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_GND_27_o_MUX_432_o_1710,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_1590
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL_GND_27_o_MUX_439_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL_760
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN_GND_27_o_MUX_441_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN_745
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_GND_27_o_MUX_266_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_1924
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0776_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_GND_27_o_MUX_229_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_1574
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_GND_27_o_MUX_343_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1601
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_GND_27_o_MUX_399_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_1580
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_GND_27_o_MUX_443_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_1592
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VALID : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_GND_27_o_MUX_408_o,
      Q => NlwRenamedSig_OI_emacclienttxstatsvld
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH : FDE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0998_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH_GND_27_o_MUX_434_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH_1961
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R3 : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R2_218,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R3_1539
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4 : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R3_PWR_16_o_MUX_15_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R3 : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R2_215,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R3_1537
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4 : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R3_PWR_16_o_MUX_15_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R3 : FD
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R2_212,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R3_1535
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4 : FD
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R3_PWR_16_o_MUX_15_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n00881 : LUT6
    generic map(
      INIT => X"0000050400010505"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I1 => BU2_N199,
      I2 => BU2_N203,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008141,
      I4 => BU2_N237,
      I5 => BU2_N236,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0088
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008144_SW3 : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      O => BU2_N237
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008144_SW1 : LUT6
    generic map(
      INIT => X"FFDFFFFFFFFFFFFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      O => BU2_N234
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT195 : LUT6
    generic map(
      INIT => X"FF55FE54FB51FA50"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_N224,
      I3 => BU2_N225,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT192_1678,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT191_1677,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_7_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0324_inv111 : LUT5
    generic map(
      INIT => X"AA808080"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0324_inv11
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv1 : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_1592,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I4 => N1,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_1955,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0189_inv1 : LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0189_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_RXD_REG_7_INV_427_o3_SW1 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28),
      O => BU2_N219
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_REG_TX_VLAN_GND_27_o_MUX_441_o11 : LUT6
    generic map(
      INIT => X"0100000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(11),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN1,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1951,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN_GND_27_o_MUX_441_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_INV_104_o1 : LUT5
    generic map(
      INIT => X"FBFFFFFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1951,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(11),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_INV_104_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv24 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(9),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14),
      I3 => BU2_N217,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv23_1703,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv21_1702,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv2
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv24_SW0 : LUT4
    generic map(
      INIT => X"F7EF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_818,
      O => BU2_N217
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_glue_set : LUT5
    generic map(
      INIT => X"FFFF02AA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1545,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I3 => N1,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0088,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_glue_set_1832
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_rstpot1 : LUT5
    generic map(
      INIT => X"00E40044"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1645,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_RXD_REG_7_INV_427_o,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_rstpot1_1918
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_glue_set : LUT6
    generic map(
      INIT => X"0A00CECC0000CCCC"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_1858,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0112_inv,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_glue_set_1857
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_glue_set : LUT6
    generic map(
      INIT => X"444444444444F444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0080_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_REG_566,
      I3 => N1,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_310,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_glue_set_1836
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_rstpot1 : LUT4
    generic map(
      INIT => X"5410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable4,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0324_inv11,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_1475,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_CONTROL_MATCH_AND_335_o,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_rstpot1_1911
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_rstpot1 : LUT4
    generic map(
      INIT => X"00CA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_1476,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0412_inv1_1818,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable6_1820,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_rstpot1_1909
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_rstpot : LUT5
    generic map(
      INIT => X"FE04FC0C"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_GND_27_o_MUX_270_o,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0848_inv1_1701,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_rstpot_1944
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_rstpot : LUT5
    generic map(
      INIT => X"FF00F870"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_1941,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_GND_27_o_MUX_298_o,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0904_inv_1868,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_rstpot_1942
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0_glue_set_1850
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1_glue_set_1849
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2_glue_set_1848
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3_glue_set_1847
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4_glue_set_1846
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5_glue_set_1845
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6_glue_set_1844
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7_glue_set_1843
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8_glue_set_1842
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(9),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9_glue_set_1841
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(10),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10_glue_set_1840
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(11),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(11),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11_glue_set_1839
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(12),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12_glue_set_1838
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13_glue_set : LUT4
    generic map(
      INIT => X"FEF4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1094_inv,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(13),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0752,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13_glue_set_1837
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcast_match_glue_set : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcast_match_1860,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0108_inv_1784,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0072_1782,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcast_match_glue_set_1859
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_rstpot : LUT6
    generic map(
      INIT => X"FFFFFFFF2AFA2A2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_1697,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv1_1582,
      I4 => BU2_N215,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_rstpot_1938
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_rstpot_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_1595,
      O => BU2_N215
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_rstpot : LUT5
    generic map(
      INIT => X"54540444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_1935,
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_FRAME_GOOD_GND_27_o_MUX_286_o11,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_rstpot_1936
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv1 : LUT6
    generic map(
      INIT => X"00FF00FF00FF01FF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I4 => BU2_N213,
      I5 => BU2_N34,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv1_SW1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      O => BU2_N213
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0112_inv1 : LUT6
    generic map(
      INIT => X"28AAAAAAAAAAAAAA"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I3 => BU2_N211,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb8,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb81_1786,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0112_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb83_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      O => BU2_N211
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0080_inv1 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(15),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(14),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(13),
      I3 => BU2_N209,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_1_1690,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_Q,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0080_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_3_SW0 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(12),
      O => BU2_N209
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_ERR_REG5_END_EXT_AND_258_o1 : LUT6
    generic map(
      INIT => X"2222000222222222"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1643,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1337,
      I2 => BU2_N207,
      I3 => BU2_N168,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_ERR_REG5_END_EXT_AND_258_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG_SW1 : LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      O => BU2_N207
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_RX_DV_REG6_RX_DV_REG6_MUX_599_o1 : LUT6
    generic map(
      INIT => X"00FF00FF04BF00FF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      I2 => BU2_N193,
      I3 => BU2_N192,
      I4 => BU2_N205,
      I5 => BU2_N168,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_DV_REG6_MUX_599_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_RX_DV_REG6_RX_DV_REG6_MUX_599_o1_SW0 : LUT3
    generic map(
      INIT => X"81"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      O => BU2_N205
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n00881_SW0_SW0 : LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      I3 => N1,
      O => BU2_N203
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_RXD_REG_7_INV_427_o3_SW0 : LUT6
    generic map(
      INIT => X"7FDFBFEFF7FDFBFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      O => BU2_N201
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008144_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(3),
      O => BU2_N199
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut_6_Q : LUT4
    generic map(
      INIT => X"F533"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut_5_Q : LUT4
    generic map(
      INIT => X"F533"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut_4_Q : LUT4
    generic map(
      INIT => X"F533"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut_3_Q : LUT4
    generic map(
      INIT => X"0533"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut_2_Q : LUT4
    generic map(
      INIT => X"0533"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut_1_Q : LUT4
    generic map(
      INIT => X"F533"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_glue_set : LUT6
    generic map(
      INIT => X"0A00CECC0000CCCC"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_1862,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_n0018_inv,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_glue_set_1861
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_END_OF_TX1 : LUT6
    generic map(
      INIT => X"080800000A000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_1924,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_340,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_rstpot : LUT3
    generic map(
      INIT => X"0E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_glue_ce_1923,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0141_1687,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_rstpot_1895
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_n0018_inv1 : LUT6
    generic map(
      INIT => X"28AAAAAAAAAAAAAA"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(7),
      I3 => BU2_N195,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb8,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb81_1789,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_n0018_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb83_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(0),
      O => BU2_N195
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_RX_DV_REG6_RX_DV_REG6_MUX_599_o1_SW0_SW1 : LUT6
    generic map(
      INIT => X"FFFF333354551011"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1337,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1278,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1287,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1288,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      O => BU2_N193
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_RX_DV_REG6_RX_DV_REG6_MUX_599_o1_SW0_SW0 : LUT6
    generic map(
      INIT => X"AAA2FFE2AAA2FFF3"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1278,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1287,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1337,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1288,
      O => BU2_N192
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_rstpot1_1918,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1645
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_rstpot1_1917,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1259
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_rstpot1_1916,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1258
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_rstpot1_1915,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_1260
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_rstpot1_1914,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_1237
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_rstpot1_1913,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1238
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1_1912,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1826
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_rstpot1_1911,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_1475
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot1_1910,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_1477
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_rstpot1_1909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_1476
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot1_1908,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1815
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_rstpot1_1907,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1640
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_rstpot1_1906,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1639
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_rstpot1_1905,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_rstpot1_1904,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_rstpot1_1903,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_234
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_rstpot1_1902,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2 : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_rstpot1_1901,
      Q => NlwRenamedSig_OI_emacclienttxstats_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot1_1900,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_565
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG : FD
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_rstpot1_1899,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1544
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_rstpot1_1897,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_1898
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2 : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2_rstpot_1896,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_rstpot_1895,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_rstpot_1894,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_1542
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_rstpot_1893,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_1541
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET : FDS
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot_1892,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1814
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG_rstpot_1891,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG_1628
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_14 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_14_rstpot_1890,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_14_1744
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_15 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_15_rstpot_1889,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_15_1745
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_13 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_13_rstpot_1888,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_13_1743
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_12 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_12_rstpot_1887,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_12_1742
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_11 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_11_rstpot_1886,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_11_1741
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_10 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_10_rstpot_1885,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_10_1740
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_7 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_7_rstpot_1884,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_7_1764
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_9 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_9_rstpot_1883,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_9_1766
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_8 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_8_rstpot_1882,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_8_1765
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_6 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_6_rstpot_1881,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_6_1763
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_5 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_5_rstpot_1880,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_5_1761
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_4 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_4_rstpot_1879,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_4_1759
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_3 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_3_rstpot_1878,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_3_1757
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_0 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_0_rstpot_1877,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_0_1738
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_2 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_2_rstpot_1876,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_2_1752
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_1 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_1_rstpot_1875,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_1_1747
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_rstpot_1874,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_rstpot : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_1697,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_GND_27_o_MUX_255_o,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0818_inv,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_rstpot_1873
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_rstpot : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_GND_27_o_MUX_255_o,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0826_inv,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_rstpot_1872
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_rstpot : LUT3
    generic map(
      INIT => X"E2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0834_inv_1698,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_GND_27_o_MUX_263_o,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_rstpot_1870
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_rstpot : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_GND_27_o_MUX_298_o,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0904_inv_1868,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_rstpot_1869
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(14),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_14_rt_1373
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_10_rt_1341
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_rt_584
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_1_rt_1412
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_2_rt_1409
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_3_rt_1406
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_4_rt_1403
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_5_rt_1400
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_6_rt_1397
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_7_rt_1394
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_8_rt_1391
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_9_rt_1388
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_10_rt_1385
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(11),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_11_rt_1382
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_12_rt_1379
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_13_rt_1376
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_rt_1368
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_rt_1365
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_rt_1362
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_rt_1359
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_rt_1356
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_rt_1353
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_rt_1350
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_rt_1347
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_9_rt_1344
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt_623
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt_620
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt_617
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt_614
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt_611
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt_608
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt_605
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt_602
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt_599
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt_596
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(11),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt_593
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt_590
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt_587
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE : FDR
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_glue_set_1867,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD : FDR
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_glue_set_1866,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1643
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT : FDR
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set_1865,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED : FDR
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_glue_set_1863,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1864
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match : FDR
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_glue_set_1861,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_1862
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcast_match : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcast_match_glue_set_1859,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcast_match_1860
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_glue_set_1857,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_1858
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT : FDS
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_glue_rst_1856,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28_glue_set_1855,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28_574
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28_glue_set_1854,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28_1305
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_INT : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_INT_glue_set_1853,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => NlwRenamedSig_OI_hostmiimrdy
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_STATE_VAR : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_STATE_VAR_1625
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT_glue_set_1851,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_REQ_INT_1852
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0_glue_set_1850,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1_glue_set_1849,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2_glue_set_1848,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3_glue_set_1847,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4_glue_set_1846,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5_glue_set_1845,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6_glue_set_1844,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7_glue_set_1843,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8_glue_set_1842,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9_glue_set_1841,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10_glue_set_1840,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11_glue_set_1839,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12_glue_set_1838,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13_glue_set_1837,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_glue_set_1836,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_glue_set_1835,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1671
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_glue_set_1834,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT : FDR
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_glue_set_1833,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1546
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT : FDR
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_glue_set_1832,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1545
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0_glue_set_1831,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => NlwRenamedSig_OI_emacclienttxstats_31_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o3 : LUT5
    generic map(
      INIT => X"11111000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD_1304,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o1_1829,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o2_1830,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1495,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o2 : LUT4
    generic map(
      INIT => X"1101"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(9),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1239,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o2_1830
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o1 : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1643,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(8),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(10),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(6),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o21,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o1_1829
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o3 : LUT6
    generic map(
      INIT => X"FFA8FFA8FFFFFFA8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o2_1828,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o1_1827,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1503,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1505,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o2 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1826,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1814,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1301,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1815,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o2_1828
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o1 : LUT6
    generic map(
      INIT => X"00B000B0BBBB00B0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1505,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_1507,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_1241,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PAUSE_LT_CHECK_HELD_1303,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1826,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1301,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o1_1827
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_38_o_AND_331_o_0_Q : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I5 => BU2_N190,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_38_o_AND_331_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_38_o_AND_331_o_0_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VLAN_ENABLE_HELD_1307,
      O => BU2_N190
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o114 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o113_1824
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o113 : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o112_1823
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o112 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(10),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(10),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(7),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o111_1822
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o111 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(9),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(9),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(8),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_LENGTH_TYPE_10_equal_9_o11
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable6 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFDF0000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1335,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      I4 => BU2_N188,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable6_1820
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable6_SW0 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcastaddressmatch_1043,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      O => BU2_N188
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0412_inv1 : LUT6
    generic map(
      INIT => X"AAAAAAAA02000000"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1335,
      I5 => BU2_N186,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0412_inv1_1818
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0412_inv1_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcastaddressmatch_1043,
      O => BU2_N186
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_183_o : LUT6
    generic map(
      INIT => X"FFFFFFFF00010101"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO_1494,
      I2 => BU2_N184,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1331,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_183_o_1484
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_183_o_SW0 : LUT5
    generic map(
      INIT => X"FFFF5755"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_1485,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1814,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1301,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1815,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ONE_1490,
      O => BU2_N184
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_TYPE_PACKET_GND_36_o_MUX_710_o1_SW0 : LUT4
    generic map(
      INIT => X"FFF7"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      O => BU2_N182
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable22 : LUT5
    generic map(
      INIT => X"AAAA8000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable22_1812
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1301,
      I3 => BU2_N180,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o1,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o_1489
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o_SW0 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1492,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      O => BU2_N180
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_34_o_RX_ERR_REG6_AND_247_o : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1287,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(1),
      I3 => BU2_N174,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(7),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_34_o_RX_ERR_REG6_AND_247_o_1294
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_34_o_RX_ERR_REG6_AND_247_o_SW0 : LUT5
    generic map(
      INIT => X"F7FFFFFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(0),
      O => BU2_N174
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GND_32_o_RX_DV_REG6_AND_249_o : LUT6
    generic map(
      INIT => X"0100000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(7),
      I2 => BU2_N172,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1287,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GND_32_o_RX_DV_REG6_AND_249_o_1292
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GND_32_o_RX_DV_REG6_AND_249_o_SW0 : LUT5
    generic map(
      INIT => X"FFFFEFFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(5),
      O => BU2_N172
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_IFG_FLAG : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      I5 => BU2_N168,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_IFG_FLAG_1296
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(0),
      I5 => BU2_N168,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG_1290
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(7),
      O => BU2_N168
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT2 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0311,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N154,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_10_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT3 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0294,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N126,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_11_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT5 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0311,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N160,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_13_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT5_SW0 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      O => BU2_N160
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT7 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0314,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N136,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_15_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT8 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0290,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(8),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N154,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_16_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT8_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29),
      O => BU2_N154
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT9 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(9),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N152,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_17_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT9_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      O => BU2_N152
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT10 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0298,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(10),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N150,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_18_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT10_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      O => BU2_N150
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT12 : LUT6
    generic map(
      INIT => X"E44E4EE44EE4E44E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0298,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0292,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I5 => BU2_N148,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT12_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      O => BU2_N148
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT16 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0298,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(15),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N146,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_23_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT16_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      O => BU2_N146
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT17 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(16),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N144,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_24_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT17_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      O => BU2_N144
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT19 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(18),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0298,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0292,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0290,
      I5 => BU2_N142,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_26_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT19_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27),
      O => BU2_N142
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT20 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0314,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(19),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N132,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_27_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT21 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(20),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N138,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_28_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT21_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      O => BU2_N138
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT22 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0298,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(21),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N136,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_29_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT22_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      O => BU2_N136
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT26 : LUT6
    generic map(
      INIT => X"7DD7D77D28828228"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0311,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => BU2_N132,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_3_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT26_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      O => BU2_N132
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT283 : LUT5
    generic map(
      INIT => X"69FF6900"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT28,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT281_1796,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0314,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT282 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT281_1796
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT281 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT28
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT292 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT291_1794
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT291 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT29
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT31 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0294,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N126,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_8_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT31_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28),
      O => BU2_N126
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT32 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0314,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I5 => BU2_N124,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_9_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT32_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      O => BU2_N124
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb83 : LUT6
    generic map(
      INIT => X"8421000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb81_1789,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb8,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb82 : LUT6
    generic map(
      INIT => X"8040201008040201"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb81_1789
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb81 : LUT6
    generic map(
      INIT => X"8040201008040201"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(6),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_match_comb8
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb83 : LUT6
    generic map(
      INIT => X"8421000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb81_1786,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb8,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb82 : LUT6
    generic map(
      INIT => X"8040201008040201"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb81_1786
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb81 : LUT6
    generic map(
      INIT => X"8040201008040201"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_match_comb8
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0108_inv : LUT6
    generic map(
      INIT => X"2AAAAAAAAAAAAAAA"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      I5 => BU2_N122,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0108_inv_1784
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0108_inv_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      O => BU2_N122
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0072 : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_N120,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0072_1782
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0072_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFF7FFFFFFF"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      O => BU2_N120
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_TRISTATE_COMB : LUT6
    generic map(
      INIT => X"FFFFFFFF88888000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_OP_INT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I3 => BU2_N118,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_TRISTATE_COMB_1027
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_TRISTATE_COMB_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      O => BU2_N118
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1013 : LUT6
    generic map(
      INIT => X"FFF7FFF7FFF7DDD5"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1011_1779,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING108_1776,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING102_1770,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING105_1773,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_OUT_RISING
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1012 : LUT6
    generic map(
      INIT => X"0F0F0F0F0F0F0002"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING109_1777,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1010_1778,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1011_1779
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1011 : LUT6
    generic map(
      INIT => X"CCF00000AA000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(10),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1010_1778
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING1010 : LUT6
    generic map(
      INIT => X"0000CCF00000AAFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(14),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING109_1777
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING109 : LUT4
    generic map(
      INIT => X"D580"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING106_1774,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING107_1775,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING108_1776
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING108 : LUT6
    generic map(
      INIT => X"0000CC00F000AAAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_OP_INT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING107_1775
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING107 : LUT6
    generic map(
      INIT => X"F0F0CCCCFF00AAAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(12),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(8),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING106_1774
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING106 : LUT6
    generic map(
      INIT => X"F0F0F0F0F0F02000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING103_1771,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING104_1772,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING105_1773
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING105 : LUT6
    generic map(
      INIT => X"0000AA000000CCF0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(13),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_OP_INT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING104_1772
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING104 : LUT6
    generic map(
      INIT => X"CCFF0000AAF00000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(9),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING103_1771
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING103 : LUT4
    generic map(
      INIT => X"7520"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING10,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING101_1769,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING102_1770
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING102 : LUT6
    generic map(
      INIT => X"CCCC00AA00F00000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING101_1769
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING101 : LUT6
    generic map(
      INIT => X"F0F0CCCCFF00AAAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(15),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(11),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mmux_MDIO_OUT_RISING10
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT5 : LUT6
    generic map(
      INIT => X"4444444414444444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I5 => BU2_N116,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT5_1011
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT5_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      O => BU2_N116
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT32 : LUT6
    generic map(
      INIT => X"BBBAAABA11100010"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_N90,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(9),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_9_375,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_9_1766,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT31 : LUT6
    generic map(
      INIT => X"BBBAAABA11100010"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_N90,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(8),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_8_377,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_8_1765,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT30 : LUT6
    generic map(
      INIT => X"BBBAAABA11100010"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_N90,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(7),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_7_379,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_7_1764,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT292 : LUT5
    generic map(
      INIT => X"AAEA0040"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT29,
      I2 => hostaddr_10(9),
      I3 => hostaddr_10(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_6_1763,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT291 : LUT6
    generic map(
      INIT => X"B9313131A8202020"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_6_381,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_INT_RD_DATA291,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT29
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT282 : LUT5
    generic map(
      INIT => X"AAEA0040"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT28,
      I2 => hostaddr_10(9),
      I3 => hostaddr_10(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_5_1761,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT281 : LUT5
    generic map(
      INIT => X"B931A820"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_5_383,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT28
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT272 : LUT5
    generic map(
      INIT => X"AAEA0040"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT27,
      I2 => hostaddr_10(9),
      I3 => hostaddr_10(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_4_1759,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT271 : LUT5
    generic map(
      INIT => X"B931A820"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_4_385,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT27
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT262 : LUT5
    generic map(
      INIT => X"AAEA0040"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT26,
      I2 => hostaddr_10(9),
      I3 => hostaddr_10(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_3_1757,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT261 : LUT5
    generic map(
      INIT => X"B931A820"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_3_387,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT26
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT253 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT251_1755,
      I1 => hostaddr_10(9),
      I2 => hostmiimsel,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(31)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT252 : LUT6
    generic map(
      INIT => X"1707120215051000"
    )
    port map (
      I0 => hostaddr_10(7),
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_1541,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT25,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_1542,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT251_1755
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT251 : LUT3
    generic map(
      INIT => X"4E"
    )
    port map (
      I0 => hostaddr_10(8),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(31),
      I2 => hostaddr_10(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT25
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT242 : LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT24,
      I1 => hostaddr_10(9),
      I2 => hostaddr_10(8),
      I3 => hostmiimsel,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(30)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT241 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_30_1006,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_in,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_30_576,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(30),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT24
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT232 : LUT5
    generic map(
      INIT => X"AAEA0040"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT23,
      I2 => hostaddr_10(9),
      I3 => hostaddr_10(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_2_1752,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT231 : LUT5
    generic map(
      INIT => X"B931A820"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_2_389,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT23
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT222 : LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT22,
      I1 => hostaddr_10(9),
      I2 => hostaddr_10(8),
      I3 => hostmiimsel,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(29)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT221 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_29_1007,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_in,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_29_1000,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(29),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT22
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT21 : LUT6
    generic map(
      INIT => X"1055104410111000"
    )
    port map (
      I0 => BU2_N104,
      I1 => hostaddr_10(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28_1305,
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(28),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28_574,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(28)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT20 : LUT6
    generic map(
      INIT => X"1055104410111000"
    )
    port map (
      I0 => BU2_N104,
      I1 => hostaddr_10(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_27_1005,
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(27),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_27_999,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(27)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT18 : LUT6
    generic map(
      INIT => X"1055104410111000"
    )
    port map (
      I0 => BU2_N104,
      I1 => hostaddr_10(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_25_1004,
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(25),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_25_572,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(25)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT18_SW0 : LUT3
    generic map(
      INIT => X"FD"
    )
    port map (
      I0 => hostaddr_10(9),
      I1 => hostmiimsel,
      I2 => hostaddr_10(8),
      O => BU2_N104
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT17 : LUT6
    generic map(
      INIT => X"0400040404000000"
    )
    port map (
      I0 => hostmiimsel,
      I1 => hostaddr_10(9),
      I2 => BU2_N102,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_24_1003,
      I4 => hostaddr_10(6),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(24),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(24)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT17_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => hostaddr_10(8),
      I1 => hostaddr_10(7),
      O => BU2_N102
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT122 : LUT5
    generic map(
      INIT => X"AAEA0040"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT12,
      I2 => hostaddr_10(9),
      I3 => hostaddr_10(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_1_1747,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT121 : LUT5
    generic map(
      INIT => X"B931A820"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_1_391,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT12
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT7 : LUT6
    generic map(
      INIT => X"BBBAAABA11100010"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_N90,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(15),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_15_363,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_15_1745,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT6 : LUT6
    generic map(
      INIT => X"BBBAAABA11100010"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_N90,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(14),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_14_365,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_14_1744,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT5 : LUT6
    generic map(
      INIT => X"BBBAAABA11100010"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_N90,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(13),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_13_367,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_13_1743,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT4 : LUT6
    generic map(
      INIT => X"BBBAAABA11100010"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_N90,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(12),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_12_369,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_12_1742,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT3 : LUT6
    generic map(
      INIT => X"BBBAAABA11100010"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_N90,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(11),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_11_371,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_11_1741,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT2 : LUT6
    generic map(
      INIT => X"BBBAAABA11100010"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_N90,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(10),
      I3 => hostaddr_10(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_10_373,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_10_1740,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT2_SW0 : LUT3
    generic map(
      INIT => X"FD"
    )
    port map (
      I0 => hostaddr_10(9),
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(7),
      O => BU2_N90
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT13 : LUT5
    generic map(
      INIT => X"AAEA0040"
    )
    port map (
      I0 => hostmiimsel,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT1,
      I2 => hostaddr_10(9),
      I3 => hostaddr_10(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_RD_DATA_0_1738,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT11 : LUT5
    generic map(
      INIT => X"B931A820"
    )
    port map (
      I0 => hostaddr_10(6),
      I1 => hostaddr_10(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_0_393,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_RD_DATA_INT1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o63 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o6,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61_1735,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o62 : LUT6
    generic map(
      INIT => X"8020401008020401"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61_1735
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o61 : LUT6
    generic map(
      INIT => X"8241000000008241"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5_CLK_DIVIDE_5_equal_20_o6
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT32 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0314,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N88,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_9_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT32_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      O => BU2_N88
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT31 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0294,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N48,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_8_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT292 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT291_1732
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT291 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT29
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT283 : LUT5
    generic map(
      INIT => X"69FF6900"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT28,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT281_1730,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0314,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT282 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT281_1730
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT281 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT28
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT26 : LUT6
    generic map(
      INIT => X"7DD7D77D28828228"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0311,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I4 => BU2_N72,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_3_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT22 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0298,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(21),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N56,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_29_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT21 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(20),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N74,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_28_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT21_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      O => BU2_N74
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT20 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0314,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(19),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N72,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_27_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT20_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      O => BU2_N72
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT17 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(16),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N68,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_24_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT17_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      O => BU2_N68
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT16 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0298,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(15),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N66,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_23_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT16_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      O => BU2_N66
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT10 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0298,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(10),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N62,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_18_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT10_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      O => BU2_N62
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT9 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(9),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N60,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_17_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT9_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      O => BU2_N60
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT8 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0290,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(8),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N46,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_16_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT7 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0314,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N56,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_15_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT7_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      O => BU2_N56
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT5 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0311,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N52,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_13_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT5_SW0 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      O => BU2_N52
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT3 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0294,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N48,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_11_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT3_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      O => BU2_N48
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT2 : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0311,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I5 => BU2_N46,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_10_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT2_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      O => BU2_N46
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DST_ADDR_BYTE2_MATCH_GND_27_o_MUX_428_o1 : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(3),
      I5 => BU2_N44,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH_GND_27_o_MUX_428_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DST_ADDR_BYTE2_MATCH_GND_27_o_MUX_428_o1_SW0 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1708,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(5),
      O => BU2_N44
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DST_ADDR_BYTE0_MATCH_GND_27_o_MUX_424_o1 : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(3),
      I5 => BU2_N42,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH_GND_27_o_MUX_424_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DST_ADDR_BYTE0_MATCH_GND_27_o_MUX_424_o1_SW0 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1708,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(5),
      O => BU2_N42
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DST_ADDR_BYTE1_MATCH_GND_27_o_MUX_426_o1 : LUT6
    generic map(
      INIT => X"0000000080000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I5 => BU2_N40,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH_GND_27_o_MUX_426_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DST_ADDR_BYTE1_MATCH_GND_27_o_MUX_426_o1_SW0 : LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1708,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_N40
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DST_ADDR_BYTE3_MATCH_GND_27_o_MUX_430_o1 : LUT6
    generic map(
      INIT => X"4000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(3),
      I5 => BU2_N38,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH_GND_27_o_MUX_430_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DST_ADDR_BYTE3_MATCH_GND_27_o_MUX_430_o1_SW0 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1708,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(5),
      O => BU2_N38
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_GND_27_o_MUX_432_o : LUT6
    generic map(
      INIT => X"0000000080000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(2),
      I4 => BU2_N36,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_GND_27_o_MUX_432_o_1710
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_GND_27_o_MUX_432_o_SW0 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1708,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(5),
      O => BU2_N36
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(7),
      I5 => BU2_N34,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv1_1582
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv1_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(6),
      O => BU2_N34
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN13 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11_1705,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12_1706,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(10),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(6),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12_1706
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11 : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(12),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(14),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(13),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(15),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(7),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11_1705
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_7_1 : LUT6
    generic map(
      INIT => X"AAAAAAAB00000001"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2),
      I4 => BU2_N32,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_7_11,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_7_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_7_1_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      O => BU2_N32
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv23 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(12),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(13),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(11),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv23_1703
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv21 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(8),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(10),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0931_inv21_1702
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0848_inv1 : LUT6
    generic map(
      INIT => X"FBFAFAFAFBFAFBFA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0848_inv1_1701
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0856_inv : LUT6
    generic map(
      INIT => X"FFFFFFFFA8AAA8A8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I4 => BU2_N22,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0856_inv_1700
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0856_inv_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      O => BU2_N22
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0834_inv : LUT6
    generic map(
      INIT => X"FFFFAAA8FFFFAAAA"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_1697,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I5 => BU2_N20,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0834_inv_1698
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0834_inv_SW0 : LUT4
    generic map(
      INIT => X"FEFF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      O => BU2_N20
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER : LUT6
    generic map(
      INIT => X"FF00FF55C000C040"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I4 => BU2_N18,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      O => BU2_N18
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o3 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(11),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(10),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(9),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(8),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(7),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o2_1693,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o2 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o1_1692,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o2_1693
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(15),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(14),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(13),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GND_24_o_INV_42_o1_1692
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_3 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(13),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(12),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(14),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(15),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_1_1690,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_Q,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_2 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(8),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(9),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(10),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(11),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_1_1690
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_1 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_24_o_equal_8_o_15_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv3 : LUT6
    generic map(
      INIT => X"AAAAAAAA20000000"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_565,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv2_1688,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(5),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv2 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv2_1688
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0141 : LUT6
    generic map(
      INIT => X"0000000013131353"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1671,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_565,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX,
      I5 => BU2_N16,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0141_1687
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0141_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_310,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_N16
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT165 : LUT4
    generic map(
      INIT => X"F1F0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT161,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT163_1683,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_6_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT164 : LUT6
    generic map(
      INIT => X"FB44EA4451444044"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(38),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(22),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT162_1682,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT163_1683
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT163 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(30),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(46),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT162_1682
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT55 : LUT4
    generic map(
      INIT => X"F1F0"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT51,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT53_1680,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT54 : LUT6
    generic map(
      INIT => X"FB44EA4451444044"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(33),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(17),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT52_1679,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT53_1680
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT53 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(25),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(41),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT52_1679
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT193 : LUT5
    generic map(
      INIT => X"75226422"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(31),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(23),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT192_1678
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT192 : LUT6
    generic map(
      INIT => X"54FF10FF54101010"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(15),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT19,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT191_1677
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT191 : LUT4
    generic map(
      INIT => X"A0CF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(47),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(39),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT19
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT34 : LUT6
    generic map(
      INIT => X"A8FF20FFA8202020"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_Mux_26_o13,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(8),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT32,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0174_inv : LUT6
    generic map(
      INIT => X"FFFFE000FFFF0000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_343,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_308,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I5 => BU2_N14,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0174_inv_311
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0174_inv_SW0 : LUT6
    generic map(
      INIT => X"AA8AAAAAAAAAAAAA"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => BU2_N14
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In13 : LUT6
    generic map(
      INIT => X"FEFA6E2A6E2A6E2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_310,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_308,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In12_1672,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In13_1673,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In11_1548,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In11 : LUT5
    generic map(
      INIT => X"FFFF0010"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1671,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In12_1672
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In12 : LUT5
    generic map(
      INIT => X"F8F05850"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_343,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_308,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_310,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In11_1670,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT105 : LUT4
    generic map(
      INIT => X"7250"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT103,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT101_1668,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_3_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT102 : LUT6
    generic map(
      INIT => X"7776676655544544"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(19),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(27),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT10,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT101_1668
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT101 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(35),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(43),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT10
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT124 : LUT6
    generic map(
      INIT => X"545454545454FE54"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT122_1665,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT121_1666,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT12,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_4_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT123 : LUT6
    generic map(
      INIT => X"4040400000400000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT122_1665
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT121 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(28),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(44),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(36),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(20),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT12
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT144 : LUT6
    generic map(
      INIT => X"545454545454FE54"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT142_1662,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT141_1663,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT14,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT143 : LUT6
    generic map(
      INIT => X"4040400000400000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(5),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT142_1662
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT141 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(29),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(45),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(37),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(21),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT14
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT74 : LUT6
    generic map(
      INIT => X"545454545454FE54"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT72_1659,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT71_1660,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT7,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT73 : LUT6
    generic map(
      INIT => X"4040400000400000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(2),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT72_1659
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT71 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(26),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(42),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(34),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(18),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT7
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv : LUT6
    generic map(
      INIT => X"AAAAAAAA00020000"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I5 => BU2_N8,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv : LUT6
    generic map(
      INIT => X"AAAAAA88AAAAAA80"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_234,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I5 => BU2_N10,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv_251
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv_SW0 : LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      O => BU2_N10
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT4 : LUT6
    generic map(
      INIT => X"1230303030303030"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I1 => BU2_N8,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT4_252
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT4_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      O => BU2_N8
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv2 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I5 => BU2_N6,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv2_SW0 : LUT3
    generic map(
      INIT => X"FD"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      O => BU2_N6
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008142 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008141
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n00811_SW0 : LUT4
    generic map(
      INIT => X"FFF7"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      O => BU2_N2
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0100_inv1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => N1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0100_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_TX_ER_REG1_GND_30_o_MUX_493_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_GND_30_o_MUX_493_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TX_EN_TO_PHY_GND_30_o_MUX_507_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_1649,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_GND_30_o_MUX_507_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TX_ER_TO_PHY_GND_30_o_MUX_509_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_1647,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_GND_30_o_MUX_509_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_EXCEEDED_MIN_LEN_OR_192_o1 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1505,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_1507,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1331,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_EXCEEDED_MIN_LEN_OR_192_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_CRC_ENGINE_ERR_OR_208_o1 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1645,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1500,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1503,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1495,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_CRC_ENGINE_ERR_OR_208_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_CRC_ENGINE_ERR_OR_213_o1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1500,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1645,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_CRC_ENGINE_ERR_OR_213_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_EXTENSION_FIELD_OR_203_o1 : LUT6
    generic map(
      INIT => X"FFFFFFFF4040FF40"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1278,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1288,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1643,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_EXTENSION_FLAG_1293,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_CRC_ENGINE_ERR_OR_213_o,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_EXTENSION_FIELD_OR_203_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o211 : LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o21
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GND_37_o_DATA_LENGTH_CNT_7_equal_1_o_7_1 : LUT5
    generic map(
      INIT => X"00400000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o21,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GND_37_o_DATA_LENGTH_CNT_7_equal_1_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_SFD_FLAG_AND_339_o1 : LUT4
    generic map(
      INIT => X"7770"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1498,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_SFD_FLAG_AND_339_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_1481,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(14),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(14),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o11 : LUT5
    generic map(
      INIT => X"00000001"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable71 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv1 : LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1331,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1643,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_RXD_7_equal_10_o_7_1 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_RXD_7_equal_10_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_NO_FCS_DATA_WITH_FCS_MUX_702_o11 : LUT6
    generic map(
      INIT => X"8888888D88888888"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_CRC_MODE_HELD_1302,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1238,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1643,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO_1494,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_1485,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_DATA_WITH_FCS_MUX_702_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_CONTROL_MATCH_AND_335_o1 : LUT5
    generic map(
      INIT => X"00400000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH_1488,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_CONTROL_MATCH_AND_335_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PWR_38_o_RXD_7_equal_16_o_7_1 : LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PWR_38_o_RXD_7_equal_16_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable3 : LUT4
    generic map(
      INIT => X"FF2A"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_VLAN_MATCH_1_GND_36_o_MUX_732_o11 : LUT6
    generic map(
      INIT => X"F444044404440444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_RXD_7_equal_10_o,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_1_GND_36_o_MUX_732_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_300_o1 : LUT5
    generic map(
      INIT => X"20000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1492,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1301,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_RXD_7_equal_10_o,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_300_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_END_DATA_OR_156_o1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1640,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_END_DATA_OR_156_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_2_GND_35_o_MUX_625_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_2_GND_35_o_MUX_625_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_4_GND_35_o_MUX_623_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_4_GND_35_o_MUX_623_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_3_GND_35_o_MUX_624_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_3_GND_35_o_MUX_624_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_1_GND_35_o_MUX_626_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_1_GND_35_o_MUX_626_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_PWR_37_o_FIELD_CONTROL_5_MUX_622_o11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0001"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1639,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1335,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PWR_37_o_FIELD_CONTROL_5_MUX_622_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_GND_35_o_FIELD_CONTROL_0_MUX_621_o11 : LUT6
    generic map(
      INIT => X"4444444444444440"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1335,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1639,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_GND_35_o_FIELD_CONTROL_0_MUX_621_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DEST_ADDRESS_FIELD_AND_269_o1 : LUT6
    generic map(
      INIT => X"4444444440004040"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1278,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1335,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DEST_ADDRESS_FIELD_AND_269_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_LEN_FIELD_AND_275_o1 : LUT5
    generic map(
      INIT => X"44444000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1639,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_LEN_FIELD_AND_275_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DAT_FIELD_AND_278_o1 : LUT5
    generic map(
      INIT => X"44444000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1638,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1331,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DAT_FIELD_AND_278_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1637,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1636,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT151 : LUT4
    generic map(
      INIT => X"69AA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(14),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_22_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT131 : LUT4
    generic map(
      INIT => X"69AA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(12),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_20_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT251 : LUT4
    generic map(
      INIT => X"69AA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(23),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_31_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT141 : LUT4
    generic map(
      INIT => X"69AA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(13),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_21_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mxor_n0305_xo_0_1 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0305
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mxor_n0298_xo_0_1 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0298
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mxor_n0290_xo_0_1 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0290
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mxor_n0292_xo_0_1 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0292
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1306,
      I1 => N1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mxor_n0314_xo_0_1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0314
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mxor_n0311_xo_0_1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0311
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mxor_n0294_xo_0_1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_n0294
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT11 : LUT6
    generic map(
      INIT => X"E44E4EE44EE4E44E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT111 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(11),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_19_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT181 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(17),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_25_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_REG_23_REG_23_mux_3_OUT241 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(22),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_30_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0085_inv1 : LUT6
    generic map(
      INIT => X"AAAAAAA2AAAAAAA8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0085_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0091_inv1 : LUT6
    generic map(
      INIT => X"2222A2220000A000"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0091_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDC1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_ENABLE_REG_1628,
      O => emacphymclkout
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_408_o1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_408_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_404_o1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_404_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT_xor_0_11 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT_xor_2_11 : LUT4
    generic map(
      INIT => X"1444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT2
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT_xor_1_11 : LUT3
    generic map(
      INIT => X"14"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT41 : LUT6
    generic map(
      INIT => X"1230303030303030"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT4
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT31 : LUT5
    generic map(
      INIT => X"14444444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT3
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_1541,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_TX_OUT_31_OR_226_o1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_1542,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_TX_OUT_31_OR_226_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_MA_OUT_6_PWR_44_o_mux_7_OUT71 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      I1 => hostwrdata_11(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_6_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_MA_OUT_6_PWR_44_o_mux_7_OUT61 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => hostwrdata_11(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_MA_OUT_6_PWR_44_o_mux_7_OUT51 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => hostwrdata_11(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_4_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_MA_OUT_6_PWR_44_o_mux_7_OUT41 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => hostwrdata_11(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_3_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_MA_OUT_6_PWR_44_o_mux_7_OUT31 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => hostwrdata_11(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_MA_OUT_6_PWR_44_o_mux_7_OUT21 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => hostwrdata_11(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_MA_OUT_6_PWR_44_o_mux_7_OUT11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => hostwrdata_11(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_INT_RD_DATA2911 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_Mmux_INT_RD_DATA291
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv1 : LUT5
    generic map(
      INIT => X"FFFF0040"
    )
    port map (
      I0 => hostaddr_10(7),
      I1 => hostaddr_10(8),
      I2 => hostaddr_10(6),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONFIG_RD_WR,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_STATE_VAR_AND_456_o1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_STATE_VAR_1625,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_READY_STATE_VAR_AND_456_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_READY_INT_1624,
      I1 => hostreq,
      I2 => hostmiimsel,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mmux_CONFIG_RD_WR11 : LUT3
    generic map(
      INIT => X"FD"
    )
    port map (
      I0 => hostaddr_10(9),
      I1 => hostmiimsel,
      I2 => hostopcode_9(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONFIG_RD_WR
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT241 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(22),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_30_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT181 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(17),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_25_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT111 : LUT6
    generic map(
      INIT => X"C66C6CC66CC6C66C"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(11),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_19_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT13 : LUT6
    generic map(
      INIT => X"E44E4EE44EE4E44E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mxor_n0294_xo_0_1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0294
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mxor_n0311_xo_0_1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0311
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mxor_n0314_xo_0_1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0314
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mxor_n0290_xo_0_1 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0290
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mxor_n0298_xo_0_1 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0298
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mxor_n0305_xo_0_1 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_n0305
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT141 : LUT4
    generic map(
      INIT => X"69AA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(13),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_21_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT251 : LUT4
    generic map(
      INIT => X"69AA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(23),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_31_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT131 : LUT4
    generic map(
      INIT => X"69AA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(12),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_20_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_REG_23_REG_23_mux_3_OUT151 : LUT4
    generic map(
      INIT => X"69AA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(14),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1616,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_22_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_ACK1 : LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_ACK_IN
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0776_inv1 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0776_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0915_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0998_inv1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0998_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable261 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1578,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_CRC_MODE_GND_27_o_MUX_229_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRC_MODE_582,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_GND_27_o_MUX_229_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_JUMBO_EN_GND_27_o_MUX_231_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_JUMBO_ENABLE_577,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_GND_27_o_MUX_231_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_VLAN_EN_GND_27_o_MUX_233_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_VLAN_ENABLE_579,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_GND_27_o_MUX_233_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_IFG_DEL_EN_GND_27_o_MUX_237_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_IFG_DEL_EN_573,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_GND_27_o_MUX_237_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_REG_PREAMBLE_GND_27_o_MUX_343_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_GND_27_o_MUX_343_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_PAD_PIPE_GND_27_o_MUX_399_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1578,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_GND_27_o_MUX_399_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DST_ADDR_MULTI_MATCH_GND_27_o_MUX_434_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH_GND_27_o_MUX_434_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_REG_SCSH_GND_27_o_MUX_443_o11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_GND_27_o_MUX_443_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_0_7_GND_27_o_mux_54_OUT61 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_0_7_GND_27_o_mux_54_OUT41 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_3_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_0_7_GND_27_o_mux_54_OUT21 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_GND_27_o_MUX_408_o1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID_1602,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_GND_27_o_MUX_408_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT81 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT71 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT61 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT51 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT41 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT31 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT21 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT11 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT_xor_0_11 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT_xor_0_11 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_2_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_2_1_770
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_0_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_0_1_772
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_4_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_4_1_768
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_6_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_6_1_765
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable181 : LUT4
    generic map(
      INIT => X"FF02"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_788,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1601,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT_xor_1_11 : LUT3
    generic map(
      INIT => X"9F"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT_xor_1_11 : LUT3
    generic map(
      INIT => X"9F"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_PREAMBLE_GND_27_o_MUX_341_o11 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_GND_27_o_MUX_341_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_PAD_GND_27_o_MUX_347_o11 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_GND_27_o_MUX_347_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_CRC_GND_27_o_MUX_349_o11 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_GND_27_o_MUX_349_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_CR178124_FIX_GND_27_o_MUX_401_o11 : LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_GND_27_o_MUX_401_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_TX_STATUS_VALID_GND_27_o_MUX_403_o11 : LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_1595,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID_GND_27_o_MUX_403_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_REG_TX_CONTROL_GND_27_o_MUX_439_o11 : LUT5
    generic map(
      INIT => X"00400000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(11),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN1,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL_GND_27_o_MUX_439_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst11 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n075211 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_1592,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1711 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH_1586,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH_1587,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH_1588,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH_1589,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_1590,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_1591,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_BROADCAST
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0888_inv111 : LUT3
    generic map(
      INIT => X"10"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0888_inv11
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv1 : LUT5
    generic map(
      INIT => X"22222220"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_3_1 : LUT5
    generic map(
      INIT => X"FF8A8AFF"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_1559,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_3_1_782
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_FRAME_GOOD_GND_27_o_MUX_286_o111 : LUT6
    generic map(
      INIT => X"2EEE0CCC22220000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_1573,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_1574,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_1583,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_1584,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0888_inv11,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_FRAME_GOOD_GND_27_o_MUX_286_o11
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv2 : LUT4
    generic map(
      INIT => X"A8A0"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv1_1582,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EN1 : LUT5
    generic map(
      INIT => X"FFFFAFAE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_1580,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_1581,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_CRC_COMPUTE_GND_27_o_MUX_383_o11 : LUT3
    generic map(
      INIT => X"54"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1578,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_GND_27_o_MUX_383_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_4_11 : LUT3
    generic map(
      INIT => X"A9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_4_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT_xor_2_11 : LUT4
    generic map(
      INIT => X"A9FF"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT2
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_FCS_GND_27_o_MUX_278_o111 : LUT6
    generic map(
      INIT => X"A888A888A8880000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_1574,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_1573,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_FCS_GND_27_o_MUX_278_o11
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_GND_27_o_MUX_298_o1 : LUT6
    generic map(
      INIT => X"00000000FFEC3320"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_1573,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_1574,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0888_inv11,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_GND_27_o_MUX_298_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_7_1 : LUT4
    generic map(
      INIT => X"E444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(7),
      I2 => N1,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_1572,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_7_1_764
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable141 : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_1572,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable14
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_TRANSMIT_GND_27_o_MUX_345_o11 : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1570,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_GND_27_o_MUX_345_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0912_inv11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1564,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_1565,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_1566,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_1567,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_1568,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0912_inv1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0826_inv1 : LUT6
    generic map(
      INIT => X"FFFFAA80FFFFAA00"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE_575,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_1562,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0826_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0818_inv1 : LUT6
    generic map(
      INIT => X"FFFFAA80FFFFAA00"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE_575,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_1560,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0818_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable11 : LUT6
    generic map(
      INIT => X"FFFFFFFF8A8A8AAA"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1558,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_1559,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_7_11,
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_7_111 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(6),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_7_11
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_27_o_GND_27_o_sub_7_OUT_7_0_xor_5_11 : LUT4
    generic map(
      INIT => X"AAA9"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_REG_PREAMBLE_DONE_GND_27_o_MUX_304_o11 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_GND_27_o_MUX_304_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_TX_GND_27_o_MUX_263_o11 : LUT5
    generic map(
      INIT => X"00000100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_1554,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_GND_27_o_MUX_263_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_CRC_MODE_INV_47_o1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_29_1000,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_CRC_MODE_INV_47_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_Reset_OR_DriverANDClockEnable1 : LUT3
    generic map(
      INIT => X"CE"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_Reset_OR_DriverANDClockEnable
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_GND_26_o_MUX_206_o1 : LUT4
    generic map(
      INIT => X"5410"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => N1,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_570,
      I3 => N0,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_GND_26_o_MUX_206_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_val1 : LUT4
    generic map(
      INIT => X"FF20"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_310,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_565,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_val
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_2_11 : LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_3_11 : LUT4
    generic map(
      INIT => X"6AAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_5_11 : LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(5),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_4_11 : LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_REQ_FROM_RX_GOOD_FRAME_IN_TX_REG_AND_29_o1 : LUT3
    generic map(
      INIT => X"20"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0084_inv11 : LUT5
    generic map(
      INIT => X"AAAA0800"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1552,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0084_inv1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_GOOD_FRAME_IN3_OR_37_o1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2_459,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN3_460,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_461,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_GOOD_FRAME_IN3_OR_37_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N1,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1551,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_310,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N1,
      I1 => clientemacpausereq,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT81 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT71 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT61 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT51 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT41 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT31 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT21 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT11 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_UNDERRUN_OUT11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT_233,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_AVAIL_OUT11 : LUT3
    generic map(
      INIT => X"AC"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_340,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_xor_0_11 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_xor_1_11 : LUT3
    generic map(
      INIT => X"BE"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In111 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In11_1548
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_Mux_26_o131 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_Mux_26_o13
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_xor_2_11 : LUT4
    generic map(
      INIT => X"1444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT2
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_xor_3_11 : LUT5
    generic map(
      INIT => X"14444444"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT3
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_21_o_Mux_26_o11 : LUT6
    generic map(
      INIT => X"5557555755575556"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_REG_342,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_Mux_26_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_xor_4_11 : LUT6
    generic map(
      INIT => X"FFFFFFFF6AAAAAAA"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT4
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_1474,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1544,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1546,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_REQ_LOCAL
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1545,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_1241,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      O => emacclientrxstats_8(24)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_BAD_FRAME_OUT11 : LUT5
    generic map(
      INIT => X"FFFF2000"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1545,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_1474,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1544,
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_COMB
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_xor_2_11 : LUT5
    generic map(
      INIT => X"01101010"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT2
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_xor_1_11 : LUT4
    generic map(
      INIT => X"0110"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT1_258
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT11 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT101 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_3_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT111 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_4_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT121 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT131 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_6_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT141 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_7_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT151 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_8_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT161 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_9_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT21 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_10_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT31 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(11),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_11_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT41 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_12_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT51 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_13_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT61 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(14),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_14_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT71 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(15),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_15_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT81 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(1),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_DATA_COUNT_4_GND_20_o_mux_12_OUT91 : LUT5
    generic map(
      INIT => X"11100100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(2),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_GOOD_FRAME_OUT11 : LUT4
    generic map(
      INIT => X"AA2A"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_1474,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1544,
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1545,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_COMB
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT31 : LUT6
    generic map(
      INIT => X"0110110011001100"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I4 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I5 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT3
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT1 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_1543,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_VLAN_ENABLE_OUT1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_27_999,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_VLAN_ENABLE_OUT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => reset,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_31_1542,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => reset,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_31_1541,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_Mmux_R3_PWR_16_o_MUX_15_o11 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R2_218,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R3_1539,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R3_PWR_16_o_MUX_15_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_Mmux_R3_PWR_16_o_MUX_15_o11 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R2_215,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R3_1537,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R3_PWR_16_o_MUX_15_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_Mmux_R3_PWR_16_o_MUX_15_o11 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R2_212,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R3_1535,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R3_PWR_16_o_MUX_15_o
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RXD81 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxd_3(7),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RXD71 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxd_3(6),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RXD61 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxd_3(5),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RXD51 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxd_3(4),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RXD41 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxd_3(3),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RXD31 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxd_3(2),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RXD21 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxd_3(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RXD11 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxd_3(0),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RX_DV11 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxdv,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_DV_REG1_907,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RX_DV
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_INT_GMII_RX_ER11 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => phyemacrxer,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_ER_REG1_898,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RX_ER
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TX_EN11 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_1534,
      O => emacphytxen
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_Mmux_GMII_TX_ER11 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => corehassgmii,
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER,
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_1533,
      O => emacphytxer
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GND_37_o_DATA_LENGTH_CNT_7_equal_1_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_1507
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_EXCEEDED_MIN_LEN_OR_192_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1505
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_198_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1503
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_MAX_LENGTH_ERR_AND_364_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1495
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_EXTENSION_FIELD_OR_203_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1500
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_SFD_FLAG_AND_339_o,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1498
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ERR : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_CRC_ENGINE_ERR_OR_213_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ERR_1257
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_OUT_OF_BOUNDS_ERR : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1495,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_OUT_OF_BOUNDS_ERR_1240
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_300_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO_1494
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_36_o_RXD_7_equal_10_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1492
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ONE : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_296_o_1489,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ONE_1490
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PWR_38_o_RXD_7_equal_16_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH_1488
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_183_o_1484,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_1485
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_DATA_WITH_FCS_MUX_702_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID_1483
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1278,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_1481
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_CRC_COMPUTE_OR_168_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1480
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_8 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_9 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_10 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_11 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_12 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_13 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0335_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_INT : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_1477,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_INT_1473
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_FRAME : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_1476,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_FRAME_1256
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_1475,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_1241
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_INT_1473,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_1474
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_38_o_AND_331_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_1_GND_36_o_MUX_732_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_0 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_0_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_1 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_1_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_2 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_2_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_3 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_3_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_4 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_4_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_5 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_5_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_6 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_6_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_7 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_7_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_8 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_8_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_9 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_9_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_10 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0347_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_38_o_mux_2_OUT_10_Q,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1239
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_2_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_0_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_1_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_5_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_3_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_4_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_8 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_8_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_6_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_7_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_11 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_9 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_9_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_10 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_10_1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_14 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_12 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_13 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0408_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0357_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_0_Q(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_emacclientrxstats(26),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_emacclientrxstats(26),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_0_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_1_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(0),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_1_rt_1412,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_1_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(0),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_1_rt_1412,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_1_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_2_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(1),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_2_rt_1409,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_2_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(1),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_2_rt_1409,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_2_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_3_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(2),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_3_rt_1406,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_3_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(2),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_3_rt_1406,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_3_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_4_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(3),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_4_rt_1403,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_4_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(3),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_4_rt_1403,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_4_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_5_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(4),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_5_rt_1400,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_5_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(4),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_5_rt_1400,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_5_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_6_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(5),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_6_rt_1397,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_6_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(5),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_6_rt_1397,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_6_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_7_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(6),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_7_rt_1394,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_7_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(6),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_7_rt_1394,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_7_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_8_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(7),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_8_rt_1391,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_8_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(7),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_8_rt_1391,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_8_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_9_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(8),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_9_rt_1388,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_9_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(8),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_9_rt_1388,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_9_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_10_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(9),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_10_rt_1385,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_10_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(9),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_10_rt_1385,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result_10_1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_11_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(10),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_11_rt_1382,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_11_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(10),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_11_rt_1382,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_12_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(11),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_12_rt_1379,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_12_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(11),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_12_rt_1379,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_13_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(12),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_13_rt_1376,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_13_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(12),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_13_rt_1376,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_14_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(13),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_14_rt_1373,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_emacclientrxstats(26),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_lut_0_Q,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_0_Q_1367
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_emacclientrxstats(26),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_lut_0_Q,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_0_Q_1367,
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_rt_1368,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_Q_1364
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_1_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_0_Q_1367,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_rt_1368,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_Q_1364,
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_rt_1365,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_Q_1361
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_2_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_1_Q_1364,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_rt_1365,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_Q_1361,
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_rt_1362,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_Q_1358
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_3_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_2_Q_1361,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_rt_1362,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_Q_1358,
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_rt_1359,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_Q_1355
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_4_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_3_Q_1358,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_rt_1359,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_Q_1355,
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_rt_1356,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_Q_1352
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_5_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_4_Q_1355,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_rt_1356,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_Q_1352,
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_rt_1353,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_Q_1349
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_6_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_5_Q_1352,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_rt_1353,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_Q_1349,
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_rt_1350,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_Q_1346
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_7_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_6_Q_1349,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_rt_1350,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_Q_1346,
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_rt_1347,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_Q_1343
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_8_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_7_Q_1346,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_rt_1347,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_9_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_Q_1343,
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_9_rt_1344,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_9_Q_1340
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_9_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_8_Q_1343,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_9_rt_1344,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_10_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_cy_9_Q_1340,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_DATA_COUNTER_10_0_xor_10_rt_1341,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Result(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_DV_REG6_MUX_599_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_1339
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_ERR_REG5_END_EXT_AND_258_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1337
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DEST_ADDRESS_FIELD_AND_269_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1335
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_LEN_FIELD_AND_275_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1333
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DAT_FIELD_AND_278_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1331
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_END_DATA_OR_156_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1329
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_0 : FDSE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PWR_37_o_FIELD_CONTROL_5_MUX_622_o,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_GND_35_o_FIELD_CONTROL_0_MUX_621_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_1_GND_35_o_MUX_626_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_2_GND_35_o_MUX_625_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_3_GND_35_o_MUX_624_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_4_GND_35_o_MUX_623_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RXD(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VLAN_ENABLE_HELD : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_n0205_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_27_1005,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_VLAN_ENABLE_HELD_1307
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_28_1305,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1306
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_n0205_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_30_1006,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD_1304
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PAUSE_LT_CHECK_HELD : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_n0205_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_24_1003,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PAUSE_LT_CHECK_HELD_1303
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_CRC_MODE_HELD : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_n0205_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_29_1007,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_CRC_MODE_HELD_1302
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_n0205_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_25_1004,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1301
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RX_DV,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_RX_ER,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1_1216
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_FLAG : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_IFG_FLAG_1296,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_FLAG_1297
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_34_o_RX_ERR_REG6_AND_247_o_1294,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1295
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_EXTENSION_FLAG : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GND_32_o_RX_DV_REG6_AND_249_o_1292,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_EXTENSION_FLAG_1293
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FALSE_CARR_FLAG : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG_1290,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FALSE_CARR_FLAG_1291
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1289,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG2_1218
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1287
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1287,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1288
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1277,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1278
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VALID : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_1260,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstatsvld
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1259,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1258,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ERR_1257,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BROADCASTADDRESSMATCH_DELAY,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_FRAME_1256,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_8 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_9 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_10 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_11 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_12 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_13 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_14 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_15 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_16 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(16)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_17 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(17)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_18 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(18)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_19 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_1241,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(19)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_20 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_OUT_OF_BOUNDS_ERR_1240,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(20)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_21 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1239,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(21)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_22 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1238,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(22)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_23 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_1237,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxstats_8(25)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_BROADCASTADDRESSMATCH : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(26),
      A2 => NlwRenamedSig_OI_emacclientrxstats(27),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcastaddressmatch_1043,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_BROADCASTADDRESSMATCH_DELAY
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_7_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_6_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_5_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_4_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_3_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_2_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_1_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_0_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RX_DV : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(26),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG2_1218,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RX_ERR : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(26),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1_1216,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_31 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_31_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(31)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_30 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_30_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(30)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_29 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_29_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(29)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_28 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_28_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(28)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_27 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_27_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(27)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_26 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_26_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(26)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_25 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_25_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(25)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_24 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_24_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(24)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_23_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(23)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_22 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_22_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(22)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_21 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_21_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(21)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_20 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_20_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(20)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_19 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_19_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(19)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_18 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_18_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(18)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_17 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_17_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(17)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_16 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_16_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(16)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_15 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_15_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_14 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_14_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_13 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_13_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_12 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_12_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_11 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_11_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_10 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_10_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_9 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_9_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_8 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_8_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_7_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_6_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_5_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_4_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_3_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_2_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_1_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CLKEN_CE_IN_AND_116_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG_23_REG_23_mux_3_OUT_0_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RECLOCK_RX_CONFIG,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_REG(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_dist_rom0 : LUT3
    generic map(
      INIT => X"21"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_dist_rom1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_dist_rom2 : LUT3
    generic map(
      INIT => X"00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_dist_rom3 : LUT3
    generic map(
      INIT => X"00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_dist_rom4 : LUT3
    generic map(
      INIT => X"00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_dist_rom5 : LUT3
    generic map(
      INIT => X"00"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_dist_rom6 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_dist_rom7 : LUT3
    generic map(
      INIT => X"06"
    )
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0),
      I1 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1),
      I2 => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_special_pause_address_address_byte(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_data_valid_reg_1141
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_0 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_0_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_1 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_1_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_2 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_3 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_3_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_4 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_4_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_5 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_5_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_6 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_6_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_7 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_7_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_8 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_8_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_9 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_9_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_10 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_10_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_11 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_11_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_12 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_12_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_13 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_13_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_14 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_14_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_15 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_15_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_16 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_16_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(16)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_17 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_17_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(17)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_18 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_18_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(18)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_19 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_19_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(19)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_20 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_20_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(20)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_21 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_21_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(21)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_22 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_22_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(22)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_23 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_23_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(23)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_24 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_24_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(24)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_25 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_25_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(25)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_26 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_26_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(26)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_27 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_27_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(27)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_28 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_28_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(28)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_29 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_29_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(29)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_30 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_30_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(30)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_31 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_31_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(31)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_32 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_32_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(32)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_33 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_33_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(33)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_34 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_34_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(34)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_35 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_35_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(35)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_36 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_36_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(36)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_37 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_37_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(37)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_38 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_38_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(38)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_39 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_39_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(39)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_40 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_40_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(40)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_41 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_41_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(41)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_42 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_42_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(42)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_43 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_43_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(43)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_44 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_44_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(44)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_45 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_45_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(45)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_46 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_46_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(46)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift_47 : FDE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_GND_44_o_rx_pause_addr_47_mux_11_OUT_47_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pause_data_shift(47)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcastaddressmatch : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0091_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcastaddressmatch_GND_44_o_MUX_1179_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_broadcastaddressmatch_1043
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pauseaddressmatch : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0091_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pauseaddressmatch_GND_44_o_MUX_1187_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_pauseaddressmatch_1041
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0085_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2_GND_44_o_mux_4_OUT_0_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0085_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2_GND_44_o_mux_4_OUT_1_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0085_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter_2_GND_44_o_mux_4_OUT_2_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_counter(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_specialpauseaddressmatch : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_n0091_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_specialpauseaddressmatch_GND_44_o_MUX_1171_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_addr_filter_top_dynamic_af_gen_dynamic_config_specialpauseaddressmatch_1032
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG1 : FDR
    port map (
      C => hostclk,
      D => phyemacmdin,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG1_1025
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_MIIM_CLK_INT_1028,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_REG_1029
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_TRISTATE : FDSE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_404_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_TRISTATE_COMB_1027,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => emacphymdtri
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG1_1025,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_IN_REG2_1026
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_OUT : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_404_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_OUT_RISING,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => emacphymdout
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT_0 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_408_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT_1 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_408_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT_2 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_408_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT2,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT_3 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_408_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT3,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT_4 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_408_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT4,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT_5 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_MDIO_CLK_MDIO_CLK_REG_AND_408_o,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_Mcount_STATE_COUNT5_1011,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_STATE_COUNT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_0 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_1 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_2 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_3 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_4 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_5 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_6 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_7 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_8 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_9 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_10 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_11 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_12 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_13 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_14 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_15 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(15),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_16 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(16),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(16)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_17 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(17),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(17)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_18 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(18),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(18)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_19 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(19),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(19)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_20 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(20),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(20)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_21 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(21),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(21)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_22 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(22),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(22)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_23 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(23),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(23)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_24 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(24),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(24)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_25 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(25),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(25)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_26 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(26),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(26)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_27 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(27),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(27)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_28 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(28),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(28)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_29 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(29),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(29)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_30 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(30),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(30)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT_31 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_1_INT_W_R_AND_441_o,
      D => hostwrdata_11(31),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(31)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_FC_OUT_29 : FDSE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_FC_CE_1_INT_W_R_AND_444_o,
      D => hostwrdata_11(29),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_in
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_FC_OUT_30 : FDSE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_FC_CE_1_INT_W_R_AND_444_o,
      D => hostwrdata_11(30),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_in
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(29),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_29_1007
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(30),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_30_1006
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(27),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_27_1005
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(25),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_25_1004
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_14_365
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(24),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_24_1003
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(15),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_15_363
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_13_367
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_12_369
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_9_375
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_11_371
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_10_373
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_8_377
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_7_379
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_4_385
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_6_381
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_5_383
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_3_387
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_2_389
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_TX_CE_1_INT_W_R_AND_443_o,
      D => hostwrdata_11(30),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_TX_OUT_31_OR_226_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_30_576
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_1_391
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_RX_CE_2_INT_W_R_AND_442_o,
      D => hostwrdata_11(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_RX1_OUT_31_OR_225_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_0_393
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_TX_CE_1_INT_W_R_AND_443_o,
      D => hostwrdata_11(29),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_TX_OUT_31_OR_226_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_29_1000
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_TX_CE_1_INT_W_R_AND_443_o,
      D => hostwrdata_11(27),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_TX_OUT_31_OR_226_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_27_999
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_INT_TX_CE_1_INT_W_R_AND_443_o,
      D => hostwrdata_11(25),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RESET_TX_OUT_31_OR_226_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_25_572
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_0 : FDE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_0_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_1 : FDE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_1_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_2 : FDE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_3 : FDE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_3_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_4 : FDE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_4_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_5 : FDE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_5_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6 : FDE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_n0319_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT_6_PWR_44_o_mux_7_OUT_6_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_MA_OUT(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_OP_INT_0 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostopcode_9(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_OP_INT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_OP_INT_1 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostopcode_9(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_OP_INT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_0 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_1 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_2 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_3 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_4 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_5 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_6 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_7 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_8 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_9 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_10 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_11 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_12 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_13 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_14 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT_15 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostwrdata_11(15),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_WR_DATA_INT(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT_0 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT_1 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT_2 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT_3 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT_4 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_PHY_AD_INT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT_0 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT_1 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT_2 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT_3 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT_4 : FDRE
    port map (
      C => hostclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REQUEST_MIIM_READY_AND_460_o,
      D => hostaddr_10(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_REG_AD_INT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_0 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_1 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_2 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_3 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_4 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_5 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_6 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_7 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_8 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_9 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_10 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_11 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_12 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_13 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_14 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_15 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(15),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_16 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(16),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(16)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_17 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(17),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(17)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_18 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(18),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(18)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_19 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(19),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(19)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_20 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(20),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(20)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_21 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(21),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(21)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_22 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(22),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(22)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_23 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(23),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(23)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_24 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(24),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(24)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_25 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(25),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(25)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_26 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(26),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(26)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_27 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(27),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(27)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_28 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(28),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(28)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_29 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(29),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(29)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_30 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(30),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(30)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_31 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_RD_DATA_INT(31),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => hostrddata_12(31)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_0 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_1 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_2 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT2,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_3 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT3,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_4 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT4,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT_5 : FDR
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_Mcount_COUNT5,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R4_909,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_COUNT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_DV_REG1 : FDR
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxdv,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_DV_REG1_907
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxd_3(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxd_3(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxd_3(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxd_3(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxd_3(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxd_3(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxd_3(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxd_3(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_ER_REG1 : FDR
    port map (
      C => rxgmiimiiclk,
      D => phyemacrxer,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_ER_REG1_898
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_0_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_1_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_2_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_3_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_4_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_5_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_6_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_7_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_8 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_8_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_9 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_9_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_10 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_10_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_11 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_11_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_12 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_12_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_13 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_13_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_14 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_14_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_15 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_15_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_16 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_16_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(16)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_17 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_17_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(17)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_18 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_18_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(18)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_19 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_19_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(19)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_20 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_20_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(20)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_21 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_21_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(21)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_22 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_22_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(22)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_23_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(23)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_24 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_24_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(24)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_25 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_25_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(25)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_26 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_26_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(26)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_27 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_27_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(27)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_28 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_28_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(28)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_29 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_29_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(29)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_30 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_30_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(30)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_31 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG_23_REG_23_mux_3_OUT_31_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_REG(31)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv,
      D => clientemactxifgdelay_5(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv,
      D => clientemactxifgdelay_5(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv,
      D => clientemactxifgdelay_5(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv,
      D => clientemactxifgdelay_5(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv,
      D => clientemactxifgdelay_5(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv,
      D => clientemactxifgdelay_5(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv,
      D => clientemactxifgdelay_5(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n0774_inv,
      D => clientemactxifgdelay_5(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3 : FDSE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_INV_104_o,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_818
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_8 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_9 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_10 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_11 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_12 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_13 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_14 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n07521,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_795,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_0_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_0_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_3_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_3_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5_Q
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_788,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_2_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_3_1_782,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_4_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_5_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_6_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_27_o_GND_27_o_sub_7_OUT_7_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_0_1_772,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_1_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable14,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_2_1_770,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_3_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable14,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_4_1_768,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_5_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable14,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_6_1_765,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_27_o_mux_54_OUT_7_1_764,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_763,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_BROADCAST,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_761,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL_760,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_8 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_9 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_10 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_11 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_12 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_13 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_14 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_15 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_16 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(16)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_17 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(17)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_18 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(18)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_19 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN_745,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxstats(19)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_8 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_9 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_10 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_11 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_12 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_13 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_14 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_15 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1075_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable18,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable26,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy_0_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv,
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_xor_0_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_93_o_inv,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy_1_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(0),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_xor_1_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(0),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy_2_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(1),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_xor_2_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(1),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT2
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy_3_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(2),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_xor_3_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(2),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT3
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy_4_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(3),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_xor_4_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(3),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT4
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy_5_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(4),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_xor_5_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(4),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT5
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy_6_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(5),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_xor_6_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(5),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT6
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_xor_7_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_cy(6),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT_lut(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT7
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT_0 : FDSE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT_1 : FDSE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT1,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT_2 : FDSE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT2,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_8 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_11 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_9 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_10 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_12 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_13 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_0 : FDSE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_14 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT_0 : FDSE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT_1 : FDSE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT1,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_2 : FDSE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT2,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT5,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT3,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT4,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT6,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1103_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_IFG_COUNT7,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1109_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_emacclientrxstats(26),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_emacclientrxstats(26),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(0),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt_623,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_1_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(0),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt_623,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(1),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt_620,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_2_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(1),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt_620,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(2),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt_617,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_3_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(2),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt_617,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(3),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt_614,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_4_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(3),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt_614,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(4),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt_611,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_5_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(4),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt_611,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(5),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt_608,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_6_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(5),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt_608,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(6),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt_605,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_7_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(6),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt_605,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(7),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt_602,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_8_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(7),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt_602,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(8),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt_599,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_9_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(8),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt_599,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(9),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt_596,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_10_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(9),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt_596,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(10),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt_593,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_11_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(10),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt_593,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(11),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt_590,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_12_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(11),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt_590,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(12),
      DI => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt_587,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_13_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(12),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt_587,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(13),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_rt_584,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRC_MODE : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_CRC_MODE_INV_47_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRC_MODE_582
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_HALF_DUPLEX : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => NlwRenamedSig_OI_emacclientrxstats(26),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_HALF_DUPLEX_580
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_VLAN_ENABLE : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_VLAN_ENABLE_OUT,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_VLAN_ENABLE_579
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_JUMBO_ENABLE : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_30_576,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_JUMBO_ENABLE_577
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_28_574,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE_575
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_IFG_DEL_EN : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_TX_OUT_25_572,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_IFG_DEL_EN_573
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_NUMBER_OF_BYTES : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_Reset_OR_DriverANDClockEnable,
      Q => emacclienttxstats(30)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS : FD
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_GND_26_o_MUX_206_o,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_570
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_BYTECNTSRL : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_emacclientrxstats(27),
      A1 => NlwRenamedSig_OI_emacclientrxstats(27),
      A2 => NlwRenamedSig_OI_emacclientrxstats(27),
      A3 => NlwRenamedSig_OI_emacclientrxstats(26),
      CE => N1,
      CLK => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_REG : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_565,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_REG_566
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_564
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_in,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_0_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv1,
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_0_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv1,
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(0),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_1_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(0),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_1_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(0),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(1),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_2_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(1),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_2_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(1),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(2),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT2
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_3_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(2),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_3_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(2),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(3),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT3
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_4_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(3),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_4_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(3),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(4),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT4
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_5_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(4),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_5_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(4),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(5),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT5
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_6_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(5),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_6_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(5),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(6),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT6
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_7_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(6),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_7_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(6),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(7),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT7
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_8_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(7),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_8_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(7),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(8),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT8
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_9_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(8),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_9_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(8),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(9),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT9
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_10_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(9),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_10_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(9),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(10),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT10
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_11_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(10),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(11),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_11_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(10),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(11),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT11
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_12_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(11),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_12_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(11),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(12),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT12
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_13_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(12),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_13_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(12),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(13),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT13
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_14_Q : MUXCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(13),
      DI => NlwRenamedSig_OI_emacclientrxstats(27),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(14),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_14_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(13),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(14),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT14
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_15_Q : XORCY
    port map (
      CI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(14),
      LI => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(15),
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT15
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT2,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT3,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT4,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT5,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT6,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT7,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_8 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT8,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_9 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT9,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_10 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT10,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_11 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT11,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_12 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT12,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_13 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT13,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_14 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT14,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0074_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT15,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Result(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_val,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_8 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_9 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_10 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_11 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_12 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_13 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_14 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_15 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(15),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_467,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_461
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_TO_TX : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_GOOD_FRAME_IN3_OR_37_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_in
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_n0034_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_REQ_LOCAL,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_464
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_461,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2_459
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2_459,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN3_460
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_8 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_9 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_10 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_11 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_12 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_13 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_14 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_15 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(15),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_16 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(16),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(16)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_17 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(17),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(17)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_18 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(18),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(18)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_19 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(19),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(19)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_20 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(20),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(20)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_21 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(21),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(21)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_22 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(22),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(22)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_23 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(23),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(23)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_24 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(24),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(24)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_25 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(25),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(25)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_26 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(26),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(26)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_27 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(27),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(27)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_28 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(28),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(28)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_29 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(29),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(29)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_30 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(30),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(30)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_31 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX0_OUT(31),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(31)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_32 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_0_393,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(32)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_33 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_1_391,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(33)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_34 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_2_389,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(34)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_35 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_3_387,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(35)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_36 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_4_385,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(36)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_37 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_5_383,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(37)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_38 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_6_381,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(38)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_39 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_7_379,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(39)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_40 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_8_377,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(40)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_41 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_9_375,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(41)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_42 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_10_373,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(42)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_43 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_11_371,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(43)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_44 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_12_369,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(44)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_45 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_13_367,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(45)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_46 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_14_365,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(46)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_47 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0163_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_MANIFGEN_MANAGEN_CONF_RX1_OUT_15_363,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(47)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_8 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(8),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_9 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(9),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_10 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(10),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_11 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(11),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_12 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(12),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_13 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(13),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_14 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(14),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_15 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0167_inv,
      D => clientemacpauseval_6(15),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxdvld,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_344
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_ACK_IN,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_343
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_REG : FDSE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_INV_8_o,
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_REG_342
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_COMB,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => emacclienttxack
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_Mux_26_o,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_340
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_0_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_1_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_2_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_3_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_4_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_5_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_6_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_21_o_wide_mux_25_OUT_7_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0174_inv_311,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0147,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0174_inv_311,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0147,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0174_inv_311,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT2,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0147,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0174_inv_311,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT3,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0147,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0174_inv_311,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT4,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0147,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_310
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1 : FDR
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In1,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_308
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_ACK_OUT : MUXF5
    port map (
      I0 => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_ACK_IN,
      I1 => NlwRenamedSig_OI_emacclientrxstats(26),
      S => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_305,
      O => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_COMB
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0117_inv,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_0_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_1_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_2_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_3_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_4_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_5_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_6_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_7_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_8 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_8_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(8)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_9 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_9_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(9)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_10 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_10_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(10)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_11 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_11_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(11)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_12 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_12_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(12)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_13 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_13_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(13)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_14 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_14_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(14)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_15 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0110_inv_262,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4_GND_20_o_mux_12_OUT_15_Q,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(15)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv_251,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv_251,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT1_258,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv_251,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT2,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv_251,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT3,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv_251,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT4_252,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_0 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxd_4(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_1 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxd_4(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_2 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxd_4(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_3 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxd_4(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_4 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxd_4(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_5 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxd_4(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_6 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxd_4(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_7 : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxd_4(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_0 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxd_7(0)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_1 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxd_7(1)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_2 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxd_7(2)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_3 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxd_7(3)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_4 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxd_7(4)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_5 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxd_7(5)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_6 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxd_7(6)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_7 : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxd_7(7)
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_234,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxdvld
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT : FDRE
    port map (
      C => txgmiimiiclk,
      CE => N1,
      D => clientemactxunderrun,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R4_232,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT_233
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_COMB,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxgoodframe
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT : FDRE
    port map (
      C => rxgmiimiiclk,
      CE => N1,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_COMB,
      R => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R4_230,
      Q => emacclientrxbadframe
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_HALF_DUPLEX_SYNC
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => txgmiimiiclk,
      D => NlwRenamedSig_OI_emacclientrxstats(26),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_SYNC
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_in,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_HALF_DUPLEX_SYNC
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => NlwRenamedSig_OI_emacclientrxstats(26),
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync1,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_SYNC
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_in,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync1
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R2 : FDP
    port map (
      C => rxgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R1_217,
      PRE => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R2_218
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R1 : FDP
    port map (
      C => rxgmiimiiclk,
      D => NlwRenamedSig_OI_emacclientrxstats(26),
      PRE => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_RXGMIIRSTGENEN_SYNC_GMII_MII_RX_RESET_I_R1_217
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R2 : FDP
    port map (
      C => txgmiimiiclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R1_214,
      PRE => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R2_215
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R1 : FDP
    port map (
      C => txgmiimiiclk,
      D => NlwRenamedSig_OI_emacclientrxstats(26),
      PRE => BU2_U0_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_SYNC_GMII_MII_TX_RESET_I_R1_214
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R2 : FDP
    port map (
      C => hostclk,
      D => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R1_211,
      PRE => reset,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R2_212
    );
  BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R1 : FDP
    port map (
      C => hostclk,
      D => NlwRenamedSig_OI_emacclientrxstats(26),
      PRE => reset,
      Q => BU2_U0_TRI_SPEED_TRIMAC_INST_G_SYNC_MGMT_RESET_SYNC_MGMT_RESET_HOST_I_R1_211
    );
  BU2_XST_VCC : VCC
    port map (
      P => NlwRenamedSig_OI_emacclientrxstats(27)
    );
  BU2_XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_emacclientrxstats(26)
    );


-- hds translate_on

end STRUCTURE;

-- synthesis translate_on

