project new single_cbc2_fmc
project set family spartan6
project set device xc6slx16
project set package csg324
project set speed -3

project set "Enable Multi-Threading" "2" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
project set "Enable Multi-Threading" "2" -process "Place & Route"
project set "Enable BitStream Compression" TRUE -process "Generate Programming File"

# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl

# Just list files by hand for now. Can't get addfiles.tcl to work.

#xfile add ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
# IPBus Ethernet for gig_eth_pcs_pma_v11_5
xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
# Add cores for Ethernet
exec cp  ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
exec cp  ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
xfile add ipcore_dir/mac_fifo_axi4.xco

cd ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco  -p coregen.cgp}
cd ..

# Xilinx ISE setup fragment for ipbus core
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd

# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_registers.vhd
xfile add external/opencores_i2c/i2c_master_top.vhd

# Add CBC2 files
xfile add cbc2/firmware/hdl/i2c_master_rtl.vhd
xfile add cbc2/firmware/hdl/slaves.vhd
xfile add cbc2/firmware/hdl/clocks_s6_extphy.vhd
xfile add cbc2/firmware/hdl/ipbus_addr_decode.vhd
xfile add cbc2/firmware/hdl/top_sp605_extphy.vhd
xfile add cbc2/firmware/hdl/cbc2_interface.vhd
xfile add cbc2/firmware/hdl/i2c_trig.vhd

# Add user constraints file
xfile add cbc2/firmware/ucf/sp601_extphy_pc045b_1hybrid.ucf

project close
