FMC MasterFIP issueshttps://ohwr.org/project/fmc-masterfip/issues2019-02-12T11:42:35Zhttps://ohwr.org/project/fmc-masterfip/issues/35Rename ADC_CS net into ADC_CS_N2019-02-12T11:42:35ZProjectsRename ADC_CS net into ADC_CS_NIt is indeed a active low net\!Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/27FieldTR pins 2,6: overshoots2019-02-12T11:42:30ZEvangelia GousiouFieldTR pins 2,6: overshootsWithout having any error in the communication, we have noticed that
there are overshoots on the differential signal from the FielDrive to
the FieldTR, i.e. FieldTR pins 2, 6.
We confirmed the same behavior on the Alstom master
board.
![](/uploads/891535639fe68667cf37baf1d0c73237/overshoots.png)
![](/uploads/f62e57f0c1dfb3cb9c86c0f4a02b4cbc/overshoots_zoomin.png)
The signals on the other side of the FieldTR, the WorldFIp bus side
(i.e. FieldTR pins 5, 3), are
clean.
![](/uploads/92321b0c7fe8a4f87926a6d6824f3581/bus_side.png)
We also contacted Exoligent and they confirmed that they see those
overshoots in their designs (see mail below).
Note that the overshoots appear only on frames emitted by the FieldDrive
(tx frames).
Note also that the part of the masterFIP design that connects the
FielDrive to the FieldTR comes from the original Alstom boards.
-----
From: Guillaume Trannoy \[mailto:guillaume.trannoy@exoligent.com\]
Sent: 11 April 2016 17:52
To: Evangelia Gousiou \<Evangelia.Gousiou@cern.ch\>
Cc: Exoligent - Bruno Lepvraud (bruno.lepvraud@exoligent.com)
\<bruno.lepvraud@exoligent.com\>
Subject: Re: overshoots on FieldTR pins 2,6
Hello Eva,
I have done measurements on one of our FIP device and we experienced the
same behavior. (Sorry for the not really good quality of pictures).
PIN 2, 6 (6: Yellow, 2:Pink, Math:
Violet)
![](/uploads/7b850689494e24603d7e0f6a36a782dc/exol_pin2_6_tx.jpg)
PIN 3, 5 (5: Yellow, 3:Pink, Math:
Violet)
![](/uploads/d6ceddac017acfd1a11c8807f9f59c76/exol_pin3_5_tx.jpg)
Intuitively, I think it is normal because of inductive effect of
FieldTR.
In my case and I think it is the same for you, the FieldDrive emits the
frames. High switching time on the inductance formed by FieldTR causes
the overshoots. And on the network side, signal is filtered by FieldTR
and line.
In case of FieldTR transferring FIP frame to the FielDrive, signal
doesn't show overshoots.
PIN 2-6 in case or receiving FIP
frame:
![](/uploads/006b513f79cc3266104fe1c4249cd3cf/exol_pin2_6_rx.jpg)
The design of FielDrive/FieldTR part I used, is the same as yours in
masterFIP.
I believe that the overshoot could be predict with switching time of the
FielDrive and equivalent electrical circuit. But I think it is a normal
behavior.
I hope it could help you.
Best regards,
Guillaume Trannoy
### Files
* [exol_pin2_6_rx.jpg](/uploads/006b513f79cc3266104fe1c4249cd3cf/exol_pin2_6_rx.jpg)
* [overshoots.png](/uploads/891535639fe68667cf37baf1d0c73237/overshoots.png)
* [overshoots_zoomin.png](/uploads/f62e57f0c1dfb3cb9c86c0f4a02b4cbc/overshoots_zoomin.png)
* [bus_side.png](/uploads/92321b0c7fe8a4f87926a6d6824f3581/bus_side.png)
* [exol_pin2_6_tx.jpg](/uploads/7b850689494e24603d7e0f6a36a782dc/exol_pin2_6_tx.jpg)
* [exol_pin3_5_tx.jpg](/uploads/d6ceddac017acfd1a11c8807f9f59c76/exol_pin3_5_tx.jpg)Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/26Altium hierarchical design2019-02-12T11:42:29ZEvangelia GousiouAltium hierarchical designAdd a top level; despite the fact that it is a simple design and there
are no sheet repetitions, the top level hierarchy would give fast a
overview of the design.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/25OHL copyright dates2019-02-12T11:42:29ZEvangelia GousiouOHL copyright datesChange the OHL "Copyright CERN 2014" to "Copyright CERN 2014-2016"Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/24Simultaneous control of the +5V_SW and -5V2019-02-12T11:42:28ZEvangelia GousiouSimultaneous control of the +5V_SW and -5VTo avoid damaging the ADC, ensure by hardware means that +5V and -5V for
the ADC front end are switched on simultaneously.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/23Replace D8 with a BAV892019-02-12T11:42:28ZEvangelia GousiouReplace D8 with a BAV89to simplify BOMEvangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/21Remove EXT_SYNC_TST_N2019-02-12T11:42:26ZEvangelia GousiouRemove EXT_SYNC_TST_NRemove completely EXT\_SYNC\_TST\_N signal along with associated T1, R1;
initially it was thought of as a way to make the PTS testing of the
board without needing any external pulse generator.
However, as the LEMO is a vital part of the design, checking its
connectivity is important and cannot be replaced by the
EXT\_SYNC\_TST\_N.
Moreover the EXT\_SYNC\_TST\_N could even damage the circuitry if the
transistor is enabled at the same time as pulses are arriving through
the LEMO.
Note also that in the PTS the LEMO is finally tested using the reference
voltage source in the USB relay box, so there is no need for a pulse
generator.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/20Replace 31.25Kbps R29: 332 Ohm 0.1% -> 330 Ohm 1%2019-02-12T11:42:26ZEvangelia GousiouReplace 31.25Kbps R29: 332 Ohm 0.1% -> 330 Ohm 1%The Alstom designs are using 332 Ohm, 1%.
HLP designs are using 330 Ohm, 1%.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/19Front connector isolation or grounding?2019-02-12T11:42:25ZEvangelia GousiouFront connector isolation or grounding?Connect the WorldFIP-cable’s shielding directly to the board’s ground,
or use the capacitor // varistor approach as in the existing Alstom
design?
See attached docs.
### Files
* [CERN-to-Alain-Charoy_WorldFIP.DOCX](/uploads/fa156cb5a8fb77d355245153ceaf3a24/CERN-to-Alain-Charoy_WorldFIP.DOCX)
* [EMC_expert_view.docx](/uploads/d7efb7dad8ff63bbdc3d3c0a227b8e28/EMC_expert_view.docx)
* [emc-extract.ppt](/uploads/6c0cf3406a75fa6a56f41f695fec59a0/emc-extract.ppt)Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/18Remove unused ADC_OUT3, ADC_OUT4 pins from ADC IC2019-02-12T11:42:25ZEvangelia GousiouRemove unused ADC_OUT3, ADC_OUT4 pins from ADC ICAs only two ADC inputs are used in the design, ADC\_OUT3 and ADC\_OUT4
could be removed from routingEvangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/14PCB: narrow vias2019-02-12T11:42:22ZEvangelia GousiouPCB: narrow viasvery narrow vias will be increasing the cost.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/13PCB: plugged vias2019-02-12T11:42:21ZEvangelia GousiouPCB: plugged viasplugged (tented and filled) vias under the ADC increasing the cost.
### Files
* [vias_pcb_cost.txt](/uploads/9d8d39cc199c36f8d82469ef743bbf3a/vias_pcb_cost.txt)Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/11Remove connection to FieldTR primary (RL2)2019-02-12T11:42:20ZEvangelia GousiouRemove connection to FieldTR primary (RL2)Remove RL2; probing on the bus side of the transformer could potentially
damage the board.
Removing RL2 will remove the possibility of diagnosing errors on the
transformer, but those are not frequent (no transformer error in 10
years and hundreds of nodes has been reported; check here \[1\] the list
of all WorldFIP related errors \[1\]; a FielDrive has been found faulty
twice, but so far there is no FieldTR error reported).
\[1\]
https://issues.cern.ch/browse/APS-5388?jql=project%20%3D%20APS%20AND%20component%20%3D%20%22WORD%20FIP%22%20ORDER%20BY%20updated%20DESC%2C%20priority%20DESC%2C%20created%20ASCEvangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/9PCB: ADC_IN1 not length matched2019-02-12T11:42:19ZEvangelia GousiouPCB: ADC_IN1 not length matchedADC\_IN1 is not length matched by ~3 mm:
ADC\_IN1\_P: 17.1 mm
ADC\_IN1\_N: 14.7 mm
In principle the few ps that this difference translates to are not
critical for our signal.
If possible though it will be better routed.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/8Add test points for the power supplies2019-02-12T11:42:19ZEvangelia GousiouAdd test points for the power suppliesAdd Test points for the: +5V
and the: +5V\_SW, -5V, 1V8Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/7LEDs drive2019-02-12T11:42:18ZEvangelia GousiouLEDs driveIn this board, to keep the design simpler we do not use a transistor to
drive the LEDs, differently to other mezzanines/carries.
\- With the FPGA output at "0" the LED is ON and with the limiting
resistor of 120 Ohms, there are 11mA to be sinked by the FPGA pin
(LVCMOS25 with default driving/sinking strength 12mA).
From the LED specs, with If=10mA the intensity of the light is: red: 13
mcd, green: 9 mcd (see picture)
\- With the FPGA output at "1" there is no current flowing as the LED Vf
= 2V, so the LED is OFF.
\- With the FPGA output at "highZ" there is some current flowing
(through the FPGA pin protection diode probably) that slightly lights
the LED (see picture).
### Files
* [masterFIP_LEDs.png](/uploads/abc9c4ee65eaf4b6cfa6255229641175/masterFIP_LEDs.png)Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/5Power supplies naming2019-02-12T11:42:17ZEvangelia GousiouPower supplies namingrename +5V to P5V etc to comply with other boards naming.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/4ADC removal2019-02-12T11:42:16ZEvangelia GousiouADC removalAfter a thorough conversation with experts and WorldFIP users, it was
decided to create a new version without the ADC, so as to decrease
components and maintenance costs and increase reliability.
The V2 version with the ADC will remain available, in case one needs the
ADC diagnostics.
The V3 is a derivation from V2, without the ADC.
### Files
* [masterFIP_ADC.pptx](/uploads/87acdc0f3a6c2ecd72b302bab657187f/masterFIP_ADC.pptx)Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/2Silkscreen2019-02-12T11:42:15ZEvangelia GousiouSilkscreenSilkscreen improvements:
\- On the BOT side write "https://www.ohwr.org/project/fmc-masterfip/"
instead of "https://www.ohwr.org/project/fmc-worldfip/"
\- On the TOP side replace the unfinished elliptical contour of the four
TP with a smaller square
\- On the front panel, write "Fmc-masterFIP" instead of
"Fmc-MasterFIP"
\- "IC14" is hidden behind the componentEvangelia GousiouEvangelia Gousiou