FMC MasterFIP issueshttps://ohwr.org/project/fmc-masterfip/issues2019-02-12T11:42:35Zhttps://ohwr.org/project/fmc-masterfip/issues/34-5V regulator shutdown pin pulled-low2019-02-12T11:42:35ZProjects-5V regulator shutdown pin pulled-lowThe -5V regulator LT1931AES5\#PBF (IC13) shutdown pin is currently
pulled low with a 30k resistor.
This pin is active low. To enable the regulator, a voltage bigger than
2.4V must be applied ([LT1931
datasheet](http://www.linear.com/docs/3921)).
It might not work as the FPGA Vohmin with VADJ=2.5V can be as low as
1.9V in the worse case.
See [Spartan-6 FPGA Data Sheet: DC and Switching
Characteristics](http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf)
pages 8 and 10.
The shutdown pin should be pulled high to +12V instead. As for the 1V8
regulator LT1763IDE-1.8\#PBF (IC9).Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/33ADC input relays are mixed-up2019-02-12T11:42:34ZProjectsADC input relays are mixed-upRL1 connects positive secondary and negative primary.
RL2 connects negative secondary and positive primary.
While it should be:
RL1 connects primary (bus side), positive and negative.
RL2 connects secondary (FIELDRIVE side), positive and negative.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/32-5V supply2019-02-12T11:42:34ZEvangelia Gousiou-5V supplyThe LT1931A with R71: 82K and R70: 30K is giving -5V34 instead of -5V
The calculation noted on the schematics is based on the LT1931 chip, not
the LT1931A.
R70 should in principle be replaced by 33K, but it could be that this
precision is not needed by the ADA4899 chip.
TODO: confirm if -5V34 is within specs for the ADA4899.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/31Rename EXT_SYNC_OE net into EXT_SYNC_OE_N2019-02-12T11:42:33ZEvangelia GousiouRename EXT_SYNC_OE net into EXT_SYNC_OE_NActive low pin\!Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/305V_EN_N_5V pullup2019-02-12T11:42:32ZEvangelia Gousiou5V_EN_N_5V pullupThe pullup R25 on the 5V\_EN\_N\_5V could be placed before the
transceiver IC3, on the net 5V\_EN\_N; like this if 5V\_EN\_N\_5V is '1'
or highZ the +5V\_SW would be OFF.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/29Remove WorldFIP-bus-termination option2019-02-12T11:42:32ZEvangelia GousiouRemove WorldFIP-bus-termination optionAs discussed with the installation team, there is no need to have the
option of adding on-board a WorldFIP termination.
Connecting by mistake the termination or a failure of the relay have a
high risk with the respect to the advantages of having this feature.
Also traces could potentially affect the bus impedance.
TODO: Remove RL3, T2, R15 and TERM\_EN\_N signal.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/28rename board to fmc-masterfip2019-02-12T11:42:31ZEvangelia Gousiourename board to fmc-masterfipit is becoming confusing using for the project both names "masterfip"
and "fmc-worldfip".
"fmc-masterfip" could keep things simpler i thinkEvangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/22Protection diodes for the G6K-2F-Y relays2019-02-12T11:42:27ZEvangelia GousiouProtection diodes for the G6K-2F-Y relaysNo indication of protection diode inside of the G6K-2F-Y-3VDC relays.
Datasheet only mentions polarity but can be critical due to i.e.
internal magnet. So it seems that protection diode is missing and T4 T6
can be damaged.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/17PCB issues2019-02-12T11:42:24ZEvangelia GousiouPCB issues\- impedance of differential pairs on L3 is a bit low (see attached
picture), make tracks wider
\- very narrow vias increasing the cost
\- plugged (tented and filled) vias under the ADC increasing the cost
### Files
* [diff_pairs_l3.png](/uploads/b1aa4a6a11d3f7f777ee3a1e00277a02/diff_pairs_l3.png)
* [EDA-03098-V2-0_calculs_paires_diff.docx](/uploads/2d7526d3ea309046899ce19e51ca43ce/EDA-03098-V2-0_calculs_paires_diff.docx)
* [vias_pcb_cost.txt](/uploads/283b1fef37b78cd4d5d7f582a7920c1c/vias_pcb_cost.txt)https://ohwr.org/project/fmc-masterfip/issues/16Front panel mechanics2019-02-12T11:42:23ZEvangelia GousiouFront panel mechanicsThe hole for the mini-subD connector does not leave space for the side
screws to be inserted; like this the WorldFIP cable cannot be plugged
in.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/15PCB: diff pairs impedence2019-02-12T11:42:23ZEvangelia GousiouPCB: diff pairs impedenceimpedance of differential pairs on L3 is a bit low (see attached
picture), make tracks wider
### Files
* [diff_pairs_l3_saturnV68.png](/uploads/7f07f0b9e6c298a6e7a4cc52dbdca916/diff_pairs_l3_saturnV68.png)
* [EDA-03098-V2-0_calculs_paires_diff.docx](/uploads/199b9314c942fadd3248307ee9d77c40/EDA-03098-V2-0_calculs_paires_diff.docx)Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/12PCB: WorldFIP diff pair routing2019-02-12T11:42:21ZEvangelia GousiouPCB: WorldFIP diff pair routingImprove routing of the differential WorldFIP signal from the front
connector to the FielDrive.
Despite the fact that the WorldFIP signal is slow and on V1 (where
routing is far from symmetrical) we have not faced issues in the testing
environment, better routing would result in a more robust design; the
removal of RL2 (see related issue) would ease the rerouting.
Place C3 next to TR1; place protection diodes D11, D12, D14 next to TR1;
place D1, D2 next to IC14.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/10RL1 control2019-02-12T11:42:20ZEvangelia GousiouRL1 controlChange the behavior of the relay control so that:
highZ: relay OFF
0: relay OFF
1: relay ON
Therefore put NMOS in place of PMOS.Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/6PCB: L3 island of 3V3 surrounded by -5V2019-02-12T11:42:17ZEvangelia GousiouPCB: L3 island of 3V3 surrounded by -5VEvangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-masterfip/issues/3Position of the front panel LEDs2019-02-12T11:42:16ZEvangelia GousiouPosition of the front panel LEDsIn the 15 V3 boards the front panel LEDs were protruding a bit; this was
bringing a slight misalignment on the screw holes of the front panel and
was making the screwing of the front panel slightly difficult.
As Betty Magnin pointed out this is due to the tolerance of the body of
the LEDs and moreover to the position of the LEDs in the PCB.
Note that the position of the LEDs is exactly the same as in V1; in V1
we had not noticed any issues as by chance the assembler was
systematically pushing the LEDs to the rear when mounting them.
Betty Magnin suggested a modification of the PCB design to move the LEDs
more inside the board.Evangelia GousiouEvangelia Gousiou