ADC CLK - might need connecting to better clock source
In operation mode the same clock should be used for all FMC FSIs (ADCs) in the entire DIOT crate, thus the ADC_CLK will be provided via the FMC connector. The ADC_CLK is currently connected to FmcClkM2c_p/n0. This PINs are in turn connected to FPGA of the DIOT Peripheral/Application FM Carrier board. The clock provided by FPGA will have some jitter that might (or might not) affect the overall accuracy of the measurement. This needs to be evaluated.
The cleanest clock is provided by the DIOT Peripheral/Application FM Carrier board to the FMC board (i.e. FSI FMC) on CLK_BIDIR2 i 3, see schematics, so this one would be the best to be used for the ADC_CLK input. However, this would require HP FMC connector. In this case, the ADC_CLK_p/n input to the ADC should be connected to FmcClkM2c_p/n0 pins FMC_CLK_BIDIR_p/n2 (k4 &k5) or FMC_CLK_BIDIR_p/n3 (j2 &j3)