Add plane cutouts to the OPA857 inputs
The OPA857 TIAs have strict constraints on the input capacitance to reach the 100MHz BW (1.5pF, including the PIN diode). The ground planes around and above the outputs of the PIN diodes have to be removed to minimize the parasitic capacity at the input of the TIAs. The layout as it is, has a parasitic capacity of 0.99pF; this way that figure can drop down to 0.7pF. Then there's the capacitance of the PIN diode itself that's a bit high but that's a different issue on itself.