From:	Carlos Gil Soriano
Sent:	04 May 2012 16:57
To:	Erik Van Der Bij
Subject:	Re: PTS for the FMC-DIO-5chTTLa board
Attachments:	scea010.pdf; family.lvt.specification.pdf

Hi Erik, 
 
Please feel attached a couple of documents about LVT family, predecessor of ABT logic (5V) 
family and ancestor of LVTH. All of these logic family are bus oriented, so it makes sense that 
they are capable of driving 50 ohms. Something heavier that can drive upto 25 ohms will go to 
BCT family. This later one was used in CTRV and CONV-TTL-BLO took that driver with the 
resistor consideration in OE for antiglitch feature. That's the general picture we should keep in 
mind for the outputs. 
 
LVT family 
Well, it is not good working in the brink of a whisker. It is better to take a look to the NXP 
datasheet about the LVT family, because the specify more conditions on the maximum rating for 
the ouput (duty cycle and frequency). The application is totally unknown for me, so I cannot 
guarantee that the output will be compliant with more restrictive specifications as shown in NXP 
datasheet. 
If load concern is the case, BCT would be the solution. 
 
LVTH family 
It seems that LVTH family is definitely the glitch-free family we're looking for. This family 
combined with the redundant antiglitch resistor in OE will make the outputs rock-solid. If I had 
to choose a component with no legacy components within a previous stock I wouldn't hesitate to 
use it. 
 
[!] Attention should be taken to changes in rise-fall times when changing between logic families. 
 
Hope that helps. 
 
Regards, 
Carlos 
 
On 05/04/2012 03:56 PM, Erik Van Der Bij wrote: 
Hi Richard,

-----Original Message-----
From: Richard [mailto:rcarrillo@sevensols.com]
Sent: 04 May 2012 13:51
To: Erik Van Der Bij
Cc: eduardo@sevensols.com; Javier Serrano
Subject: RE: PTS for the FMC-DIO-5chTTLa board

Hi Erik,

Hi Richard,

These are the specifications for the output:
•Output levels: LVTTL, capable of driving +3.3 V over 
a 50-Ohm load.
Yes, (if fulfills the requirement by a whisker according to the
recommendations of the current-driver datasheet) but it actually 
does.

** At power-up the outputs should be in Hi-Z state **
Actually they are not, at least no in the board that I’m using 
now.

•Withstands a continuous short-circuit on all the 
outputs at the same
time
Well, no according to the “recommended operating conditions” of 
the driver.
The datasheets specifies a maximum recommended output current of 
32mA
(since we have 2 drivers per port it is 64mA). But it doesn’t 
mention anything
about “withstanding short-circuit”.

- Can you tell me more specifically why the 10K is 
not enough?
When setting the output enable lines to a high state, some 
current is
consumed towards the SPEC, I guess that it is because of the 
input current
required to set the FPGA pins to a high state when it is 
unconfigured, but I
would need to have a look at the SPEC schematics.


Actually there are two G* inputs of the SN74LVT125D on this single pull-up. 
Each total 0.1mA would give already a drop of 1V over 10K.
Then again, the datasheet gives an Ii of 1uA only... so it should come from 
the Xilinx then.
Carlos: as you know the unconfigured state better, do you know what input 
current it can draw?

- What's the voltage you measure on the G* lines with 
10K and with 4k7?
When the FPGA is unconfigured:
About 1.1V with 10K resistors
About 2.2V with 4K7 resistors (the recommended minimum VIH 
according to
the driver’s datasheet is 2V)

- Would 4k7 give enough margin?
In the board that I’m testing now yes. But it would probably be 
advisable to
calculate this value considering the specified maximum current 
required to
set these lines high according to the FPGA and driver’s 
datasheets.

It seems to be on the limit. Let's also look what other R values we have 
already on the board to not complicated the design.
2k2 seems to be a good candidate. 0.5mA * 5 is what it will take extra. 2.5mA 
* 3V = 7.5mW, seems OK :-)


- Are you really sure that the SN74LVT125D doesn't go 
into tri-state
and that there is no other problem?
I have used external pull-ups resistors (100R) to try to set the 
board ports to
3.3V, however, their state didn’t become high until I reduced the 
value of
the pull-up resistors of the output-enable lines.

- Can you verify if the "Withstands a continuous 
short-circuit on all
the outputs at the same time" is true? I'll pay the 
repair if needed.
Do you mean empirically? Even if the board doesn’t suffer any 
apparent
damage at the beginning, it doesn’t mean that it is not working 
stressed.
I think that it would be advisable to always comply with the 
“recommended
operating conditions” of the driver. So, what I can do is measure 
the port-
short-circuit current to see if it is clearly higher than the 
recommended
maximum current of the driver.

So this means that with the current design and a test 
description to
put first the cable (before startup) and disconnect 
after test 5, it will work.
Dependent on your answers at the top, you may correct 
the value of the
resistors.

I can repeat the measurements with another fmcdio5chttla board to 
provide
more reassurance on this point If you want.

Thanks for all those measurements. After checking the Ii of a Xilinx that it 
corresponds to what we expect, I think the 2k2 would be OK.

Best regards,
	Erik
 
Cheers,
Richard