FMC DIO 5ch TTL a issueshttps://ohwr.org/project/fmc-dio-5chttla/issues2019-02-15T22:06:29Zhttps://ohwr.org/project/fmc-dio-5chttla/issues/20Some FMC pins are not labeled in schematics2019-02-15T22:06:29ZLuigi CalligarisSome FMC pins are not labeled in schematicsIn the EDA-02408-V2-0 schematics,
![schematics summary](/uploads/d6f0f268864ff2dbe4cce3d7445e7bd4/Screenshot_20190215_195159.png)
![schematics FMC detail](/uploads/2dfd82133c194d22588d99508327b30d/Screenshot_20190215_195144.png)
the FMC lane names for some signals are not made explicit. While considering that the naming of these signals should be changed for consistency, see [Issue 19](https://www.ohwr.org/project/fmc-dio-5chttla/issues/19), in the current configuration I suggest the following mapping, resolved from the column/row labels of the FMC:
IN4_P = H10 = LA04_P
IN4_N = H11 = LA04_N
IN3_P = H13 = LA07_P
IN3_N = H14 = LA07_N
IN2_P = G12 = LA08_P
IN2_N = G13 = LA08_N
IN1_P = H31 = LA28_P
IN1_N = H32 = LA28_N
IN0_P = G30 = LA29_P
IN0_N = G31 = LA29_N
https://ohwr.org/project/fmc-dio-5chttla/issues/19IN/OUT labels between schematics and hardware note are inconsistent2019-02-15T22:05:35ZLuigi CalligarisIN/OUT labels between schematics and hardware note are inconsistentIn the dio_hw.pdf hardware note,
![Figure 3.1](/uploads/86683d36161768757d728fc369c7a183/Screenshot_20190215_193428.png)
in Figure 3.1 the input comparator is shown to be driving the DIFF_IN signals, and the output buffer is shown to be driven by the DIFF_OUT differential signals. This is probably the most sensible assignment from the point of view of the function the device is going to play: to output a signal into the LEMO connector or to receive an input signal from the LEMO connector.
In the EDA-02408-V2-0 schematics, instead,
![schematics](/uploads/2c23a4aa655abf3164eaf67bd6d1d9b7/Screenshot_20190215_193456.png)
the input comparator is driving the OUTXY_P/OUT_XY_N differential signals, and the output buffer is shown to be driven by the INXY_P/IN_XY_N. This latter signal assignment is, further, inconsistent with the output enable negation signals (OEXY_N) that enable the output buffer.https://ohwr.org/project/fmc-dio-5chttla/issues/21PROTECT line is powered by signal inputs2021-01-29T10:27:59ZPeter JansweijerPROTECT line is powered by signal inputsInput signals are protected by two protection diodes. This is okay!
However, the upper protection diode is clamped to the I/O over-voltage protection bias circuit build around a zener diode which is fed by 12 V. This means that the 12V line is indirectly powered by the input signals when the 12V is absent which typically is the case at power-up.
The above issue causes trouble when the DIO is plugged onto a board that has a power converter with under voltage lockout protection (UVLO) since these converters reset their UVLO fault latch when the input voltage dropped under the UVLO threshold.
Work-around:
1) Plug the DIO but do not connect DIO input signals.
2) Power the system
3) Plug input signals into DIO.https://ohwr.org/project/fmc-dio-5chttla/issues/3IC11 separation2019-02-12T09:55:07ZPiotr MiedzikIC11 separationFMC Carrier should read EEPROM and check/validate module before enabling
12P0V, 3P3V and VADJ.
Therefore IC11 should not be connected directly to Management (I2C, GA0,
GA1).
PCA9306 like buffers are required.
IC11 is a DAC5578SRGE directly connected to (I2C, GA0, GA1), while it is
powered by P3V3 that may not be present.
See page 5 of
https://edms.cern.ch/ui/file/1250230/1/EDA-02408-V2-0_sch.pdfhttps://ohwr.org/project/fmc-dio-5chttla/issues/2Default FRU file2019-02-12T09:55:06ZPiotr MiedzikDefault FRU filehttps://ohwr.org/project/fmc-dio-5chttla/issues/1EEPROM type not compatible with VITA 57.12019-02-12T09:55:06ZDimitris LampridisEEPROM type not compatible with VITA 57.1In order to comply with VITA 57.1 standard, the FMC EEPROM needs to be
changed to 24C02.