- 26 Jul, 2019 1 commit
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Miguel Jimenez Lopez authored
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- 11 Jul, 2019 1 commit
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Miguel Jimenez Lopez authored
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- 03 Apr, 2019 31 commits
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Javier Díaz authored
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Javier Díaz authored
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Benoit Rat authored
The first channel is set with 0 so that we force it to be output mode p/P & i/I mode will be only available for ch0, and D,d,1,0 will not be working (they will be seen as p/P).
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Miguel Jimenez Lopez authored
- OUT is enable when one pulse occurs or 1-PPS ch0 signal is enable. - TERM enable when any resistor termination channel is enable
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Miguel Jimenez Lopez authored
dio: Added DIO ch0 input support and hold DIO ch0 output as 1-PPS dedicated signal. Deleted PPS mode in DIO core
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Benoit Rat authored
We have remove all connections (input and output) of first channel to the DIO. In the future we might re-add the input connection...
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Grzegorz Daniluk authored
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Benoit Rat authored
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Benoit Rat authored
Create the a new inout register to setup default value. use it instead of GPIO register for O_E_N and TERM_E.
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Grzegorz Daniluk authored
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Javier Diaz authored
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Tomasz Wlostowski authored
wrsw_dio/pulse_gen_pl: removed 1-subtraction from the pulse start time, which was calculated incorrectly for timestamps with cycles value == 0. Now the subtraction is done in the NIC driver
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Javier Díaz authored
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Javier Díaz authored
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Javier Díaz authored
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Javier Díaz authored
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Javier Díaz authored
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Javier Díaz authored
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Javier authored
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
wrsw_dio.vhd: fixed wrong address decoding (included most significant bits which should be masked out)
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Rafael Rodriguez authored
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Rafael Rodriguez authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Rafael Rodriguez authored
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Rafael Rodriguez authored
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Rafael Rodriguez authored
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Rafael Rodriguez authored
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Rafael Rodriguez authored
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Rafael Rodriguez authored
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- 26 Mar, 2019 1 commit
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Maciej Lipinski authored
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