This latch provokes false interrupts in the DIO channel 4 for some bitstreams.

- Legacy NIC/DIO

This design instantiates the NIC and DIO cores externally.
The WRPC fabric interface is connected to a fabric redirector core to allow the interconnection of a NIC module together with an Etherbone one.

- DIO design with only NIC capabilities.
- DIO design with only Etherbone capabilities.

The first channel is set with 0 so that we force it to be output mode
p/P & i/I mode will be only available for ch0, and D,d,1,0 will not be
working (they will be seen as p/P).

- OUT is enable when one pulse occurs or 1-PPS ch0 signal is enable.
- TERM enable when any resistor termination channel is enable

dio: Added DIO ch0 input support and hold DIO ch0 output as 1-PPS dedicated signal. Deleted PPS mode in DIO core

We have remove all connections (input and output) of first channel to the DIO.
In the future we might re-add the input connection...

Create the a new inout register to setup default value.
use it instead of GPIO register for O_E_N and TERM_E.

wrsw_dio/pulse_gen_pl: removed 1-subtraction from the pulse start time, which was calculated incorrectly for timestamps with cycles value == 0. Now the subtraction is done in the NIC driver

wrsw_dio.vhd: fixed wrong address decoding (included most significant bits which should be masked out)