Commit e58dc553 authored by Miguel Jimenez Lopez's avatar Miguel Jimenez Lopez

Fix indentation.

parent ea659890
Subproject commit f0519a1f5f7f2261b861e6a6d4562e2bec875fb4
Subproject commit 4e5e3dfc01e395a81d9403bd1e150560972685f7
-------------------------------------------------------------------------------
-- Entity: dummy_time
-- File: dummy_time.vhd
-- Description: ¿?
-- Author: Javier Diaz (jdiaz@atc.ugr.es)
-- Date: 8 March 2012
-- Version: 0.01
-- To do:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-- -----------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details. You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it from
-- http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity: dummy_time
-- File: dummy_time.vhd
-- Description: ¿?
-- Author: Javier Diaz (jdiaz@atc.ugr.es)
-- Date: 8 March 2012
-- Version: 0.01
-- To do:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-- -----------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details. You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it from
-- http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
entity dummy_time is
port(clk_sys : in std_logic; -- data output reference clock 125MHz
rst_n : in std_logic; -- system reset
-- utc time in seconds
tm_utc : out std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles : out std_logic_vector(27 downto 0));
end dummy_time;
architecture Behavioral of dummy_time is
signal OneSecond : std_logic;
signal init_time : std_logic;
signal tm_cycles_Aux : std_logic_vector(27 downto 0);
signal tm_utc_Aux : std_logic_vector(39 downto 0);
constant MaxCountcycles1 : std_logic_vector(27 downto 0) := "0111011100110101100100111111"; --125.000.000-1
constant MaxCountcycles2 : std_logic_vector(27 downto 0) := "0111011100110101100101000000"; --125.000.000
constant AllOnesUTC : std_logic_vector(39 downto 0) := (others => '1');
begin
---------------------------------------
-- Process to count cycles in a second
---------------------------------------
P_CountTM_cycles :
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_cycles_Aux <= (others => '0');
oneSecond <= '0';
init_time <= '0';
elsif(rising_Edge(Clk_sys)) then
if (Tm_cycles_Aux /= MaxCountcycles2) then
tm_cycles_Aux <= tm_cycles_Aux + 1;
else
tm_cycles_Aux <= (others => '0');
end if;
if(Tm_cycles_Aux = MaxCountcycles1) then
OneSecond <= '1';
else
OneSecond <= '0';
end if;
init_time <= '1';
end if;
end process P_CountTM_cycles;
P_CountTM_UTC :
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_utc_Aux <= (others => '0');
elsif(rising_edge(Clk_sys)) then
if (OneSecond = '1') then
if (tm_utc_Aux /= AllOnesUTC) then
tm_utc_Aux <= tm_utc_Aux + 1;
else
tm_utc_Aux <= (others => '0');
end if;
end if;
end if;
end process P_CountTM_UTC;
tm_cycles <= tm_cycles_Aux when init_time = '1' else (others => '1');
tm_utc <= tm_utc_Aux when init_time = '1' else (others => '1');
entity dummy_time is
port(clk_sys : in std_logic; -- data output reference clock 125MHz
rst_n: in std_logic; -- system reset
-- utc time in seconds
tm_utc : out std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles : out std_logic_vector(27 downto 0));
end dummy_time;
architecture Behavioral of dummy_time is
signal OneSecond: std_logic;
signal init_time: std_logic;
signal tm_cycles_Aux: std_logic_vector(27 downto 0);
signal tm_utc_Aux: std_logic_vector(39 downto 0);
constant MaxCountcycles1: std_logic_vector(27 downto 0) :="0111011100110101100100111111"; --125.000.000-1
constant MaxCountcycles2: std_logic_vector(27 downto 0) :="0111011100110101100101000000"; --125.000.000
constant AllOnesUTC: std_logic_vector(39 downto 0):=(others=>'1');
begin
---------------------------------------
-- Process to count cycles in a second
---------------------------------------
P_CountTM_cycles:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_cycles_Aux <= (others=>'0');
oneSecond <= '0';
init_time <= '0';
elsif(rising_Edge(Clk_sys)) then
if (Tm_cycles_Aux /= MaxCountcycles2) then
tm_cycles_Aux <= tm_cycles_Aux + 1;
else
tm_cycles_Aux <= (others=>'0');
end if;
if(Tm_cycles_Aux = MaxCountcycles1) then
OneSecond <= '1';
else
OneSecond <= '0';
end if;
init_time <= '1';
end if;
end process P_CountTM_cycles;
P_CountTM_UTC:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_utc_Aux <= (others=>'0');
elsif(rising_edge(Clk_sys)) then
if (OneSecond='1') then
if (tm_utc_Aux /= AllOnesUTC) then
tm_utc_Aux <= tm_utc_Aux + 1;
else
tm_utc_Aux <= (others=>'0');
end if;
end if;
end if;
end process P_CountTM_UTC;
tm_cycles <= tm_cycles_Aux when init_time = '1' else (others=>'1');
tm_utc <= tm_utc_Aux when init_time = '1' else (others=>'1');
end Behavioral;
end Behavioral;
......@@ -27,111 +27,107 @@
-- http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
entity immed_pulse_counter is
generic (
-- reference clock frequency
pulse_length_width : integer := 28
);
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic; -- asynchronous system reset
pulse_start_i : in std_logic; -- asynchronous strobe for pulse generation
pulse_length_i : in std_logic_vector(pulse_length_width-1 downto 0); -- asynchronous signal
clk_i : in std_logic;
rst_n_i : in std_logic; -- asynchronous system reset
pulse_start_i : in std_logic; -- asynchronous strobe for pulse generation
pulse_length_i : in std_logic_vector(pulse_length_width-1 downto 0); -- asynchronous signal
pulse_output_o : out std_logic
);
);
end immed_pulse_counter;
architecture rtl of immed_pulse_counter is
-- Internal registers to hold pulse duration
signal counter : unsigned (pulse_length_width-1 downto 0);
-- Signals for states
type counter_state is (WAIT_ST, COUNTING);
signal state : counter_state;
signal state : counter_state;
-- Signal for synchronization (in fact they are not so necessary for current system...)
signal pulse_start_d0, pulse_start_d1, pulse_start_d2, pulse_start_d3 : std_logic;
signal nozerolength, nozerolength_aux : boolean;
-- Aux
constant zeros : std_logic_vector(pulse_length_width-1 downto 0) := (others=>'0');
begin -- architecture rtl
signal pulse_start_d0, pulse_start_d1, pulse_start_d2, pulse_start_d3 : std_logic;
signal nozerolength, nozerolength_aux : boolean;
-- Aux
constant zeros : std_logic_vector(pulse_length_width-1 downto 0) := (others => '0');
begin -- architecture rtl
synchronization: process(clk_i, rst_n_i)
synchronization : process(clk_i, rst_n_i)
begin
if (rst_n_i='0') then
pulse_start_d0 <='0';
pulse_start_d1 <='0';
pulse_start_d2 <='0';
pulse_start_d3 <='0';
elsif rising_edge(clk_i) then
pulse_start_d0<=pulse_start_i;
pulse_start_d1<=pulse_start_d0;
pulse_start_d2<=pulse_start_d1;
pulse_start_d3<=pulse_start_d2;
nozerolength_aux<=pulse_length_i/=zeros;
if (pulse_start_d2='1' and pulse_start_d1='0') then
nozerolength<=nozerolength_aux;
end if;
end if;
end process;
if (rst_n_i = '0') then
pulse_start_d0 <= '0';
pulse_start_d1 <= '0';
pulse_start_d2 <= '0';
pulse_start_d3 <= '0';
elsif rising_edge(clk_i) then
pulse_start_d0 <= pulse_start_i;
pulse_start_d1 <= pulse_start_d0;
pulse_start_d2 <= pulse_start_d1;
pulse_start_d3 <= pulse_start_d2;
nozerolength_aux <= pulse_length_i /= zeros;
if (pulse_start_d2 = '1' and pulse_start_d1 = '0') then
nozerolength <= nozerolength_aux;
end if;
end if;
end process;
state_process : process(clk_i, rst_n_i)
begin
if (rst_n_i='0') then
counter <=(others=>'0');
state <=WAIT_ST;
elsif rising_edge(clk_i) then
if (rst_n_i = '0') then
counter <= (others => '0');
state <= WAIT_ST;
elsif rising_edge(clk_i) then
case state is
when WAIT_ST =>
if pulse_start_d3='1' and nozerolength then
state <=COUNTING;
counter <=unsigned(pulse_length_i)-1;
else
state<=WAIT_ST;
end if;
if pulse_start_d3 = '1' and nozerolength then
state <= COUNTING;
counter <= unsigned(pulse_length_i)-1;
else
state <= WAIT_ST;
end if;
when COUNTING =>
if (counter=0) then
state <= WAIT_ST;
else
state <= COUNTING;
counter<=counter-1;
end if;
if (counter = 0) then
state <= WAIT_ST;
else
state <= COUNTING;
counter <= counter-1;
end if;
when others =>
state<=WAIT_ST;
state <= WAIT_ST;
end case;
end if;
end process;
end if;
end process;
output_process:process(counter, state)
output_process : process(counter, state)
begin
if (rst_n_i='0') then
pulse_output_o <='0';
else
if (rst_n_i = '0') then
pulse_output_o <= '0';
else
case state is
when WAIT_ST =>
pulse_output_o <='0';
when WAIT_ST =>
pulse_output_o <= '0';
when COUNTING =>
pulse_output_o <='1';
pulse_output_o <= '1';
when others =>
pulse_output_o <='0';
end case;
pulse_output_o <= '0';
end case;
end if;
end process;
end process;
end architecture rtl;
......@@ -39,7 +39,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen_pl is
generic (
-- reference clock frequency
g_ref_clk_rate : integer := 125000000);
......@@ -96,10 +96,10 @@ architecture rtl of pulse_gen_pl is
signal trig_valid_ref_p1 : std_logic;
-- Aux
constant zeros : std_logic_vector(27 downto 0) := (others => '0');
signal counter : unsigned (27 downto 0);
signal nozerolength : boolean;
constant zeros : std_logic_vector(27 downto 0) := (others => '0');
signal counter : unsigned (27 downto 0);
signal nozerolength : boolean;
begin -- architecture rtl
-- Get trigger time into internal registers
......@@ -215,5 +215,5 @@ begin -- architecture rtl
end if;
end if;
end process gen_out;
end architecture rtl;
......@@ -6,7 +6,7 @@
-- Author : Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-07-25
-- Last update: 2012-07-25
-- Last update: 2019-08-27
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -33,32 +33,32 @@ entity wr_dio is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
);
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_onewire_b : inout std_logic;
dio_sdn_n_o : out std_logic;
dio_sdn_ck_n_o : out std_logic;
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic;
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic;
dio_ga_o : out std_logic_vector(1 downto 0);
dio_int : out std_logic;
tm_time_valid_i : in std_logic;
tm_seconds_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_onewire_b : inout std_logic;
dio_sdn_n_o : out std_logic;
dio_sdn_ck_n_o : out std_logic;
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic;
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic;
dio_ga_o : out std_logic_vector(1 downto 0);
dio_int : out std_logic;
tm_time_valid_i : in std_logic;
tm_seconds_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
-------------------------------------------------------------------------------
-- Wishbone bus
......@@ -73,15 +73,15 @@ entity wr_dio is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
-- Debug signals for chipscope
TRIG0 : out std_logic_vector(31 downto 0);
TRIG1 : out std_logic_vector(31 downto 0);
TRIG2 : out std_logic_vector(31 downto 0);
TRIG3 : out std_logic_vector(31 downto 0)
TRIG0 : out std_logic_vector(31 downto 0);
TRIG1 : out std_logic_vector(31 downto 0);
TRIG2 : out std_logic_vector(31 downto 0);
TRIG3 : out std_logic_vector(31 downto 0)
);
end wr_dio;
);
end wr_dio;
architecture rtl of wr_dio is
......@@ -111,10 +111,10 @@ architecture rtl of wr_dio is
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic;
dio_ga_o : out std_logic_vector(1 downto 0);
dio_ga_o : out std_logic_vector(1 downto 0);
tm_time_valid_i : in std_logic;
tm_seconds_i : in std_logic_vector(39 downto 0);
tm_seconds_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
TRIG0 : out std_logic_vector(31 downto 0);
......@@ -122,18 +122,18 @@ architecture rtl of wr_dio is
TRIG2 : out std_logic_vector(31 downto 0);
TRIG3 : out std_logic_vector(31 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
dio_int : out std_logic
);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
dio_int : out std_logic
);
end component; --DIO core
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
-------------------------------------------------------------------------------
begin
U_WRAPPER_DIO : xwr_dio
begin
U_WRAPPER_DIO : xwr_dio
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity)
......@@ -143,39 +143,39 @@ U_WRAPPER_DIO : xwr_dio
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
dio_clk_i => dio_clk_i,
dio_pps_i => dio_pps_i,
dio_in_i => dio_in_i,
dio_out_o => dio_out_o,
dio_oe_n_o => dio_oe_n_o,
dio_term_en_o => dio_term_en_o,
dio_clk_i => dio_clk_i,
dio_pps_i => dio_pps_i,
dio_in_i => dio_in_i,
dio_out_o => dio_out_o,
dio_oe_n_o => dio_oe_n_o,
dio_term_en_o => dio_term_en_o,
dio_onewire_b => dio_onewire_b,
dio_sdn_n_o => dio_sdn_n_o,
dio_sdn_ck_n_o => dio_sdn_ck_n_o,
dio_led_top_o => dio_led_top_o,
dio_led_bot_o => dio_led_bot_o,
dio_scl_b => dio_scl_b,
dio_sda_b => dio_sda_b,
dio_ga_o => dio_ga_o,
dio_scl_b => dio_scl_b,
dio_sda_b => dio_sda_b,
dio_ga_o => dio_ga_o,
tm_time_valid_i => tm_time_valid_i,
tm_seconds_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
slave_i => wb_in,
slave_o => wb_out,
dio_int => dio_int
-- Chipscope, debugging signals
--TRIG0 => TRIG0,
--TRIG1 => TRIG1,
--TRIG2 => TRIG2,
--TRIG3 => TRIG3,
);
slave_i => wb_in,
slave_o => wb_out,
dio_int => dio_int
-- Chipscope, debugging signals
--TRIG0 => TRIG0,
--TRIG1 => TRIG1,
--TRIG2 => TRIG2,
--TRIG3 => TRIG3,
);
wb_in.cyc <= wb_cyc_i;
wb_in.stb <= wb_stb_i;
wb_in.we <= wb_we_i;
......@@ -185,7 +185,7 @@ U_WRAPPER_DIO : xwr_dio
wb_dat_o <= wb_out.dat;
wb_ack_o <= wb_out.ack;
wb_stall_o <= wb_out.stall;
-----------------------------------------------------------------------------------
end rtl;
......
......@@ -6,7 +6,7 @@
-- Author : Javier Díaz
-- Company : Seven Solutions, UGR
-- Created : 2012-07-18
-- Last update: 2012-06-19
-- Last update: 2019-08-27
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -36,92 +36,92 @@ package wr_dio_pkg is
-- DIO
-----------------------------------------------------------------------------
constant c_xwr_dio_sdb : t_sdb_product := (
vendor_id => x"00000000000075CB", -- SEVEN SOLUTIONS
device_id => x"00000002",
version => x"00000002",
date => x"20120720",
name => "WR-DIO-Core ");
vendor_id => x"00000000000075CB", -- SEVEN SOLUTIONS
device_id => x"00000002",
version => x"00000002",
date => x"20120720",
name => "WR-DIO-Core ");
-----------------------------------------------------------------------------
-- DIO REGISTERS - (basic slave from wbgen2)
-----------------------------------------------------------------------------
constant c_xwr_dio_wb_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"00000000000075CB", -- SEVEN SOLUTIONS
device_id => x"00000001",
version => x"00000002",
date => x"20120709",
name => "WR-DIO-Registers ")));
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"00000000000075CB", -- SEVEN SOLUTIONS
device_id => x"00000001",
version => x"00000002",
date => x"20120709",
name => "WR-DIO-Registers ")));
------------------------------------------------------------------------------
-- SDB re-declaration of bridges function to include product info
------------------------------------------------------------------------------
-- Use the f_xwb_bridge_*_sdb to bridge a crossbar to another
function f_xwb_bridge_product_manual_sdb( -- take a manual bus size
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address;
g_sdb_product : t_sdb_product) return t_sdb_bridge;
function f_xwb_bridge_product_manual_sdb( -- take a manual bus size
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address;
g_sdb_product : t_sdb_product) return t_sdb_bridge;
function f_xwb_bridge_product_layout_sdb( -- determine bus size from layout
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address;
g_sdb_product : t_sdb_product) return t_sdb_bridge;
function f_xwb_bridge_product_layout_sdb( -- determine bus size from layout
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address;
g_sdb_product : t_sdb_product) return t_sdb_bridge;
end wr_dio_pkg;
package body wr_dio_pkg is
package body wr_dio_pkg is
function f_xwb_bridge_product_manual_sdb(
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address;
g_sdb_product: t_sdb_product) return t_sdb_bridge
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address;
g_sdb_product : t_sdb_product) return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := (others => '0');
result.sdb_child := (others => '0');
result.sdb_child(c_wishbone_address_width-1 downto 0) := g_sdb_addr;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := (others => '0');
result.sdb_component.addr_first := (others => '0');