Commit dc00dad0 authored by Javier Díaz's avatar Javier Díaz Committed by Miguel Jimenez Lopez

vic-eic interrupts tested, debugged with python scripts

parent 1da5cbfa
files = ["wrsw_dio_wb.vhd",
"wrsw_dio.vhd",
"xwrsw_dio.vhd",
"pulse_gen_pl.vhd",
"immed_pulse_counter.vhd",
"dummy_time.vhd" ]
......
......@@ -25,7 +25,11 @@
-- 2012-03-08 0.2 Javier.d Added wrsw_dio_wb
-- 2012-07-05 0.3 Javier.d Midified wrsw_dio_wb, modified interface
-------------------------------------------------------------------------------
-- Memory map:
-- 0x000: DIO-ONEWIRE
-- 0x100: DIO-I2C
-- 0x200: DIO-GPIO
-- 0x300: DIO-REGISTERS
-- WARNING: only pipelined mode is supported (Intercon is pipelined only) - T.W.
library ieee;
......@@ -83,13 +87,13 @@ architecture rtl of wrsw_dio is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate seconds time)
-------------------------------------------------------------------------------
-- component dummy_time is
-- port(
-- clk_sys : in std_logic;
-- rst_n : in std_logic;
-- tm_utc : out std_logic_vector(39 downto 0);
-- tm_cycles : out std_logic_vector(27 downto 0));
-- end component;
component dummy_time is
port(
clk_sys : in std_logic;
rst_n : in std_logic;
tm_utc : out std_logic_vector(39 downto 0);
tm_cycles : out std_logic_vector(27 downto 0));
end component;
-------------------------------------------------------------------------------
-- PULSE GENERATOR which produces a 1-tick-long pulse in its
......@@ -387,12 +391,16 @@ architecture rtl of wrsw_dio is
signal cbar_master_in : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
signal slave_bypass_i : t_wishbone_slave_in;
signal slave_bypass_o : t_wishbone_slave_out;
-- DIO related signals
signal dio_pulse : std_logic_vector(4 downto 0);
signal dio_pulse_prog : std_logic_vector(4 downto 0);
signal dio_pulse_immed : std_logic_vector(4 downto 0);
signal dio_pulse_immed_stb : std_logic_vector(4 downto 0);
signal dio_out_mode : std_logic_vector(4 downto 0);
signal wb_dio_irq : std_logic;
-------------------------------------------------------------------------------
-- rtl
......@@ -400,13 +408,13 @@ architecture rtl of wrsw_dio is
begin
-- Dummy counter for simulationg WRPC seconds time
-- U_dummy: dummy_time
-- port map(
-- clk_sys => clk_ref_i,
-- rst_n => rst_n_i,
-- tm_utc => tm_utc,
-- tm_cycles => tm_cycles
-- );
U_dummy: dummy_time
port map(
clk_sys => clk_ref_i,
rst_n => rst_n_i,
tm_utc => tm_seconds,
tm_cycles => tm_cycles
);
------------------------------------------------------------------------------
-- GEN AND STAMPER
......@@ -420,12 +428,12 @@ begin
pulse_o => dio_pulse_prog(i),
-- DEBUG
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_utc,--tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
tm_time_valid_i => '1',--tm_time_valid_i,
tm_utc_i => tm_seconds,--tm_utc_i,
tm_cycles_i => tm_cycles, --tm_cycles_i,
-- tm_time_valid_i => tm_time_valid_i,
-- tm_utc_i => tm_seconds_i,
-- tm_cycles_i => tm_cycles_i,
trig_ready_o => trig_ready(i),
......@@ -444,12 +452,13 @@ begin
pulse_a_i => dio_in_i(i),
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_utc, --tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
-- DEBUG
tm_time_valid_i => '1',--tm_time_valid_i,
tm_utc_i => tm_seconds, --tm_utc_i,
tm_cycles_i => tm_cycles, --tm_cycles_i,
-- tm_time_valid_i => tm_time_valid_i,
-- tm_utc_i => tm_seconds_i,
-- tm_cycles_i => tm_cycles_i,
tag_utc_o => tag_seconds(i),
tag_cycles_o => tag_cycles(i),
......@@ -543,13 +552,28 @@ begin
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
-- Master connections
slave_i(0) => slave_i,
slave_o(0) => slave_o,
slave_i(0) => slave_bypass_i,
slave_o(0) => slave_bypass_o,
-- Slave conenctions
master_i => cbar_master_in,
master_o => cbar_master_out
);
-- Irq form one slave is bypassed to the Master connection
slave_bypass_i.cyc <= slave_i.cyc;
slave_bypass_i.stb <= slave_i.stb;
slave_bypass_i.adr <= slave_i.adr;
slave_bypass_i.sel <= slave_i.sel;
slave_bypass_i.dat <= slave_i.dat;
slave_bypass_i.we <= slave_i.we;
slave_o.ack <= slave_bypass_o.ack;
--slave_o.err <= slave_bypass_o.err;
--slave_o.rty <= slave_bypass_o.rty;
slave_o.stall <= slave_bypass_o.stall;
slave_o.int <= wb_dio_irq;
slave_o.dat <= slave_bypass_o.dat;
immediate_output_with_pulse_length: for i in 0 to 4 generate
immediate_output_component: immed_pulse_counter
generic map (
......@@ -595,7 +619,8 @@ begin
wb_we_i => cbar_master_out(3).we,
wb_ack_o => cbar_master_in(3).ack,
wb_stall_o => cbar_master_in(3).stall,
wb_int_o => cbar_master_in(3).int,--wb_irq_data_fifo_o, --slave_o.int,
-- Crossbar could not propagate interrupt lines of several slaves => signal bypass
wb_int_o => wb_dio_irq,
clk_asyn_i => clk_ref_i,
dio_tsf0_wr_req_i => dio_tsf_wr_req(0),
......
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