Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC DIO 5ch TTL a
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
6
Issues
6
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC DIO 5ch TTL a
Commits
dc00dad0
Commit
dc00dad0
authored
Jul 12, 2012
by
Javier Díaz
Committed by
Miguel Jimenez Lopez
Apr 03, 2019
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
vic-eic interrupts tested, debugged with python scripts
parent
1da5cbfa
Expand all
Show whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
888 additions
and
109 deletions
+888
-109
Manifest.py
modules/wrsw_dio/Manifest.py
+4
-4
wrsw_dio.vhd
modules/wrsw_dio/wrsw_dio.vhd
+130
-105
xwrsw_dio.vhd
modules/wrsw_dio/xwrsw_dio.vhd
+754
-0
No files found.
modules/wrsw_dio/Manifest.py
View file @
dc00dad0
files
=
[
"wrsw_dio_wb.vhd"
,
"
wrsw_dio.vhd"
,
"x
wrsw_dio.vhd"
,
"pulse_gen_pl.vhd"
,
"immed_pulse_counter.vhd"
,
"dummy_time.vhd"
]
...
...
modules/wrsw_dio/wrsw_dio.vhd
View file @
dc00dad0
...
...
@@ -25,7 +25,11 @@
-- 2012-03-08 0.2 Javier.d Added wrsw_dio_wb
-- 2012-07-05 0.3 Javier.d Midified wrsw_dio_wb, modified interface
-------------------------------------------------------------------------------
-- Memory map:
-- 0x000: DIO-ONEWIRE
-- 0x100: DIO-I2C
-- 0x200: DIO-GPIO
-- 0x300: DIO-REGISTERS
-- WARNING: only pipelined mode is supported (Intercon is pipelined only) - T.W.
library
ieee
;
...
...
@@ -83,13 +87,13 @@ architecture rtl of wrsw_dio is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate seconds time)
-------------------------------------------------------------------------------
--
component dummy_time is
--
port(
--
clk_sys : in std_logic;
--
rst_n : in std_logic;
--
tm_utc : out std_logic_vector(39 downto 0);
--
tm_cycles : out std_logic_vector(27 downto 0));
--
end component;
component
dummy_time
is
port
(
clk_sys
:
in
std_logic
;
rst_n
:
in
std_logic
;
tm_utc
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles
:
out
std_logic_vector
(
27
downto
0
));
end
component
;
-------------------------------------------------------------------------------
-- PULSE GENERATOR which produces a 1-tick-long pulse in its
...
...
@@ -387,12 +391,16 @@ architecture rtl of wrsw_dio is
signal
cbar_master_in
:
t_wishbone_master_in_array
(
c_WB_SLAVES_DIO
-1
downto
0
);
signal
cbar_master_out
:
t_wishbone_master_out_array
(
c_WB_SLAVES_DIO
-1
downto
0
);
signal
slave_bypass_i
:
t_wishbone_slave_in
;
signal
slave_bypass_o
:
t_wishbone_slave_out
;
-- DIO related signals
signal
dio_pulse
:
std_logic_vector
(
4
downto
0
);
signal
dio_pulse_prog
:
std_logic_vector
(
4
downto
0
);
signal
dio_pulse_immed
:
std_logic_vector
(
4
downto
0
);
signal
dio_pulse_immed_stb
:
std_logic_vector
(
4
downto
0
);
signal
dio_out_mode
:
std_logic_vector
(
4
downto
0
);
signal
wb_dio_irq
:
std_logic
;
-------------------------------------------------------------------------------
-- rtl
...
...
@@ -400,13 +408,13 @@ architecture rtl of wrsw_dio is
begin
-- Dummy counter for simulationg WRPC seconds time
--
U_dummy: dummy_time
--
port map(
--
clk_sys => clk_ref_i,
--
rst_n => rst_n_i,
-- tm_utc => tm_utc
,
--
tm_cycles => tm_cycles
--
);
U_dummy
:
dummy_time
port
map
(
clk_sys
=>
clk_ref_i
,
rst_n
=>
rst_n_i
,
tm_utc
=>
tm_seconds
,
tm_cycles
=>
tm_cycles
);
------------------------------------------------------------------------------
-- GEN AND STAMPER
...
...
@@ -420,12 +428,12 @@ begin
pulse_o
=>
dio_pulse_prog
(
i
),
-- DEBUG
--
tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_utc
,--tm_utc_i,
--
tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i
=>
tm_time_valid_i
,
tm_utc_i
=>
tm_seconds_i
,
tm_cycles_i
=>
tm_cycles_i
,
tm_time_valid_i
=>
'1'
,
--tm_time_valid_i,
tm_utc_i
=>
tm_seconds
,
--tm_utc_i,
tm_cycles_i
=>
tm_cycles
,
--tm_cycles_i,
--
tm_time_valid_i => tm_time_valid_i,
--
tm_utc_i => tm_seconds_i,
--
tm_cycles_i => tm_cycles_i,
trig_ready_o
=>
trig_ready
(
i
),
...
...
@@ -444,12 +452,13 @@ begin
pulse_a_i
=>
dio_in_i
(
i
),
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_utc, --tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i
=>
tm_time_valid_i
,
tm_utc_i
=>
tm_seconds_i
,
tm_cycles_i
=>
tm_cycles_i
,
-- DEBUG
tm_time_valid_i
=>
'1'
,
--tm_time_valid_i,
tm_utc_i
=>
tm_seconds
,
--tm_utc_i,
tm_cycles_i
=>
tm_cycles
,
--tm_cycles_i,
-- tm_time_valid_i => tm_time_valid_i,
-- tm_utc_i => tm_seconds_i,
-- tm_cycles_i => tm_cycles_i,
tag_utc_o
=>
tag_seconds
(
i
),
tag_cycles_o
=>
tag_cycles
(
i
),
...
...
@@ -543,13 +552,28 @@ begin
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
-- Master connections
slave_i
(
0
)
=>
slave_i
,
slave_o
(
0
)
=>
slave_o
,
slave_i
(
0
)
=>
slave_
bypass_
i
,
slave_o
(
0
)
=>
slave_
bypass_
o
,
-- Slave conenctions
master_i
=>
cbar_master_in
,
master_o
=>
cbar_master_out
);
-- Irq form one slave is bypassed to the Master connection
slave_bypass_i
.
cyc
<=
slave_i
.
cyc
;
slave_bypass_i
.
stb
<=
slave_i
.
stb
;
slave_bypass_i
.
adr
<=
slave_i
.
adr
;
slave_bypass_i
.
sel
<=
slave_i
.
sel
;
slave_bypass_i
.
dat
<=
slave_i
.
dat
;
slave_bypass_i
.
we
<=
slave_i
.
we
;
slave_o
.
ack
<=
slave_bypass_o
.
ack
;
--slave_o.err <= slave_bypass_o.err;
--slave_o.rty <= slave_bypass_o.rty;
slave_o
.
stall
<=
slave_bypass_o
.
stall
;
slave_o
.
int
<=
wb_dio_irq
;
slave_o
.
dat
<=
slave_bypass_o
.
dat
;
immediate_output_with_pulse_length
:
for
i
in
0
to
4
generate
immediate_output_component
:
immed_pulse_counter
generic
map
(
...
...
@@ -595,7 +619,8 @@ begin
wb_we_i
=>
cbar_master_out
(
3
)
.
we
,
wb_ack_o
=>
cbar_master_in
(
3
)
.
ack
,
wb_stall_o
=>
cbar_master_in
(
3
)
.
stall
,
wb_int_o
=>
cbar_master_in
(
3
)
.
int
,
--wb_irq_data_fifo_o, --slave_o.int,
-- Crossbar could not propagate interrupt lines of several slaves => signal bypass
wb_int_o
=>
wb_dio_irq
,
clk_asyn_i
=>
clk_ref_i
,
dio_tsf0_wr_req_i
=>
dio_tsf_wr_req
(
0
),
...
...
modules/wrsw_dio/xwrsw_dio.vhd
0 → 100644
View file @
dc00dad0
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment