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FMC DIO 5ch TTL a
Commits
a3efe86e
Commit
a3efe86e
authored
May 14, 2020
by
Jorge Machado
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Create structures to handle different DIO versions
parent
d1c126b0
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6 changed files
with
1059 additions
and
651 deletions
+1059
-651
wr-dio-regs.c
sw/kernel/hw/wr-dio-regs.c
+18
-0
wr-dio-regs.h
sw/kernel/hw/wr-dio-regs.h
+32
-651
wr-dio-regs_v1.c
sw/kernel/hw/wr-dio-regs_v1.c
+80
-0
wr-dio-regs_v1.h
sw/kernel/hw/wr-dio-regs_v1.h
+673
-0
wr-dio-regs_v2.c
sw/kernel/hw/wr-dio-regs_v2.c
+80
-0
wr-dio-regs_v2.h
sw/kernel/hw/wr-dio-regs_v2.h
+176
-0
No files found.
sw/kernel/hw/wr-dio-regs.c
0 → 100644
View file @
a3efe86e
#include "wr-dio-regs.h"
struct
regmap
*
get_regmap
(
unsigned
int
ver
)
{
if
(
ver
==
0
)
return
regmap_v1
;
else
return
regmap_v2
;
}
struct
regmap_common
get_regmap_common
(
unsigned
int
ver
)
{
if
(
ver
==
0
)
return
regmap_common_v1
;
else
return
regmap_common_v2
;
}
\ No newline at end of file
sw/kernel/hw/wr-dio-regs.h
View file @
a3efe86e
This diff is collapsed.
Click to expand it.
sw/kernel/hw/wr-dio-regs_v1.c
0 → 100644
View file @
a3efe86e
#include "wr-dio-regs_v1.h"
#include "wr-dio-regs.h"
#define R(x) (offsetof(struct DIO_WB, x))
struct
regmap
regmap_v1
[]
=
{
{
.
trig_l
=
R
(
TRIG0
),
.
trig_h
=
R
(
TRIGH0
),
.
cycle
=
R
(
CYC0
),
.
pulse
=
R
(
PROG0_PULSE
),
.
pulse_per
=
0
,
.
fifo_tai_l
=
R
(
TSF0_R0
),
.
fifo_tai_h
=
R
(
TSF0_R1
),
.
fifo_cycle
=
R
(
TSF0_R2
),
.
fifo_status
=
R
(
TSF0_CSR
),
},
{
.
trig_l
=
R
(
TRIG1
),
.
trig_h
=
R
(
TRIGH1
),
.
cycle
=
R
(
CYC1
),
.
pulse
=
R
(
PROG1_PULSE
),
.
pulse_per
=
0
,
.
fifo_tai_l
=
R
(
TSF1_R0
),
.
fifo_tai_h
=
R
(
TSF1_R1
),
.
fifo_cycle
=
R
(
TSF1_R2
),
.
fifo_status
=
R
(
TSF1_CSR
),
},
{
.
trig_l
=
R
(
TRIG2
),
.
trig_h
=
R
(
TRIGH2
),
.
cycle
=
R
(
CYC2
),
.
pulse
=
R
(
PROG2_PULSE
),
.
pulse_per
=
0
,
.
fifo_tai_l
=
R
(
TSF2_R0
),
.
fifo_tai_h
=
R
(
TSF2_R1
),
.
fifo_cycle
=
R
(
TSF2_R2
),
.
fifo_status
=
R
(
TSF2_CSR
),
},
{
.
trig_l
=
R
(
TRIG3
),
.
trig_h
=
R
(
TRIGH3
),
.
cycle
=
R
(
CYC3
),
.
pulse
=
R
(
PROG3_PULSE
),
.
pulse_per
=
0
,
.
fifo_tai_l
=
R
(
TSF3_R0
),
.
fifo_tai_h
=
R
(
TSF3_R1
),
.
fifo_cycle
=
R
(
TSF3_R2
),
.
fifo_status
=
R
(
TSF3_CSR
),
},
{
.
trig_l
=
R
(
TRIG4
),
.
trig_h
=
R
(
TRIGH4
),
.
cycle
=
R
(
CYC4
),
.
pulse
=
R
(
PROG4_PULSE
),
.
pulse_per
=
0
,
.
fifo_tai_l
=
R
(
TSF4_R0
),
.
fifo_tai_h
=
R
(
TSF4_R1
),
.
fifo_cycle
=
R
(
TSF4_R2
),
.
fifo_status
=
R
(
TSF4_CSR
),
},
{
.
trig_l
=
0
,
.
trig_h
=
0
,
.
cycle
=
0
,
.
pulse
=
0
,
.
pulse_per
=
0
,
.
fifo_tai_l
=
0
,
.
fifo_tai_h
=
0
,
.
fifo_cycle
=
0
,
.
fifo_status
=
0
,
}
};
struct
regmap_common
regmap_common_v1
=
{
.
ver_
=
0
,
.
iomode_reg
=
R
(
IOMODE
),
.
latch_reg
=
R
(
R_LATCH
),
.
trig_reg
=
R
(
TRIG
),
.
pulse_reg
=
R
(
PULSE
),
.
eic_idr_reg
=
R
(
EIC_IDR
),
.
eic_ier_reg
=
R
(
EIC_IER
),
.
eic_imr_reg
=
R
(
EIC_IMR
),
.
eic_isr_reg
=
R
(
EIC_ISR
),
};
sw/kernel/hw/wr-dio-regs_v1.h
0 → 100644
View file @
a3efe86e
This diff is collapsed.
Click to expand it.
sw/kernel/hw/wr-dio-regs_v2.c
0 → 100644
View file @
a3efe86e
#include "wr-dio-regs_v2.h"
#include "wr-dio-regs.h"
#define R(x) (offsetof(struct DIO_WB, x))
struct
regmap
regmap_v2
[]
=
{
{
.
trig_l
=
R
(
TRIG0
),
.
trig_h
=
R
(
TRIGH0
),
.
cycle
=
R
(
CYC0
),
.
pulse
=
R
(
PROG0_PULSE
),
.
pulse_per
=
R
(
PROG0_PULSE_PER
),
.
fifo_tai_l
=
R
(
TSF0_R0
),
.
fifo_tai_h
=
R
(
TSF0_R1
),
.
fifo_cycle
=
R
(
TSF0_R2
),
.
fifo_status
=
R
(
TSF0_CSR
),
},
{
.
trig_l
=
R
(
TRIG1
),
.
trig_h
=
R
(
TRIGH1
),
.
cycle
=
R
(
CYC1
),
.
pulse
=
R
(
PROG1_PULSE
),
.
pulse_per
=
R
(
PROG1_PULSE_PER
),
.
fifo_tai_l
=
R
(
TSF1_R0
),
.
fifo_tai_h
=
R
(
TSF1_R1
),
.
fifo_cycle
=
R
(
TSF1_R2
),
.
fifo_status
=
R
(
TSF1_CSR
),
},
{
.
trig_l
=
R
(
TRIG2
),
.
trig_h
=
R
(
TRIGH2
),
.
cycle
=
R
(
CYC2
),
.
pulse
=
R
(
PROG2_PULSE
),
.
pulse_per
=
R
(
PROG2_PULSE_PER
),
.
fifo_tai_l
=
R
(
TSF2_R0
),
.
fifo_tai_h
=
R
(
TSF2_R1
),
.
fifo_cycle
=
R
(
TSF2_R2
),
.
fifo_status
=
R
(
TSF2_CSR
),
},
{
.
trig_l
=
R
(
TRIG3
),
.
trig_h
=
R
(
TRIGH3
),
.
cycle
=
R
(
CYC3
),
.
pulse
=
R
(
PROG3_PULSE
),
.
pulse_per
=
R
(
PROG3_PULSE_PER
),
.
fifo_tai_l
=
R
(
TSF3_R0
),
.
fifo_tai_h
=
R
(
TSF3_R1
),
.
fifo_cycle
=
R
(
TSF3_R2
),
.
fifo_status
=
R
(
TSF3_CSR
),
},
{
.
trig_l
=
R
(
TRIG4
),
.
trig_h
=
R
(
TRIGH4
),
.
cycle
=
R
(
CYC4
),
.
pulse
=
R
(
PROG4_PULSE
),
.
pulse_per
=
R
(
PROG4_PULSE_PER
),
.
fifo_tai_l
=
R
(
TSF4_R0
),
.
fifo_tai_h
=
R
(
TSF4_R1
),
.
fifo_cycle
=
R
(
TSF4_R2
),
.
fifo_status
=
R
(
TSF4_CSR
),
},
{
.
trig_l
=
R
(
TRIG5
),
.
trig_h
=
R
(
TRIGH5
),
.
cycle
=
R
(
CYC5
),
.
pulse
=
R
(
PROG5_PULSE
),
.
pulse_per
=
R
(
PROG5_PULSE_PER
),
.
fifo_tai_l
=
R
(
TSF5_R0
),
.
fifo_tai_h
=
R
(
TSF5_R1
),
.
fifo_cycle
=
R
(
TSF5_R2
),
.
fifo_status
=
R
(
TSF5_CSR
),
}
};
struct
regmap_common
regmap_common_v2
=
{
.
ver_
=
R
(
VER
),
.
iomode_reg
=
R
(
IOMODE
),
.
latch_reg
=
R
(
R_LATCH
),
.
trig_reg
=
R
(
TRIG
),
.
pulse_reg
=
R
(
PULSE
),
.
eic_idr_reg
=
R
(
EIC_IDR
),
.
eic_ier_reg
=
R
(
EIC_IER
),
.
eic_imr_reg
=
R
(
EIC_IMR
),
.
eic_isr_reg
=
R
(
EIC_ISR
),
};
sw/kernel/hw/wr-dio-regs_v2.h
0 → 100644
View file @
a3efe86e
/*
Register definitions for slave core: FMC-DIO-5chttla
* File : wr-dio-regs.h
* Author : auto-generated by wbgen2 from wr_dio.wb
* Created : Tue Apr 28 15:59:03 2020
* Version : 0x00000002
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_dio.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WR_DIO_V2
#define __WBGEN2_REGDEFS_WR_DIO_V2
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
/* version definition */
#define WBGEN2_DIO_VERSION 0x00000002
PACKED
struct
DIO_WB
{
/* [0x0]: REG Version register */
uint32_t
VER
;
/* [0x4]: REG fmc-dio 0 seconds-based trigger for pulse generation */
uint32_t
TRIG0
;
/* [0x8]: REG fmc-dio 0 seconds-based trigger for pulse generation */
uint32_t
TRIGH0
;
/* [0xc]: REG fmc-dio 0 cycles to trigger a pulse generation */
uint32_t
CYC0
;
/* [0x10]: REG fmc-dio 1 seconds-based trigger for pulse generation */
uint32_t
TRIG1
;
/* [0x14]: REG fmc-dio 1 seconds-based trigger for pulse generation */
uint32_t
TRIGH1
;
/* [0x18]: REG fmc-dio 1 cycles to trigger a pulse generation */
uint32_t
CYC1
;
/* [0x1c]: REG fmc-dio 2 seconds-based trigger for pulse generation */
uint32_t
TRIG2
;
/* [0x20]: REG fmc-dio 2 seconds-based trigger for pulse generation */
uint32_t
TRIGH2
;
/* [0x24]: REG fmc-dio 2 cycles to trigger a pulse generation */
uint32_t
CYC2
;
/* [0x28]: REG fmc-dio 3 seconds-based trigger for pulse generation */
uint32_t
TRIG3
;
/* [0x2c]: REG fmc-dio 3 seconds-based trigger for pulse generation */
uint32_t
TRIGH3
;
/* [0x30]: REG fmc-dio 3 cycles to trigger a pulse generation */
uint32_t
CYC3
;
/* [0x34]: REG fmc-dio 4 seconds-based trigger for pulse generation */
uint32_t
TRIG4
;
/* [0x38]: REG fmc-dio 4 seconds-based trigger for pulse generation */
uint32_t
TRIGH4
;
/* [0x3c]: REG fmc-dio 4 cycles to trigger a pulse generation */
uint32_t
CYC4
;
/* [0x40]: REG fmc-dio 5 seconds-based trigger for pulse generation */
uint32_t
TRIG5
;
/* [0x44]: REG fmc-dio 5 seconds-based trigger for pulse generation */
uint32_t
TRIGH5
;
/* [0x48]: REG fmc-dio 5 cycles to trigger a pulse generation */
uint32_t
CYC5
;
/* [0x4c]: REG FMC-DIO input/output configuration register. */
uint32_t
IOMODE
;
/* [0x50]: REG Time-programmable output strobe signal */
uint32_t
R_LATCH
;
/* [0x54]: REG FMC-DIO time trigger is ready to accept a new trigger generation request */
uint32_t
TRIG
;
/* [0x58]: REG fmc-dio channel 0 Programmable/immediate output pulse length */
uint32_t
PROG0_PULSE
;
/* [0x5c]: REG fmc-dio channel 0 Programmable/immediate output pulse period */
uint32_t
PROG0_PULSE_PER
;
/* [0x60]: REG fmc-dio channel 1 Programmable/immediate output pulse length */
uint32_t
PROG1_PULSE
;
/* [0x64]: REG fmc-dio channel 1 Programmable/immediate output pulse period */
uint32_t
PROG1_PULSE_PER
;
/* [0x68]: REG fmc-dio channel 2 Programmable/immediate output pulse length */
uint32_t
PROG2_PULSE
;
/* [0x6c]: REG fmc-dio channel 2 Programmable/immediate output pulse period */
uint32_t
PROG2_PULSE_PER
;
/* [0x70]: REG fmc-dio channel 3 Programmable/immediate output pulse length */
uint32_t
PROG3_PULSE
;
/* [0x74]: REG fmc-dio channel 3 Programmable/immediate output pulse period */
uint32_t
PROG3_PULSE_PER
;
/* [0x78]: REG fmc-dio channel 4 Programmable/immediate output pulse length */
uint32_t
PROG4_PULSE
;
/* [0x7c]: REG fmc-dio channel 4 Programmable/immediate output pulse period */
uint32_t
PROG4_PULSE_PER
;
/* [0x80]: REG fmc-dio channel 5 Programmable/immediate output pulse length */
uint32_t
PROG5_PULSE
;
/* [0x84]: REG fmc-dio channel 5 Programmable/immediate output pulse period */
uint32_t
PROG5_PULSE_PER
;
/* [0x88]: REG Pulse generate immediately */
uint32_t
PULSE
;
/* padding to: 40 words */
uint32_t
__padding_0
[
5
];
/* [0xa0]: REG Interrupt disable register */
uint32_t
EIC_IDR
;
/* [0xa4]: REG Interrupt enable register */
uint32_t
EIC_IER
;
/* [0xa8]: REG Interrupt mask register */
uint32_t
EIC_IMR
;
/* [0xac]: REG Interrupt status register */
uint32_t
EIC_ISR
;
/* [0xb0]: REG FIFO 'Timestamp FIFO 0' data output register 0 */
uint32_t
TSF0_R0
;
/* [0xb4]: REG FIFO 'Timestamp FIFO 0' data output register 1 */
uint32_t
TSF0_R1
;
/* [0xb8]: REG FIFO 'Timestamp FIFO 0' data output register 2 */
uint32_t
TSF0_R2
;
/* [0xbc]: REG FIFO 'Timestamp FIFO 0' data output register 3 */
uint32_t
TSF0_R3
;
/* [0xc0]: REG FIFO 'Timestamp FIFO 0' control/status register */
uint32_t
TSF0_CSR
;
/* [0xc4]: REG FIFO 'Timestamp FIFO 1' data output register 0 */
uint32_t
TSF1_R0
;
/* [0xc8]: REG FIFO 'Timestamp FIFO 1' data output register 1 */
uint32_t
TSF1_R1
;
/* [0xcc]: REG FIFO 'Timestamp FIFO 1' data output register 2 */
uint32_t
TSF1_R2
;
/* [0xd0]: REG FIFO 'Timestamp FIFO 1' data output register 3 */
uint32_t
TSF1_R3
;
/* [0xd4]: REG FIFO 'Timestamp FIFO 1' control/status register */
uint32_t
TSF1_CSR
;
/* [0xd8]: REG FIFO 'Timestamp FIFO 2' data output register 0 */
uint32_t
TSF2_R0
;
/* [0xdc]: REG FIFO 'Timestamp FIFO 2' data output register 1 */
uint32_t
TSF2_R1
;
/* [0xe0]: REG FIFO 'Timestamp FIFO 2' data output register 2 */
uint32_t
TSF2_R2
;
/* [0xe4]: REG FIFO 'Timestamp FIFO 2' data output register 3 */
uint32_t
TSF2_R3
;
/* [0xe8]: REG FIFO 'Timestamp FIFO 2' control/status register */
uint32_t
TSF2_CSR
;
/* [0xec]: REG FIFO 'Timestamp FIFO 3' data output register 0 */
uint32_t
TSF3_R0
;
/* [0xf0]: REG FIFO 'Timestamp FIFO 3' data output register 1 */
uint32_t
TSF3_R1
;
/* [0xf4]: REG FIFO 'Timestamp FIFO 3' data output register 2 */
uint32_t
TSF3_R2
;
/* [0xf8]: REG FIFO 'Timestamp FIFO 3' data output register 3 */
uint32_t
TSF3_R3
;
/* [0xfc]: REG FIFO 'Timestamp FIFO 3' control/status register */
uint32_t
TSF3_CSR
;
/* [0x100]: REG FIFO 'Timestamp FIFO 4' data output register 0 */
uint32_t
TSF4_R0
;
/* [0x104]: REG FIFO 'Timestamp FIFO 4' data output register 1 */
uint32_t
TSF4_R1
;
/* [0x108]: REG FIFO 'Timestamp FIFO 4' data output register 2 */
uint32_t
TSF4_R2
;
/* [0x10c]: REG FIFO 'Timestamp FIFO 4' data output register 3 */
uint32_t
TSF4_R3
;
/* [0x110]: REG FIFO 'Timestamp FIFO 4' control/status register */
uint32_t
TSF4_CSR
;
/* [0x114]: REG FIFO 'Timestamp FIFO 5' data output register 0 */
uint32_t
TSF5_R0
;
/* [0x118]: REG FIFO 'Timestamp FIFO 5' data output register 1 */
uint32_t
TSF5_R1
;
/* [0x11c]: REG FIFO 'Timestamp FIFO 5' data output register 2 */
uint32_t
TSF5_R2
;
/* [0x120]: REG FIFO 'Timestamp FIFO 5' data output register 3 */
uint32_t
TSF5_R3
;
/* [0x124]: REG FIFO 'Timestamp FIFO 5' control/status register */
uint32_t
TSF5_CSR
;
};
#endif
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