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FMC DIO 5ch TTL a
Commits
76f580f8
Commit
76f580f8
authored
Apr 03, 2019
by
Miguel Jimenez Lopez
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hdl: Move and rename DIO modules and testbench.
parent
854b0a92
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16 changed files
with
148 additions
and
17454 deletions
+148
-17454
Manifest.py
hdl/modules/wr_dio/Manifest.py
+8
-0
build_wb.sh
hdl/modules/wr_dio/build_wb.sh
+3
-0
dummy_time.vhd
hdl/modules/wr_dio/dummy_time.vhd
+88
-88
immed_pulse_counter.vhd
hdl/modules/wr_dio/immed_pulse_counter.vhd
+0
-0
pulse_gen_pl.vhd
hdl/modules/wr_dio/pulse_gen_pl.vhd
+0
-0
wr_dio.vhd
hdl/modules/wr_dio/wr_dio.vhd
+13
-11
wr_dio.wb
hdl/modules/wr_dio/wr_dio.wb
+1
-1
wr_dio_pkg.vhd
hdl/modules/wr_dio/wr_dio_pkg.vhd
+8
-122
wr_dio_wb.vhd
hdl/modules/wr_dio/wr_dio_wb.vhd
+6
-6
xwr_dio.vhd
hdl/modules/wr_dio/xwr_dio.vhd
+20
-19
Manifest.py
hdl/testbench/wr_dio/Manifest.py
+0
-0
main.sv
hdl/testbench/wr_dio/main.sv
+1
-1
run.do
hdl/testbench/wr_dio/run.do
+0
-0
wave.do
hdl/testbench/wr_dio/wave.do
+0
-0
build_wb.sh
modules/wrsw_dio/build_wb.sh
+0
-7
wrsw_dio_wb.htm
modules/wrsw_dio/wrsw_dio_wb.htm
+0
-17199
No files found.
modules/wrsw
_dio/Manifest.py
→
hdl/modules/wr
_dio/Manifest.py
View file @
76f580f8
files
=
[
"wr
sw
_dio_wb.vhd"
,
"xwr
sw
_dio.vhd"
,
"wr
sw
_dio.vhd"
,
"wr
nic_sdb
_pkg.vhd"
,
files
=
[
"wr_dio_wb.vhd"
,
"xwr_dio.vhd"
,
"wr_dio.vhd"
,
"wr
_dio
_pkg.vhd"
,
"pulse_gen_pl.vhd"
,
"immed_pulse_counter.vhd"
,
"dummy_time.vhd"
]
...
...
hdl/modules/wr_dio/build_wb.sh
0 → 100755
View file @
76f580f8
#!/bin/bash
wbgen2
-D
wr_dio_wb.htm
-V
wr_dio_wb.vhd
--cstyle
defines
--lang
vhdl
-K
../../sim/dio_timing_regs.vh wr_dio.wb
modules/wrsw
_dio/dummy_time.vhd
→
hdl/modules/wr
_dio/dummy_time.vhd
View file @
76f580f8
modules/wrsw
_dio/immed_pulse_counter.vhd
→
hdl/modules/wr
_dio/immed_pulse_counter.vhd
View file @
76f580f8
File moved
modules/wrsw
_dio/pulse_gen_pl.vhd
→
hdl/modules/wr
_dio/pulse_gen_pl.vhd
View file @
76f580f8
File moved
modules/wrsw_dio/wrsw
_dio.vhd
→
hdl/modules/wr_dio/wr
_dio.vhd
View file @
76f580f8
...
...
@@ -2,7 +2,7 @@
-- Title : DIO Core
-- Project : White Rabbit Network Interface
-------------------------------------------------------------------------------
-- File : wr
sw
_dio.vhd
-- File : wr_dio.vhd
-- Author : Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-07-25
...
...
@@ -10,7 +10,7 @@
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Simulation file for the xwr
sw
_dio.vhd file
-- Description: Simulation file for the xwr_dio.vhd file
--
-------------------------------------------------------------------------------
-- TODO:
...
...
@@ -29,7 +29,7 @@ library work;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
entity
wr
sw
_dio
is
entity
wr_dio
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
...
...
@@ -54,6 +54,7 @@ entity wrsw_dio is
dio_scl_b
:
inout
std_logic
;
dio_sda_b
:
inout
std_logic
;
dio_ga_o
:
out
std_logic_vector
(
1
downto
0
);
dio_int
:
out
std_logic
;
tm_time_valid_i
:
in
std_logic
;
tm_seconds_i
:
in
std_logic_vector
(
39
downto
0
);
...
...
@@ -80,13 +81,13 @@ entity wrsw_dio is
TRIG3
:
out
std_logic_vector
(
31
downto
0
)
);
end
wr
sw_dio
;
end
wr
_dio
;
architecture
rtl
of
wr
sw
_dio
is
architecture
rtl
of
wr_dio
is
-- DIO core
component
xwr
sw
_dio
component
xwr_dio
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
...
...
@@ -122,7 +123,8 @@ architecture rtl of wrsw_dio is
TRIG3
:
out
std_logic_vector
(
31
downto
0
);
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
slave_o
:
out
t_wishbone_slave_out
;
dio_int
:
out
std_logic
);
end
component
;
--DIO core
...
...
@@ -131,7 +133,7 @@ architecture rtl of wrsw_dio is
-------------------------------------------------------------------------------
begin
U_WRAPPER_DIO
:
xwr
sw
_dio
U_WRAPPER_DIO
:
xwr_dio
generic
map
(
g_interface_mode
=>
g_interface_mode
,
g_address_granularity
=>
g_address_granularity
)
...
...
@@ -163,7 +165,9 @@ U_WRAPPER_DIO : xwrsw_dio
tm_cycles_i
=>
tm_cycles_i
,
slave_i
=>
wb_in
,
slave_o
=>
wb_out
slave_o
=>
wb_out
,
dio_int
=>
dio_int
-- Chipscope, debugging signals
--TRIG0 => TRIG0,
...
...
@@ -181,8 +185,6 @@ U_WRAPPER_DIO : xwrsw_dio
wb_dat_o
<=
wb_out
.
dat
;
wb_ack_o
<=
wb_out
.
ack
;
wb_stall_o
<=
wb_out
.
stall
;
wb_irq_o
<=
wb_out
.
int
;
-----------------------------------------------------------------------------------
end
rtl
;
...
...
modules/wrsw_dio/wrsw
_dio.wb
→
hdl/modules/wr_dio/wr
_dio.wb
View file @
76f580f8
...
...
@@ -32,7 +32,7 @@ peripheral {
prefix="dio";
hdl_entity="wr
sw
_dio_wb";
hdl_entity="wr_dio_wb";
----------------------------------------------------
-- FIFOS & INTERRUPTS FOR INPUT EVENT TIME STAMPING
...
...
modules/wrsw_dio/wrnic_sdb
_pkg.vhd
→
hdl/modules/wr_dio/wr_dio
_pkg.vhd
View file @
76f580f8
...
...
@@ -30,60 +30,12 @@ use ieee.numeric_std.all;
library
work
;
use
work
.
wishbone_pkg
.
all
;
package
wr
nic_sdb
_pkg
is
package
wr
_dio
_pkg
is
-----------------------------------------------------------------------------
--
WR CORE --> TBD: move to wrcore_pkg
--
DIO
-----------------------------------------------------------------------------
constant
c_xwr_core_sdb
:
t_sdb_product
:
=
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000011"
,
version
=>
x"00000003"
,
date
=>
x"20120305"
,
name
=>
"WR-CORE "
);
-----------------------------------------------------------------------------
-- WR NIC
-----------------------------------------------------------------------------
constant
c_xwrsw_nic_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000001ffff"
,
-- I think this is overestimated
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000012"
,
version
=>
x"00000001"
,
date
=>
x"20000101"
,
-- UNKNOWN
name
=>
"WR-NIC "
)));
-----------------------------------------------------------------------------
-- WR TXTSU --> TBD: Move to wrsw_txtsu_pkg
-----------------------------------------------------------------------------
constant
c_xwrsw_txtsu_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000014"
,
version
=>
x"00000001"
,
date
=>
x"20120316"
,
name
=>
"WR-TXTSU "
)));
-----------------------------------------------------------------------------
-- WRSW DIO
-----------------------------------------------------------------------------
constant
c_xwrsw_dio_sdb
:
t_sdb_product
:
=
(
constant
c_xwr_dio_sdb
:
t_sdb_product
:
=
(
vendor_id
=>
x"00000000000075CB"
,
-- SEVEN SOLUTIONS
device_id
=>
x"00000002"
,
version
=>
x"00000002"
,
...
...
@@ -91,9 +43,9 @@ package wrnic_sdb_pkg is
name
=>
"WR-DIO-Core "
);
-----------------------------------------------------------------------------
--
WRSW
DIO REGISTERS - (basic slave from wbgen2)
-- DIO REGISTERS - (basic slave from wbgen2)
-----------------------------------------------------------------------------
constant
c_xwr
sw
_dio_wb_sdb
:
t_sdb_device
:
=
(
constant
c_xwr_dio_wb_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
...
...
@@ -109,70 +61,6 @@ package wrnic_sdb_pkg is
date
=>
x"20120709"
,
name
=>
"WR-DIO-Registers "
)));
-------------------------------------------------------------------------------
-- WB ONEWIRE MASTER --> TBD: move wishbone_pkg
-- ISSUE: this element have two sdb definitions with different names, this one
-- and the one available at WR_CORE_PKG.
-- The definition need to be unique and be included into wishbone_pkg
-------------------------------------------------------------------------------
-- constant c_xwb_onewire_master_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"01",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"00000000000000ff",
-- product => (
-- vendor_id => x"000000000000CE42", -- CERN
-- device_id => x"779c5443",
-- version => x"00000001",
-- date => x"20120305",
-- name => "WR-1Wire-master ")));
-------------------------------------------------------------------------------
-- WB I2C MASTER --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
-- constant c_xwb_i2c_master_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"01",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"00000000000000ff",
-- product => (
-- vendor_id => x"000000000000CE42", -- CERN
-- device_id => x"123c5443",
-- version => x"00000001",
-- date => x"20000101", -- UNKNOWN
-- name => "WB-I2C-Master ")));
-------------------------------------------------------------------------------
-- WB GPIO --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
-- constant c_xwb_gpio_port_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"01",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"00000000000000ff",
-- product => (
-- vendor_id => x"000000000000CE42", -- CERN
-- device_id => x"441c5143",
-- version => x"00000001",
-- date => x"20000101", -- UNKNOWN
-- name => "WB-GPIO-Port ")));
------------------------------------------------------------------------------
-- SDB re-declaration of bridges function to include product info
------------------------------------------------------------------------------
...
...
@@ -190,9 +78,9 @@ package wrnic_sdb_pkg is
g_sdb_product
:
t_sdb_product
)
return
t_sdb_bridge
;
end
wr
nic_sdb
_pkg
;
end
wr
_dio
_pkg
;
package
body
wr
nic_sdb
_pkg
is
package
body
wr
_dio
_pkg
is
function
f_xwb_bridge_product_manual_sdb
(
g_size
:
t_wishbone_address
;
...
...
@@ -266,6 +154,4 @@ package body wrnic_sdb_pkg is
return
f_xwb_bridge_product_manual_sdb
(
std_logic_vector
(
f_bus_end
(
c_wishbone_address_width
-1
downto
0
)),
g_sdb_addr
,
g_sdb_product
);
end
f_xwb_bridge_product_layout_sdb
;
end
wrnic_sdb_pkg
;
end
wr_dio_pkg
;
modules/wrsw_dio/wrsw
_dio_wb.vhd
→
hdl/modules/wr_dio/wr
_dio_wb.vhd
View file @
76f580f8
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC-DIO-5chttla
---------------------------------------------------------------------------------------
-- File : wr
sw
_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wr
sw
_dio.wb
-- File : wr_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wr_dio.wb
-- Created : Wed May 8 14:07:08 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr
sw
_dio.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_dio.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
...
...
@@ -15,7 +15,7 @@ use ieee.std_logic_1164.all;
use
ieee
.
numeric_std
.
all
;
use
work
.
wbgen2_pkg
.
all
;
entity
wr
sw
_dio_wb
is
entity
wr_dio_wb
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
...
@@ -168,9 +168,9 @@ entity wrsw_dio_wb is
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_pulse_imm_4_o
:
out
std_logic
);
end
wr
sw
_dio_wb
;
end
wr_dio_wb
;
architecture
syn
of
wr
sw
_dio_wb
is
architecture
syn
of
wr_dio_wb
is
signal
dio_tsf0_rst_n
:
std_logic
;
signal
dio_tsf0_in_int
:
std_logic_vector
(
67
downto
0
);
...
...
modules/wrsw_dio/xwrsw
_dio.vhd
→
hdl/modules/wr_dio/xwr
_dio.vhd
View file @
76f580f8
...
...
@@ -2,7 +2,7 @@
-- Title : DIO Core
-- Project : White Rabbit Network Interface
-------------------------------------------------------------------------------
-- File : xwr
sw
_dio.vhd
-- File : xwr_dio.vhd
-- Author : Rafael Rodriguez, Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-03-03
...
...
@@ -22,8 +22,8 @@
-- Revisions :
-- Date Version Author Description
-- 2012-03-03 0.1 Rafa.r Created
-- 2012-03-08 0.1 JDiaz Added wr
sw
_dio_wb
-- 2012-07-05 0.2 JDiaz Modified wr
sw
_dio_wb, modified interface
-- 2012-03-08 0.1 JDiaz Added wr_dio_wb
-- 2012-07-05 0.2 JDiaz Modified wr_dio_wb, modified interface
-- 2012-07-20 0.2 JDiaz Include sdb support
-------------------------------------------------------------------------------
-- Memory map:
...
...
@@ -39,9 +39,9 @@ use ieee.numeric_std.all;
library
work
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wr
nic_sdb
_pkg
.
all
;
use
work
.
wr
_dio
_pkg
.
all
;
entity
xwr
sw
_dio
is
entity
xwr_dio
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
...
...
@@ -74,16 +74,18 @@ entity xwrsw_dio is
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
dio_int
:
out
std_logic
;
-- Debug signals for chipscope
TRIG0
:
out
std_logic_vector
(
31
downto
0
);
TRIG1
:
out
std_logic_vector
(
31
downto
0
);
TRIG2
:
out
std_logic_vector
(
31
downto
0
);
TRIG3
:
out
std_logic_vector
(
31
downto
0
)
);
end
xwr
sw
_dio
;
end
xwr_dio
;
architecture
rtl
of
xwr
sw
_dio
is
architecture
rtl
of
xwr_dio
is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate seconds time)
...
...
@@ -189,7 +191,7 @@ architecture rtl of xwrsw_dio is
);
end
component
;
component
wr
sw
_dio_wb
is
component
wr_dio_wb
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
...
@@ -399,7 +401,7 @@ architecture rtl of xwrsw_dio is
(
0
=>
f_sdb_embed_device
(
c_xwb_onewire_master_sdb
,
x"00000000"
),
-- ONEWIRE
1
=>
f_sdb_embed_device
(
c_xwb_i2c_master_sdb
,
x"00000100"
),
-- I2C
2
=>
f_sdb_embed_device
(
c_xwb_gpio_port_sdb
,
x"00000200"
),
-- GPIO
3
=>
f_sdb_embed_device
(
c_xwr
sw
_dio_wb_sdb
,
x"00000300"
)
-- DIO REGISTERS
3
=>
f_sdb_embed_device
(
c_xwr_dio_wb_sdb
,
x"00000300"
)
-- DIO REGISTERS
);
constant
c_diobar_sdb_address
:
t_wishbone_address
:
=
x"00000400"
;
...
...
@@ -529,12 +531,12 @@ begin
slave_i
=>
cbar_master_out
(
1
),
slave_o
=>
cbar_master_in
(
1
),
desc_o
=>
open
,
scl_pad_i
=>
scl_pad_in
,
scl_pad_o
=>
scl_pad_out
,
scl_padoen_o
=>
scl_pad_oen
,
sda_pad_i
=>
sda_pad_in
,
sda_pad_o
=>
sda_pad_out
,
sda_padoen_o
=>
sda_pad_oen
);
scl_pad_i
(
0
)
=>
scl_pad_in
,
scl_pad_o
(
0
)
=>
scl_pad_out
,
scl_padoen_o
(
0
)
=>
scl_pad_oen
,
sda_pad_i
(
0
)
=>
sda_pad_in
,
sda_pad_o
(
0
)
=>
sda_pad_out
,
sda_padoen_o
(
0
)
=>
sda_pad_oen
);
dio_scl_b
<=
scl_pad_out
when
scl_pad_oen
=
'0'
else
'Z'
;
...
...
@@ -597,7 +599,8 @@ begin
slave_o
.
ack
<=
slave_bypass_o
.
ack
;
slave_o
.
stall
<=
slave_bypass_o
.
stall
;
slave_o
.
int
<=
wb_dio_irq
;
--slave_o.int <= wb_dio_irq;
dio_int
<=
wb_dio_irq
;
slave_o
.
dat
<=
slave_bypass_o
.
dat
;
slave_o
.
err
<=
slave_bypass_o
.
err
;
slave_o
.
rty
<=
slave_bypass_o
.
rty
;
...
...
@@ -680,10 +683,9 @@ begin
------------------------------------------------------------------------------
wb_dio_slave_out
.
err
<=
'0'
;
wb_dio_slave_out
.
rty
<=
'0'
;
wb_dio_slave_out
.
int
<=
'0'
;
-- Real signal we bypass to crossbar
-- SUPPORTING PIPELINE WBGEN2 SLAVES
U_DIO_REGISTERS
:
wr
sw
_dio_wb
U_DIO_REGISTERS
:
wr_dio_wb
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_sys_i
,
...
...
@@ -862,7 +864,6 @@ begin
TRIG0
(
23
)
<=
tm_time_valid_i
;
TRIG0
(
31
downto
24
)
<=
pulse_length
(
0
)(
7
downto
0
);
TRIG1
(
27
downto
0
)
<=
tag_cycles
(
0
)(
27
downto
0
);
TRIG1
(
28
)
<=
slave_bypass_o
.
int
;
TRIG1
(
29
)
<=
slave_bypass_o
.
ack
;
TRIG1
(
30
)
<=
dio_pulse
(
0
);
TRIG1
(
31
)
<=
gpio_out
(
0
);
...
...
testbench/wrsw
_dio/Manifest.py
→
hdl/testbench/wr
_dio/Manifest.py
View file @
76f580f8
File moved
testbench/wrsw
_dio/main.sv
→
hdl/testbench/wr
_dio/main.sv
View file @
76f580f8
...
...
@@ -31,7 +31,7 @@ module main;
//assign #10 clk_sys_dly = clk_sys;
//assign #10ns time_valid =1'b1;
wr
sw
_dio
wr_dio
#(
.
g_interface_mode
(
PIPELINED
)
,
.
g_address_granularity
(
WORD
))
...
...
testbench/wrsw
_dio/run.do
→
hdl/testbench/wr
_dio/run.do
View file @
76f580f8
File moved
testbench/wrsw
_dio/wave.do
→
hdl/testbench/wr
_dio/wave.do
View file @
76f580f8
File moved
modules/wrsw_dio/build_wb.sh
deleted
100755 → 0
View file @
854b0a92
#!/bin/bash
wbgen2
-D
wrsw_dio_wb.htm
-V
wrsw_dio_wb.vhd
--cstyle
defines
--lang
vhdl
-K
../../sim/dio_timing_regs.vh wrsw_dio.wb
#mkdir -p doc
# wbgen2 -D ./doc/dio.html -V wrsw_dio_wb.vhd --cstyle defines --lang vhdl -p dio_wbgen2_pkg.vhd -H record -K ../../sim/dio_timing_regs.vh wrsw_dio.wb
modules/wrsw_dio/wrsw_dio_wb.htm
deleted
100644 → 0
View file @
854b0a92
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