HW changes from Maciej feedback

61bdb074 · Jorge Machado · 7804027d · 61bdb074 · 61bdb074
Commit 61bdb074 authored Aug 19, 2020 by Jorge Machado
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Showing with 5 additions and 2 deletions

imm_pulse_train_gen.vhd hdl/modules/wr_dio/imm_pulse_train_gen.vhd +3 -1

pulse_gen_pl.vhd hdl/modules/wr_dio/pulse_gen_pl.vhd +2 -1

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--- a/hdl/modules/wr_dio/imm_pulse_train_gen.vhd
+++ b/hdl/modules/wr_dio/imm_pulse_train_gen.vhd
@@ -103,8 +103,10 @@ begin
          state 	<= WAIT_ST;
        end if;
      when COUNTING =>
-        if (counter = 0) then
+        if counter = 0 then
          state 	<= CAPTURE_PERIOD;
+		  elsif dio_pulse_immed_stb_d2 = '1' then
+			 state <= WAIT_ST;
        else
          state   <= COUNTING;
          counter <= counter-1;

--- a/hdl/modules/wr_dio/pulse_gen_pl.vhd
+++ b/hdl/modules/wr_dio/pulse_gen_pl.vhd
@@ -229,7 +229,8 @@ begin  -- architecture rtl
        pulse_o_internal <= '1';
        counter <= unsigned(pulse_length_ref)-1;
        train_counter <= unsigned(pulse_period_ref);
-      elsif train_counter /= 0 then
+		  --load_values <= '1';
+      elsif train_counter > 1 then
        train_counter <= train_counter-1;
        pulse_o_internal <= '0';
        load_values <= '0';