hdl: Add NIC/DIO designs using the new BSP components.

- Legacy NIC/DIO This design instantiates the NIC and DIO cores externally. The WRPC fabric interface is connected to a fabric redirector core to allow the interconnection of a NIC module together with an Etherbone one. - DIO design with only NIC capabilities. - DIO design with only Etherbone capabilities.

hdl: Add NIC/DIO designs using the new BSP components.
- Legacy NIC/DIO This design instantiates the NIC and DIO cores externally. The WRPC fabric interface is connected to a fabric redirector core to allow the interconnection of a NIC module together with an Etherbone one. - DIO design with only NIC capabilities. - DIO design with only Etherbone capabilities.
5c15128a · Miguel Jimenez Lopez · 1c1e44c5 · 5c15128a · 5c15128a · 5c15128a
Commit 5c15128a authored Mar 27, 2019 by Miguel Jimenez Lopez
15 changed files
--- a/hdl/syn/dio-etherbone/Manifest.py
+++ b/hdl/syn/dio-etherbone/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+fetchto = "../../ip_cores"
+
+syn_tool = "ise"
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_top = "dio_etherbone_top"
+syn_project = "dio_etherbone_top.xise"
+
+modules = {"local" : 
+              [ "../../top/dio-etherbone"] 
+          }
--- a/hdl/syn/dio-ext-nic-etherbone/Manifest.py
+++ b/hdl/syn/dio-ext-nic-etherbone/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+fetchto = "../../ip_cores"
+
+syn_tool = "ise"
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_top = "dio_ext_nic_etherbone_top"
+syn_project = "dio_ext_nic_etherbone_top.xise"
+
+modules = {"local" : 
+              [ "../../top/dio-ext-nic-etherbone"] 
+          }
--- a/hdl/syn/dio-nic/Manifest.py
+++ b/hdl/syn/dio-nic/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+fetchto = "../../ip_cores"
+
+syn_tool = "ise"
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_top = "dio_nic_top"
+syn_project = "dio_nic_top.xise"
+
+modules = {"local" : 
+              [ "../../top/dio-nic"] 
+          }
--- a/hdl/top/dio-common/Manifest.py
+++ b/hdl/top/dio-common/Manifest.py
+files = ["dio_common_top.vhd", "dio_common_top_pkg.vhd"]
--- a/hdl/top/dio-common/dio_common_top.vhd
+++ b/hdl/top/dio-common/dio_common_top.vhd
+-------------------------------------------------------------------------------
+-- Title      : DIO common design with NIC or Etherbone core.
+-- Project    : FMC DIO 5CH TTa
+-------------------------------------------------------------------------------
+-- File       : dio_common_top.vhd
+-- Author     : Miguel Jimenez-Lopez
+-- Company    : Seven Solutions
+-- Created    : 2019-03-27
+-- Last update: 2019-03-27
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- DIO design with NIC or Etherbone capabilities.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 Seven Solutions
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2019-03-27  1.0      klyone          Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_spec_pkg.all;
+use work.gn4124_core_pkg.all;
+use work.wrcore_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_dio_pkg.all;
+use work.wr_nic_wrapper_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.dio_common_top_pkg.all;
+
+entity dio_common_top is
+  generic (
+    g_dio_mode : t_dio_cfg_mode := DIO_NIC;
+    g_dpram_initf : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
+    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
+    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
+    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
+    g_simulation : integer := 0
+  );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- Local oscillators
+    clk_20m_vcxo_i : in std_logic;                -- 20MHz VCXO clock
+
+    clk_125m_pllref_p_i : in std_logic;           -- 125 MHz PLL reference
+    clk_125m_pllref_n_i : in std_logic;
+
+    clk_125m_gtp_n_i : in std_logic;              -- 125 MHz GTP reference
+    clk_125m_gtp_p_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- GN4124 PCIe bridge signals
+    ---------------------------------------------------------------------------
+    -- From GN4124 Local bus
+    gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
+    -- PCIe to Local [Inbound Data] - RX
+    gn_p2l_clk_n  : in  std_logic;       -- Receiver Source Synchronous Clock-
+    gn_p2l_clk_p  : in  std_logic;       -- Receiver Source Synchronous Clock+
+    gn_p2l_rdy    : out std_logic;       -- Rx Buffer Full Flag
+    gn_p2l_dframe : in  std_logic;       -- Receive Frame
+    gn_p2l_valid  : in  std_logic;       -- Receive Data Valid
+    gn_p2l_data   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
+    -- Inbound Buffer Request/Status
+    gn_p_wr_req   : in  std_logic_vector(1 downto 0);  -- PCIe Write Request
+    gn_p_wr_rdy   : out std_logic_vector(1 downto 0);  -- PCIe Write Ready
+    gn_rx_error   : out std_logic;                     -- Receive Error
+    -- Local to Parallel [Outbound Data] - TX
+    gn_l2p_clkn   : out std_logic;       -- Transmitter Source Synchronous Clock-
+    gn_l2p_clkp   : out std_logic;       -- Transmitter Source Synchronous Clock+
+    gn_l2p_dframe : out std_logic;       -- Transmit Data Frame
+    gn_l2p_valid  : out std_logic;       -- Transmit Data Valid
+    gn_l2p_edb    : out std_logic;       -- Packet termination and discard
+    gn_l2p_data   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
+    -- Outbound Buffer Status
+    gn_l2p_rdy    : in std_logic;                     -- Tx Buffer Full Flag
+    gn_l_wr_rdy   : in std_logic_vector(1 downto 0);  -- Local-to-PCIe Write
+    gn_p_rd_d_rdy : in std_logic_vector(1 downto 0);  -- PCIe-to-Local Read Response Data Ready
+    gn_tx_error   : in std_logic;                     -- Transmit Error
+    gn_vc_rdy     : in std_logic_vector(1 downto 0);  -- Channel ready
+    -- General Purpose Interface
+    gn_gpio : inout std_logic_vector(1 downto 0);  -- gn_gpio[0] -> GN4124 GPIO8
+                                                   -- gn_gpio[1] -> GN4124 GPIO9
+    ---------------------------------------------------------------------------
+    -- SPI interface to DACs
+    ---------------------------------------------------------------------------
+
+    plldac_sclk_o     : out std_logic;
+    plldac_din_o      : out std_logic;
+    pll25dac_cs_n_o : out std_logic; --cs1
+    pll20dac_cs_n_o : out std_logic; --cs2
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver
+    ---------------------------------------------------------------------------
+
+    sfp_txp_o         : out   std_logic;
+    sfp_txn_o         : out   std_logic;
+    sfp_rxp_i         : in    std_logic;
+    sfp_rxn_i         : in    std_logic;
+    sfp_mod_def0_i    : in    std_logic;          -- sfp detect
+    sfp_mod_def1_b    : inout std_logic;          -- scl
+    sfp_mod_def2_b    : inout std_logic;          -- sda
+    sfp_rate_select_o : out   std_logic;
+    sfp_tx_fault_i    : in    std_logic;
+    sfp_tx_disable_o  : out   std_logic;
+    sfp_los_i         : in    std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+
+    onewire_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Miscellanous SPEC pins
+    ---------------------------------------------------------------------------
+    -- Red LED next to the SFP: blinking indicates that packets are being
+    -- transferred.
+    led_act_o   : out std_logic;
+    -- Green LED next to the SFP: indicates if the link is up.
+    led_link_o : out std_logic;
+
+    button1_i   : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Digital I/O FMC Pins
+    -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
+    -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
+    ---------------------------------------------------------------------------
+
+    -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
+    -- external reference input.
+    dio_clk_p_i : in std_logic;
+    dio_clk_n_i : in std_logic;
+
+    -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
+    -- the mezzanine front panel.
+    dio_n_i : in std_logic_vector(4 downto 0);
+    dio_p_i : in std_logic_vector(4 downto 0);
+
+    -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
+    -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
+    -- of I/O (N+1) on the front panel of the mezzanine
+    dio_n_o : out std_logic_vector(4 downto 0);
+    dio_p_o : out std_logic_vector(4 downto 0);
+
+    -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
+    -- panel is configured as an output.
+    dio_oe_n_o    : out std_logic_vector(4 downto 0);
+
+    -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
+    -- panel is 50-ohm terminated
+    dio_term_en_o : out std_logic_vector(4 downto 0);
+
+    -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
+    -- blink 1-PPS.
+    dio_led_top_o : out std_logic;
+    dio_led_bot_o : out std_logic;
+
+    -- DIO 1-wire bus
+    dio_onewire_b  : inout std_logic;
+    dio_sdn_n_o    : out   std_logic;
+    dio_sdn_ck_n_o : out   std_logic;
+
+    -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
+    -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
+    dio_scl_b : inout std_logic;
+    dio_sda_b : inout std_logic
+
+  );
+end entity dio_common_top;
+
+architecture top of dio_common_top is
+
+  -----------------------------------------------------------------------------
+  -- Components
+  -----------------------------------------------------------------------------
+
+  -- DIO module
+  component xwr_dio
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD
+      );
+    port (
+      clk_sys_i : in std_logic;
+      clk_ref_i : in std_logic;
+      rst_n_i   : in std_logic;
+
+      dio_clk_i      : in    std_logic;
+      dio_pps_i      : in    std_logic;
+      dio_in_i       : in    std_logic_vector(4 downto 0);
+      dio_out_o      : out   std_logic_vector(4 downto 0);
+      dio_oe_n_o     : out   std_logic_vector(4 downto 0);
+      dio_term_en_o  : out   std_logic_vector(4 downto 0);
+      dio_onewire_b  : inout std_logic;
+      dio_sdn_n_o    : out   std_logic;
+      dio_sdn_ck_n_o : out   std_logic;
+      dio_led_top_o  : out   std_logic;
+      dio_led_bot_o  : out   std_logic;
+
+      dio_scl_b : inout std_logic;
+      dio_sda_b : inout std_logic;
+      dio_ga_o  : out std_logic_vector(1 downto 0);
+
+      tm_time_valid_i : in std_logic;
+      tm_seconds_i        : in std_logic_vector(39 downto 0);
+      tm_cycles_i     : in std_logic_vector(27 downto 0);
+
+      TRIG0 : out std_logic_vector(31 downto 0);
+      TRIG1 : out std_logic_vector(31 downto 0);
+      TRIG2 : out std_logic_vector(31 downto 0);
+      TRIG3 : out std_logic_vector(31 downto 0);
+
+      slave_i                      : in  t_wishbone_slave_in;
+      slave_o                      : out t_wishbone_slave_out;
+      dio_int                      : out std_logic
+  );
+  end component; 
+  
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- Wishbone buse(s) from masters attached to crossbar
+  signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
+  signal cnx_master_in  : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
+
+  -- Wishbone buse(s) to slaves attached to crossbar
+  signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
+  signal cnx_slave_in  : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
+
+  -- Gennum signals
+  signal gn_wbadr : std_logic_vector(31 downto 0);
+
+  -- clock and reset
+  signal clk_sys_62m5   : std_logic;
+  signal rst_sys_62m5_n : std_logic;
+  signal rst_ref_125m_n : std_logic;
+  signal clk_ref_125m   : std_logic;
+  signal clk_ref_div2   : std_logic;
+  signal clk_ext_10m    : std_logic;
+
+  -- I2C EEPROM
+  signal eeprom_sda_in  : std_logic;
+  signal eeprom_sda_out : std_logic;
+  signal eeprom_scl_in  : std_logic;
+  signal eeprom_scl_out : std_logic;
+
+  -- SFP
+  signal sfp_sda_in  : std_logic;
+  signal sfp_sda_out : std_logic;
+  signal sfp_scl_in  : std_logic;
+  signal sfp_scl_out : std_logic;
+
+  -- OneWire
+  signal onewire_data : std_logic;
+  signal onewire_oe   : std_logic;
+
+  -- LEDs and GPIO
+  signal wrc_abscal_txts_out : std_logic;
+  signal wrc_abscal_rxts_out : std_logic;
+  signal wrc_pps_out : std_logic;
+  attribute IOB: string;
+  attribute IOB of wrc_pps_out: signal is "TRUE";
+  signal wrc_pps_csync_out : std_logic;
+  signal wrc_pps_csync_out_ext : std_logic;
+  signal wrc_pps_valid_out : std_logic;
+  signal wrc_pps_valid_out_ext : std_logic;
+  signal wrc_pps_led : std_logic;
+  signal wrc_pps_in  : std_logic;
+  signal svec_led    : std_logic_vector(15 downto 0);
+
+  -- DIO Mezzanine
+  signal dio_in  : std_logic_vector(4 downto 0);
+  signal dio_out : std_logic_vector(4 downto 0);
+
+  -- Timecode output
+  signal tm_time_valid : std_logic;
+  signal tm_seconds    : std_logic_vector(39 downto 0);
+  signal tm_cycles     : std_logic_vector(27 downto 0);
+  
+  signal dio_int       : std_logic;
+  signal vic_vec_int   : std_logic_vector(0 downto 0);
+  signal vic_irq       : std_logic;
+
+  -- WR Fabric I/F
+  signal wrc_wrf_src_out : t_wrf_source_out;
+  signal wrc_wrf_src_in  : t_wrf_source_in;
+  signal wrc_wrf_snk_out : t_wrf_sink_out;
+  signal wrc_wrf_snk_in  : t_wrf_sink_in;
+  
+  -- Tx Timestamp
+  signal wrc_timestamps_out     : t_txtsu_timestamp;
+  signal wrc_timestamps_ack_in  : std_logic := '1';
+  
+  -- VIC-only signals
+  signal vic_only_irqs : std_logic_vector(3 downto 0);
+
+begin  -- architecture top
+  
+  -----------------------------------------------------------------------------
+  -- Primary wishbone Crossbar (Only GN4124 as Master)
+  -----------------------------------------------------------------------------
+  cmp_sdb_crossbar : xwb_sdb_crossbar
+    generic map (
+      g_num_masters => c_NUM_WB_MASTERS,
+      g_num_slaves  => c_NUM_WB_SLAVES,
+      g_registered  => TRUE,
+      g_wraparound  => TRUE,
+      g_layout      => f_pick_sdb_layout_for_dio(g_dio_mode),
+      g_sdb_addr    => c_SDB_ADDRESS)
+    port map (
+      clk_sys_i => clk_sys_62m5,
+      rst_n_i   => rst_sys_62m5_n,
+      slave_i   => cnx_master_out,
+      slave_o   => cnx_master_in,
+      master_i  => cnx_slave_out,
+      master_o  => cnx_slave_in);
+  
+  -----------------------------------------------------------------------------
+  -- GN4124, PCIe bridge core
+  -----------------------------------------------------------------------------
+  cmp_gn4124_core : gn4124_core
+    port map (
+      ---------------------------------------------------------
+      -- Control and status
+      rst_n_a_i => gn_rst_n,
+      status_o  => open,
+
+      ---------------------------------------------------------
+      -- P2L Direction
+      --
+      -- Source Sync DDR related signals
+      p2l_clk_p_i  => gn_p2l_clk_p,
+      p2l_clk_n_i  => gn_p2l_clk_n,
+      p2l_data_i   => gn_p2l_data,
+      p2l_dframe_i => gn_p2l_dframe,
+      p2l_valid_i  => gn_p2l_valid,
+      -- P2L Control
+      p2l_rdy_o    => gn_p2l_rdy,
+      p_wr_req_i   => gn_p_wr_req,
+      p_wr_rdy_o   => gn_p_wr_rdy,
+      rx_error_o   => gn_rx_error,
+      vc_rdy_i     => gn_vc_rdy,
+
+      ---------------------------------------------------------
+      -- L2P Direction
+      --
+      -- Source Sync DDR related signals
+      l2p_clk_p_o  => gn_l2p_clkp,
+      l2p_clk_n_o  => gn_l2p_clkn,
+      l2p_data_o   => gn_l2p_data,
+      l2p_dframe_o => gn_l2p_dframe,
+      l2p_valid_o  => gn_l2p_valid,
+      -- L2P Control
+      l2p_edb_o    => gn_l2p_edb,
+      l2p_rdy_i    => gn_l2p_rdy,
+      l_wr_rdy_i   => gn_l_wr_rdy,
+      p_rd_d_rdy_i => gn_p_rd_d_rdy,
+      tx_error_i   => gn_tx_error,
+
+      ---------------------------------------------------------
+      -- Interrupt interface
+      dma_irq_o => open,
+      irq_p_i   => vic_irq,
+      irq_p_o   => gn_gpio(0),
+
+      ---------------------------------------------------------
+      -- DMA registers wishbone interface (slave classic)
+      dma_reg_clk_i => clk_sys_62m5,
+      dma_reg_adr_i => (others=>'0'),
+      dma_reg_dat_i => (others=>'0'),
+      dma_reg_sel_i => (others=>'0'),
+      dma_reg_stb_i => '0',
+      dma_reg_we_i  => '0',
+      dma_reg_cyc_i => '0',
+
+      ---------------------------------------------------------
+      -- CSR wishbone interface (master pipelined)
+      csr_clk_i   => clk_sys_62m5,
+      csr_adr_o   => gn_wbadr,
+      csr_dat_o   => cnx_master_out(c_WB_MASTER_PCIE).dat,
+      csr_sel_o   => cnx_master_out(c_WB_MASTER_PCIE).sel,
+      csr_stb_o   => cnx_master_out(c_WB_MASTER_PCIE).stb,
+      csr_we_o    => cnx_master_out(c_WB_MASTER_PCIE).we,
+      csr_cyc_o   => cnx_master_out(c_WB_MASTER_PCIE).cyc,
+      csr_dat_i   => cnx_master_in(c_WB_MASTER_PCIE).dat,
+      csr_ack_i   => cnx_master_in(c_WB_MASTER_PCIE).ack,
+      csr_stall_i => cnx_master_in(c_WB_MASTER_PCIE).stall,
+      csr_err_i   => cnx_master_in(c_WB_MASTER_PCIE).err,
+      csr_rty_i   => cnx_master_in(c_WB_MASTER_PCIE).rty,
+
+      ---------------------------------------------------------
+      -- L2P DMA Interface (Pipelined Wishbone master)
+      dma_clk_i   => clk_sys_62m5,
+      dma_dat_i   => (others=>'0'),
+      dma_ack_i   => '1',
+      dma_stall_i => '0',
+      dma_err_i   => '0',
+      dma_rty_i   => '0');
+
+  -- "translating" word addressing of Gennum module into byte addressing
+  cnx_master_out(c_WB_MASTER_PCIE).adr(1 downto 0)   <= (others => '0');
+  cnx_master_out(c_WB_MASTER_PCIE).adr(18 downto 2)  <= gn_wbadr(16 downto 0);
+  cnx_master_out(c_WB_MASTER_PCIE).adr(31 downto 19) <= (others => '0');
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core board package (WB Slave + WB AUX)
+  -----------------------------------------------------------------------------
+  cmp_xwrc_board_spec : xwrc_board_spec
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => TRUE,
+      g_dpram_initf               => g_dpram_initf,
+      g_fabric_iface              => f_pick_fabric_iface_for_dio(g_dio_mode))
+    port map (
+      areset_n_i          => button1_i,
+      areset_edge_n_i     => gn_rst_n,
+      clk_20m_vcxo_i      => clk_20m_vcxo_i,
+      clk_125m_pllref_p_i => clk_125m_pllref_p_i,
+      clk_125m_pllref_n_i => clk_125m_pllref_n_i,
+      clk_125m_gtp_n_i    => clk_125m_gtp_n_i,
+      clk_125m_gtp_p_i    => clk_125m_gtp_p_i,
+      clk_10m_ext_i       => clk_ext_10m,
+      clk_sys_62m5_o      => clk_sys_62m5,
+      clk_ref_125m_o      => clk_ref_125m,
+      rst_sys_62m5_n_o    => rst_sys_62m5_n,
+      rst_ref_125m_n_o    => rst_ref_125m_n,
+
+      plldac_sclk_o       => plldac_sclk_o,
+      plldac_din_o        => plldac_din_o,
+      pll25dac_cs_n_o     => pll25dac_cs_n_o,
+      pll20dac_cs_n_o     => pll20dac_cs_n_o,
+
+      sfp_txp_o           => sfp_txp_o,
+      sfp_txn_o           => sfp_txn_o,
+      sfp_rxp_i           => sfp_rxp_i,
+      sfp_rxn_i           => sfp_rxn_i,
+      sfp_det_i           => sfp_mod_def0_i,
+      sfp_sda_i           => sfp_sda_in,
+      sfp_sda_o           => sfp_sda_out,
+      sfp_scl_i           => sfp_scl_in,
+      sfp_scl_o           => sfp_scl_out,
+      sfp_rate_select_o   => sfp_rate_select_o,
+      sfp_tx_fault_i      => sfp_tx_fault_i,
+      sfp_tx_disable_o    => sfp_tx_disable_o,
+      sfp_los_i           => sfp_los_i,
+
+      eeprom_sda_i        => eeprom_sda_in,
+      eeprom_sda_o        => eeprom_sda_out,
+      eeprom_scl_i        => eeprom_scl_in,
+      eeprom_scl_o        => eeprom_scl_out,
+
+      onewire_i           => onewire_data,
+      onewire_oen_o       => onewire_oe,
+      -- Uart
+      uart_rxd_i          => uart_rxd_i,
+      uart_txd_o          => uart_txd_o,
+      -- SPI Flash
+      flash_sclk_o        => flash_sclk_o,
+      flash_ncs_o         => flash_ncs_o,
+      flash_mosi_o        => flash_mosi_o,
+      flash_miso_i        => flash_miso_i,
+
+      wb_slave_o          => cnx_slave_out(c_WB_SLAVE_WRC),
+      wb_slave_i          => cnx_slave_in(c_WB_SLAVE_WRC),
+
+      wrf_src_o           => wrc_wrf_src_out,
+      wrf_src_i           => wrc_wrf_src_in,
+      wrf_snk_o           => wrc_wrf_snk_out,
+      wrf_snk_i           => wrc_wrf_snk_in,
+      
+      abscal_txts_o       => wrc_abscal_txts_out,
+      abscal_rxts_o       => wrc_abscal_rxts_out,
+
+      timestamps_o        => wrc_timestamps_out,
+      timestamps_ack_i    => wrc_timestamps_ack_in,
+
+      pps_ext_i           => wrc_pps_in,
+      pps_p_o             => wrc_pps_out,
+      pps_csync_o         => wrc_pps_csync_out,
+      pps_valid_o         => wrc_pps_valid_out,
+      pps_led_o           => wrc_pps_led,
+      led_link_o          => led_link_o,
+      led_act_o           => led_act_o,
+
+      tm_time_valid_o      => tm_time_valid,
+      tm_tai_o             => tm_seconds,
+      tm_cycles_o          => tm_cycles);
+
+  -- Logic to extend pps_csync_o (125 MHz) in order to be detected
+  -- in clk_sys (62.5 MHz) domain.
+  U_Extend_pps_csync : gc_extend_pulse
+  generic map (
+    g_width => 3)
+  port map (
+    clk_i      => clk_ref_125m,
+    rst_n_i    => rst_ref_125m_n,
+    pulse_i    => wrc_pps_csync_out,
+    extended_o => wrc_pps_csync_out_ext);
+
+  -- Logic to extend pps_valid_o (125 MHz) in order to be detected
+  -- in clk_sys (62.5 MHz) domain.
+  U_Extend_pps_valid : gc_extend_pulse
+  generic map (
+    g_width => 3)
+  port map (
+    clk_i      => clk_ref_125m,
+    rst_n_i    => rst_ref_125m_n,
+    pulse_i    => wrc_pps_valid_out,
+    extended_o => wrc_pps_valid_out_ext);
+
+  -- Tristates for SFP EEPROM
+  sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
+  sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
+  sfp_scl_in     <= sfp_mod_def1_b;
+  sfp_sda_in     <= sfp_mod_def2_b;
+
+  -- tri-state onewire access
+  onewire_b    <= '0' when (onewire_oe = '1') else 'Z';
+  onewire_data <= onewire_b;
+
+  ------------------------------------------------------------------------------
+  -- Digital I/O FMC Mezzanine connections
+  ------------------------------------------------------------------------------
+  gen_dio_ibufs: for I in 0 to 4 generate
+    U_ibuf: IBUFDS
+      generic map (
+        DIFF_TERM => true)
+      port map (
+        O  => dio_in(i),
+        I  => dio_p_i(i),
+        IB => dio_n_i(i));
+  end generate gen_dio_ibufs;
+
+  gen_dio_obufs : for I in 1 to 4 generate
+    U_obuf : OBUFDS
+      port map (
+        I  => dio_out(i),
+        O  => dio_p_o(i),
+        OB => dio_n_o(i));
+  end generate gen_dio_obufs;
+
+  U_obuf_pps : OBUFDS
+    port map (
+      I  => wrc_pps_out,
+      O  => dio_p_o(0),
+      OB => dio_n_o(0));
+
+  -- EEPROM I2C tri-states
+  dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
+  eeprom_sda_in <= dio_sda_b;
+  dio_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
+  eeprom_scl_in <= dio_scl_b;
+
+  -- Div by 2 reference clock to LEMO connector
+  process(clk_ref_125m)
+  begin
+    if rising_edge(clk_ref_125m) then
+      clk_ref_div2 <= not clk_ref_div2;
+    end if;
+  end process;
+
+  cmp_ibugds_extref: IBUFGDS
+    generic map (
+      DIFF_TERM => true)
+    port map (
+      O  => clk_ext_10m,
+      I  => dio_clk_p_i,
+      IB => dio_clk_n_i);
+
+  wrc_pps_in    <= dio_in(3);
+
+  -------------------------------------
+  -- DIO
+  -------------------------------------
+  U_DIO_CORE : xwr_dio
+    generic map (
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE)
+
+    port map(
+      clk_sys_i => clk_sys_62m5,
+      clk_ref_i => clk_ref_125m,
+      rst_n_i   => rst_sys_62m5_n,
+      dio_clk_i => clk_ext_10m,
+      dio_pps_i	=> wrc_pps_out,
+      dio_in_i => dio_in,
+      dio_out_o => dio_out,
+      dio_oe_n_o => dio_oe_n_o,
+      dio_term_en_o  => dio_term_en_o,
+      dio_onewire_b  => dio_onewire_b,
+      dio_sdn_n_o    => dio_sdn_n_o,
+      dio_sdn_ck_n_o => dio_sdn_ck_n_o,
+      dio_led_top_o  => dio_led_top_o,
+      dio_led_bot_o  => dio_led_bot_o,
+      dio_ga_o => open,
+      tm_time_valid_i => tm_time_valid,
+      tm_seconds_i => tm_seconds,
+      tm_cycles_i => tm_cycles,
+      slave_i => cnx_slave_in(c_WB_SLAVE_DIO),
+      slave_o => cnx_slave_out(c_WB_SLAVE_DIO),
+      dio_int => dio_int
+      );
+
+  vic_vec_int(0) <= dio_int;
+  
+  NIC_GEN : if g_dio_mode = DIO_NIC generate
+  cmp_nic_wrapper : wr_nic_wrapper
+    generic map(
+      g_num_irqs  => 1,
+      g_num_ports => 1
+    )
+    port map(
+      clk_sys_i                 => clk_sys_62m5,
+      resetn_i                  => rst_sys_62m5_n,
+      ext_slave_i               => cnx_slave_in(c_WB_SLAVE_NIC_VIC),
+      ext_slave_o               => cnx_slave_out(c_WB_SLAVE_NIC_VIC),
+      nic_snk_i                 => wrc_wrf_src_out,
+      nic_snk_o                 => wrc_wrf_src_in,
+      nic_src_i                 => wrc_wrf_snk_out,
+      nic_src_o                 => wrc_wrf_snk_in,
+      pps_p_i                   => wrc_pps_csync_out_ext,
+      pps_valid_i               => wrc_pps_valid_out_ext,
+      vic_irqs_i                => vic_vec_int,
+      vic_int_o                 => vic_irq,
+      txtsu_timestamps_i(0)     => wrc_timestamps_out,
+      txtsu_timestamps_ack_o(0) => wrc_timestamps_ack_in);
+   end generate NIC_GEN;
+	
+	VIC_ONLY_GEN : if g_dio_mode = DIO_ETHERBONE generate
+	  cmp_vic : xwb_vic
+    generic map(
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE,
+      g_num_interrupts      => 4)
+    port map(
+      clk_sys_i    => clk_sys_62m5,
+      rst_n_i      => rst_sys_62m5_n,
+      slave_i      => cnx_slave_in(c_WB_SLAVE_NIC_VIC),
+      slave_o      => cnx_slave_out(c_WB_SLAVE_NIC_VIC),
+      irqs_i       => vic_only_irqs,
+      irq_master_o => vic_irq);
+      
+      -- Reserved
+      vic_only_irqs(0) <= '0';
+      vic_only_irqs(1) <= '0';
+      -- PPS
+      vic_only_irqs(2) <= wrc_pps_csync_out_ext;
+      -- DIO
+      vic_only_irqs(3) <= vic_vec_int(0);
+      
+      -- Dummy signals for Fabric and Tx Timestamp ports
+      wrc_wrf_src_in <= c_dummy_src_in;
+      wrc_wrf_snk_in <= c_dummy_snk_in;
+      wrc_timestamps_ack_in <= '1';
+	end generate VIC_ONLY_GEN;
+
+end architecture top;
--- a/hdl/top/dio-common/dio_common_top_pkg.vhd
+++ b/hdl/top/dio-common/dio_common_top_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : DIO common package
+-- Project    : FMC DIO 5CH TTa
+-------------------------------------------------------------------------------
+-- File       : dio_common_top.vhd
+-- Author     : Miguel Jimenez-Lopez
+-- Company    : Seven Solutions
+-- Created    : 2019-03-27
+-- Last update: 2019-03-27
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- DIO common package with NIC or Etherbone capabilities.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 Seven Solutions
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2019-03-27  1.0      klyone          Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_dio_pkg.all;
+
+package dio_common_top_pkg is
+
+  type t_dio_cfg_mode is (DIO_NIC, DIO_ETHERBONE);
+
+  function f_pick_fabric_iface_for_dio(mode : t_dio_cfg_mode) return t_board_fabric_iface;
+  function f_pick_sdb_layout_for_dio(mode : t_dio_cfg_mode) return t_sdb_record_array;
+
+  component dio_common_top
+  generic (
+    g_dio_mode : t_dio_cfg_mode := DIO_NIC;
+    g_dpram_initf : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
+    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
+    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
+    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
+    g_simulation : integer := 0
+  );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- Local oscillators
+    clk_20m_vcxo_i : in std_logic;                -- 20MHz VCXO clock
+
+    clk_125m_pllref_p_i : in std_logic;           -- 125 MHz PLL reference
+    clk_125m_pllref_n_i : in std_logic;
+
+    clk_125m_gtp_n_i : in std_logic;              -- 125 MHz GTP reference
+    clk_125m_gtp_p_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- GN4124 PCIe bridge signals
+    ---------------------------------------------------------------------------
+    -- From GN4124 Local bus
+    gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
+    -- PCIe to Local [Inbound Data] - RX
+    gn_p2l_clk_n  : in  std_logic;       -- Receiver Source Synchronous Clock-
+    gn_p2l_clk_p  : in  std_logic;       -- Receiver Source Synchronous Clock+
+    gn_p2l_rdy    : out std_logic;       -- Rx Buffer Full Flag
+    gn_p2l_dframe : in  std_logic;       -- Receive Frame
+    gn_p2l_valid  : in  std_logic;       -- Receive Data Valid
+    gn_p2l_data   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
+    -- Inbound Buffer Request/Status
+    gn_p_wr_req   : in  std_logic_vector(1 downto 0);  -- PCIe Write Request
+    gn_p_wr_rdy   : out std_logic_vector(1 downto 0);  -- PCIe Write Ready
+    gn_rx_error   : out std_logic;                     -- Receive Error
+    -- Local to Parallel [Outbound Data] - TX
+    gn_l2p_clkn   : out std_logic;       -- Transmitter Source Synchronous Clock-
+    gn_l2p_clkp   : out std_logic;       -- Transmitter Source Synchronous Clock+
+    gn_l2p_dframe : out std_logic;       -- Transmit Data Frame
+    gn_l2p_valid  : out std_logic;       -- Transmit Data Valid
+    gn_l2p_edb    : out std_logic;       -- Packet termination and discard
+    gn_l2p_data   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
+    -- Outbound Buffer Status
+    gn_l2p_rdy    : in std_logic;                     -- Tx Buffer Full Flag
+    gn_l_wr_rdy   : in std_logic_vector(1 downto 0);  -- Local-to-PCIe Write
+    gn_p_rd_d_rdy : in std_logic_vector(1 downto 0);  -- PCIe-to-Local Read Response Data Ready
+    gn_tx_error   : in std_logic;                     -- Transmit Error
+    gn_vc_rdy     : in std_logic_vector(1 downto 0);  -- Channel ready
+    -- General Purpose Interface
+    gn_gpio : inout std_logic_vector(1 downto 0);  -- gn_gpio[0] -> GN4124 GPIO8
+                                                   -- gn_gpio[1] -> GN4124 GPIO9
+    ---------------------------------------------------------------------------
+    -- SPI interface to DACs
+    ---------------------------------------------------------------------------
+
+    plldac_sclk_o     : out std_logic;
+    plldac_din_o      : out std_logic;
+    pll25dac_cs_n_o : out std_logic; --cs1
+    pll20dac_cs_n_o : out std_logic; --cs2
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver
+    ---------------------------------------------------------------------------
+
+    sfp_txp_o         : out   std_logic;
+    sfp_txn_o         : out   std_logic;
+    sfp_rxp_i         : in    std_logic;
+    sfp_rxn_i         : in    std_logic;
+    sfp_mod_def0_i    : in    std_logic;          -- sfp detect
+    sfp_mod_def1_b    : inout std_logic;          -- scl
+    sfp_mod_def2_b    : inout std_logic;          -- sda
+    sfp_rate_select_o : out   std_logic;
+    sfp_tx_fault_i    : in    std_logic;
+    sfp_tx_disable_o  : out   std_logic;
+    sfp_los_i         : in    std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+
+    onewire_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Miscellanous SPEC pins
+    ---------------------------------------------------------------------------
+    -- Red LED next to the SFP: blinking indicates that packets are being
+    -- transferred.
+    led_act_o   : out std_logic;
+    -- Green LED next to the SFP: indicates if the link is up.
+    led_link_o : out std_logic;
+
+    button1_i   : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Digital I/O FMC Pins
+    -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
+    -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
+    ---------------------------------------------------------------------------
+
+    -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
+    -- external reference input.
+    dio_clk_p_i : in std_logic;
+    dio_clk_n_i : in std_logic;
+
+    -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
+    -- the mezzanine front panel.
+    dio_n_i : in std_logic_vector(4 downto 0);
+    dio_p_i : in std_logic_vector(4 downto 0);
+
+    -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
+    -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
+    -- of I/O (N+1) on the front panel of the mezzanine
+    dio_n_o : out std_logic_vector(4 downto 0);
+    dio_p_o : out std_logic_vector(4 downto 0);
+
+    -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
+    -- panel is configured as an output.
+    dio_oe_n_o    : out std_logic_vector(4 downto 0);
+
+    -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
+    -- panel is 50-ohm terminated
+    dio_term_en_o : out std_logic_vector(4 downto 0);
+
+    -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
+    -- blink 1-PPS.
+    dio_led_top_o : out std_logic;
+    dio_led_bot_o : out std_logic;
+
+    -- DIO 1-wire bus
+    dio_onewire_b  : inout std_logic;
+    dio_sdn_n_o    : out   std_logic;
+    dio_sdn_ck_n_o : out   std_logic;
+
+    -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
+    -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
+    dio_scl_b : inout std_logic;
+    dio_sda_b : inout std_logic
+
+  );
+  end component;
+  
+  -- Number of masters on the wishbone crossbar
+  constant c_NUM_WB_MASTERS : integer := 1;
+
+  -- Number of slaves on the primary wishbone crossbar
+  constant c_NUM_WB_SLAVES : integer := 3;
+
+  -- Primary Wishbone master(s) offsets
+  constant c_WB_MASTER_PCIE    : integer := 0;
+
+  -- Primary Wishbone slave(s) offsets
+  constant c_WB_SLAVE_WRC : integer := 0;
+  constant c_WB_SLAVE_NIC_VIC : integer := 1;
+  constant c_WB_SLAVE_DIO : integer := 2;
+
+  -- sdb header address on primary crossbar
+  constant c_SDB_ADDRESS : t_wishbone_address := x"00070000";
+
+-- f_xwb_bridge_manual_sdb(size, sdb_addr)
+-- Note: sdb_addr is the sdb records address relative to the bridge base address
+constant c_wrc_bridge_sdb : t_sdb_bridge :=
+  f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
+constant c_nic_bridge_sdb : t_sdb_bridge :=
+  f_xwb_bridge_manual_sdb(x"0001ffff", x"00011000");
+constant c_wr_dio_bridge_sdb : t_sdb_bridge :=
+  f_xwb_bridge_product_manual_sdb(x"00000fff", x"00000400", c_xwr_dio_sdb);
+
+-- Primary wishbone crossbar layout (NIC)
+constant c_NIC_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
+  c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"),  -- WRPC
+  c_WB_SLAVE_NIC_VIC => f_sdb_embed_bridge(c_nic_bridge_sdb, x"00040000"),  -- NIC
+  c_WB_SLAVE_DIO => f_sdb_embed_bridge(c_wr_dio_bridge_sdb, x"00060000")   -- DIO
+  );
+     
+-- Primary wishbone crossbar layout (NIC)
+constant c_VIC_ONLY_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
+  c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"),  -- WRPC
+  c_WB_SLAVE_NIC_VIC => f_sdb_embed_device(c_xwb_vic_sdb , x"00040000"), -- VIC
+  c_WB_SLAVE_DIO => f_sdb_embed_bridge(c_wr_dio_bridge_sdb, x"00060000")   -- DIO
+  );
+  
+end dio_common_top_pkg;
+
+package body dio_common_top_pkg is	 
+
+  function f_pick_fabric_iface_for_dio(mode : t_dio_cfg_mode)
+  return t_board_fabric_iface is
+  begin
+    case mode is
+      when DIO_NIC => return PLAIN;
+      when DIO_ETHERBONE => return ETHERBONE;
+      when others => return PLAIN; --by default
+    end case;
+  end function;
+  
+  function f_pick_sdb_layout_for_dio(mode : t_dio_cfg_mode)
+  return t_sdb_record_array is
+  begin
+    case mode is
+      when DIO_NIC => return c_NIC_WB_LAYOUT;
+      when DIO_ETHERBONE => return c_VIC_ONLY_WB_LAYOUT;
+      when others => return c_NIC_WB_LAYOUT; --by default
+    end case;
+  end function;
+  
+end dio_common_top_pkg;
--- a/hdl/top/dio-etherbone/Manifest.py
+++ b/hdl/top/dio-etherbone/Manifest.py
+files = ["dio_etherbone_top.vhd", "dio_etherbone_top.ucf"]
+
+modules = { "local" : [ "../dio-common",
+                        "../../" ] }
--- a/hdl/top/dio-etherbone/dio_etherbone_top.ucf
+++ b/hdl/top/dio-etherbone/dio_etherbone_top.ucf
+#bank 0
+NET "clk_20m_vcxo_i" LOC = H12;
+NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
+
+NET "clk_125m_pllref_n_i" LOC = F10;
+NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
+NET "clk_125m_pllref_p_i" LOC = G9;
+NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
+
+NET "clk_125m_gtp_n_i" LOC = D11;
+NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
+NET "clk_125m_gtp_p_i" LOC = C11;
+NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
+
+###########################################################################
+## GN4124 PCIe bridge signals
+###########################################################################
+NET "gn_rst_n"       LOC = N20;
+NET "gn_rst_n"       IOSTANDARD = "LVCMOS18";
+NET "gn_p2l_clk_n"   LOC = M19;
+NET "gn_p2l_clk_n"   IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_clk_p"   LOC = M20;
+NET "gn_p2l_clk_p"   IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_rdy"     LOC = J16;
+NET "gn_p2l_rdy"     IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_dframe"  LOC = J22;
+NET "gn_p2l_dframe"  IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_valid"   LOC = L19;
+NET "gn_p2l_valid"   IOSTANDARD = "SSTL18_I";
+
+NET "gn_p2l_data[0]" LOC = K20;
+NET "gn_p2l_data[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[1]" LOC = H22;
+NET "gn_p2l_data[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[2]" LOC = H21;
+NET "gn_p2l_data[2]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[3]" LOC = L17;
+NET "gn_p2l_data[3]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[4]" LOC = K17;
+NET "gn_p2l_data[4]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[5]" LOC = G22;
+NET "gn_p2l_data[5]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[6]" LOC = G20;
+NET "gn_p2l_data[6]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[7]" LOC = K18;
+NET "gn_p2l_data[7]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[8]" LOC = K19;
+NET "gn_p2l_data[8]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[9]" LOC = H20;
+NET "gn_p2l_data[9]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[10]" LOC = J19;
+NET "gn_p2l_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[11]" LOC = E22;
+NET "gn_p2l_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[12]" LOC = E20;
+NET "gn_p2l_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[13]" LOC = F22;
+NET "gn_p2l_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[14]" LOC = F21;
+NET "gn_p2l_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[15]" LOC = H19;
+NET "gn_p2l_data[15]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_p_wr_req[0]" LOC = M22;
+NET "gn_p_wr_req[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_req[1]" LOC = M21;
+NET "gn_p_wr_req[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[0]" LOC = L15;
+NET "gn_p_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[1]" LOC = K16;
+NET "gn_p_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_rx_error"    LOC = J17;
+NET "gn_rx_error"    IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_clkn"    LOC = K22;
+NET "gn_l2p_clkn"    IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_clkp"    LOC = K21;
+NET "gn_l2p_clkp"    IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_dframe"  LOC = U22;
+NET "gn_l2p_dframe"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_valid"   LOC = T18;
+NET "gn_l2p_valid"   IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_edb"     LOC = U20;
+NET "gn_l2p_edb"     IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_data[0]"  LOC = P16;
+NET "gn_l2p_data[0]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[1]"  LOC = P21;
+NET "gn_l2p_data[1]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[2]"  LOC = P18;
+NET "gn_l2p_data[2]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[3]"  LOC = T20;
+NET "gn_l2p_data[3]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[4]"  LOC = V21;
+NET "gn_l2p_data[4]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[5]"  LOC = V19;
+NET "gn_l2p_data[5]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[6]"  LOC = W22;
+NET "gn_l2p_data[6]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[7]"  LOC = Y22;
+NET "gn_l2p_data[7]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[8]"  LOC = P22;
+NET "gn_l2p_data[8]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[9]"  LOC = R22;
+NET "gn_l2p_data[9]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[10]" LOC = T21;
+NET "gn_l2p_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[11]" LOC = T19;
+NET "gn_l2p_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[12]" LOC = V22;
+NET "gn_l2p_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[13]" LOC = V20;
+NET "gn_l2p_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[14]" LOC = W20;
+NET "gn_l2p_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[15]" LOC = Y21;
+NET "gn_l2p_data[15]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_rdy"       LOC = U19;
+NET "gn_l2p_rdy"       IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[0]"   LOC = R20;
+NET "gn_l_wr_rdy[0]"   IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[1]"   LOC = T22;
+NET "gn_l_wr_rdy[1]"   IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[0]" LOC = N16;
+NET "gn_p_rd_d_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[1]" LOC = P19;
+NET "gn_p_rd_d_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_tx_error"      LOC = M17;
+NET "gn_tx_error"      IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[0]"     LOC = B21;
+NET "gn_vc_rdy[0]"     IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[1]"     LOC = B22;
+NET "gn_vc_rdy[1]"     IOSTANDARD = "SSTL18_I";
+
+NET "gn_gpio[1]" LOC = U16;
+NET "gn_gpio[1]" IOSTANDARD = "LVCMOS25";
+NET "gn_gpio[0]" LOC = AB19;
+NET "gn_gpio[0]" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## SPI interface to DACs
+###########################################################################
+NET "plldac_sclk_o" LOC = A4;
+NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "plldac_din_o" LOC = C4;
+NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
+NET "pll25dac_cs_n_o" LOC = A3;
+NET "pll25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
+NET "pll20dac_cs_n_o" LOC = B3;
+NET "pll20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## SFP I/O for transceiver
+###########################################################################
+#NET "sfp_txp_o" IOSTANDARD = "LVDS_12";
+NET "sfp_txp_o" LOC= B16;
+#NET "sfp_txn_o" IOSTANDARD = "LVDS_12";
+NET "sfp_txn_o" LOC= A16;
+#NET "sfp_rxp_i" IOSTANDARD = "LVDS_12";
+NET "sfp_rxp_i" LOC= D15;
+#NET "sfp_rxn_i" IOSTANDARD = "LVDS_12";
+NET "sfp_rxn_i" LOC= C15;
+NET "sfp_mod_def0_i"    LOC = G15;
+NET "sfp_mod_def0_i"    IOSTANDARD = "LVCMOS25";
+NET "sfp_mod_def1_b"    LOC = C17;
+NET "sfp_mod_def1_b"    IOSTANDARD = "LVCMOS25";
+NET "sfp_mod_def2_b"    LOC = G16;
+NET "sfp_mod_def2_b"    IOSTANDARD = "LVCMOS25";
+NET "sfp_rate_select_o" LOC = H14;
+NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
+NET "sfp_tx_fault_i"    LOC = B18;
+NET "sfp_tx_fault_i"    IOSTANDARD = "LVCMOS25";
+NET "sfp_tx_disable_o"  LOC = F17;
+NET "sfp_tx_disable_o"  IOSTANDARD = "LVCMOS25";
+NET "sfp_los_i"         LOC = D18;
+NET "sfp_los_i"         IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## Onewire interface -> thermometer
+###########################################################################
+NET "onewire_b" LOC = D4;
+NET "onewire_b" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## UART
+###########################################################################
+NET "uart_rxd_i" LOC= A2;
+NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
+NET "uart_txd_o" LOC= B2;
+NET "uart_txd_o" IOSTANDARD=LVCMOS25;
+
+###########################################################################
+## Flash memory SPI interface
+###########################################################################
+NET "flash_ncs_o"  LOC = AA3;
+NET "flash_ncs_o"  IOSTANDARD = "LVCMOS25";
+NET "flash_sclk_o" LOC = Y20;
+NET "flash_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "flash_mosi_o" LOC = AB20;
+NET "flash_mosi_o" IOSTANDARD = "LVCMOS25";
+NET "flash_miso_i" LOC = AA20;
+NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## Miscellanous SPEC pins
+###########################################################################
+NET "led_act_o"  LOC = D5;
+NET "led_act_o"  IOSTANDARD = "LVCMOS25";
+NET "led_link_o" LOC = E5;
+NET "led_link_o" IOSTANDARD = "LVCMOS25";
+NET "button1_i"  LOC = C22;
+NET "button1_i"  IOSTANDARD = "LVCMOS18";
+
+###########################################################################
+##  Pin definitions for FmcDio5chttl
+###########################################################################
+NET "dio_clk_p_i" LOC=L20;
+NET "dio_clk_p_i" IOSTANDARD=LVDS_25;
+NET "dio_clk_n_i" LOC=L22;
+NET "dio_clk_n_i" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[4]" LOC =Y11;
+NET "dio_p_i[4]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[4]" LOC =AB11;
+NET "dio_n_i[4]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[3]" LOC =V7;
+NET "dio_p_i[3]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[3]" LOC =W8;
+NET "dio_n_i[3]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[2]" LOC =W12;
+NET "dio_p_i[2]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[2]" LOC =Y12;
+NET "dio_n_i[2]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[1]" LOC =R11;
+NET "dio_p_i[1]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[1]" LOC =T11;
+NET "dio_n_i[1]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[0]" LOC =C19;
+NET "dio_p_i[0]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[0]" LOC =A19;
+NET "dio_n_i[0]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[4]" LOC= T8; 
+NET "dio_n_o[4]" LOC= U8; 
+NET "dio_p_o[4]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[4]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[3]" LOC= U9; 
+NET "dio_n_o[3]" LOC= V9;
+NET "dio_p_o[3]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[3]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[2]" LOC=  R9;
+NET "dio_n_o[2]" LOC=  R8;
+NET "dio_p_o[2]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[2]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[1]" LOC=  Y16;
+NET "dio_n_o[1]" LOC=  W15;
+NET "dio_p_o[1]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[1]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[0]" LOC=  W17;
+NET "dio_n_o[0]" LOC=  Y18;
+NET "dio_p_o[0]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[0]" IOSTANDARD=LVDS_25;
+
+NET "dio_oe_n_o[4]" LOC= AA6;
+NET "dio_oe_n_o[3]" LOC= W10;
+NET "dio_oe_n_o[2]" LOC= W11;
+NET "dio_oe_n_o[1]" LOC= Y14;
+NET "dio_oe_n_o[0]" LOC= V17;
+NET "dio_oe_n_o[4]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[3]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[2]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[1]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[0]" IOSTANDARD=LVCMOS25;
+
+NET "dio_term_en_o[4]" LOC=AB7;
+NET "dio_term_en_o[3]" LOC=Y7;
+NET "dio_term_en_o[2]" LOC=AB6;
+NET "dio_term_en_o[1]" LOC=AB5;
+NET "dio_term_en_o[0]" LOC=W18;
+NET "dio_term_en_o[4]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[3]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[2]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[1]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[0]" IOSTANDARD=LVCMOS25;
+
+NET "dio_led_top_o" LOC= AA12;
+NET "dio_led_top_o" IOSTANDARD=LVCMOS25;
+NET "dio_led_bot_o" LOC= AB12;
+NET "dio_led_bot_o" IOSTANDARD=LVCMOS25;
+
+NET "dio_scl_b" LOC = F7;
+NET "dio_scl_b" IOSTANDARD = "LVCMOS25";
+NET "dio_sda_b" LOC = F8;
+NET "dio_sda_b" IOSTANDARD = "LVCMOS25";
+
+NET "dio_onewire_b" LOC=AB16;
+NET "dio_onewire_b" IOSTANDARD=LVCMOS25;
+
+NET "dio_sdn_n_o" LOC=  V11;
+NET "dio_sdn_n_o" IOSTANDARD=LVCMOS25;
+
+NET "dio_sdn_ck_n_o" LOC=  Y5;
+NET "dio_sdn_ck_n_o" IOSTANDARD=LVCMOS25;
+
+# GN4124
+NET "gn_p2l_clk_p" TNM_NET = "gn_p2l_clkp_grp";
+NET "gn_p2l_clk_n" TNM_NET = "gn_p2l_clkn_grp";
+TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_dio_etherbone/cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
+NET "gn_rst_n" TIG;
+NET "cmp_dio_etherbone/cmp_gn4124_core/rst_*" TIG;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
+NET "cmp_dio_etherbone/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_dio_etherbone/cmp_gn4124_core/cmp_clk_in/P_clk;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
+NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
+TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
+NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
+TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
+NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
+TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
+NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
+TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
+NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
+TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
+# 10MHz reference clock input
+NET "dio_clk_p_i" TNM_NET = dio_clk_p_i;
+TIMESPEC TS_dio_clk_p_i = PERIOD "dio_clk_p_i" 100 ns HIGH 50%;
+NET "dio_clk_n_i" TNM_NET = dio_clk_n_i;
+TIMESPEC TS_dio_clk_n_i = PERIOD "dio_clk_n_i" 100 ns HIGH 50%;
+
+# Needed only when DMTD samples 125m refclock (clock has to be fed to D input of
+# a flip-flop).
+# However, in case of SPEC we use g_divide_input_by_2 generic in the dmtd_with_deglitcher.
+# This re-generates 62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D
+# input of a flip-flop. This constraint would be needed e.g. for Kintex, where
+# refclock is 62.5MHz and we don't use g_divide_input_by_2.
+#PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE; 
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20
+NET "cmp_dio_etherbone/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_dio_etherbone/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
+TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_dio_etherbone/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
+# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; 
+##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
+
+TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
+
+#INST "cmp_dio_etherbone/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
--- a/hdl/top/dio-etherbone/dio_etherbone_top.vhd
+++ b/hdl/top/dio-etherbone/dio_etherbone_top.vhd
+-------------------------------------------------------------------------------
+-- Title      : DIO design with Etherbone core.
+-- Project    : FMC DIO 5CH TTa
+-------------------------------------------------------------------------------
+-- File       : dio_etherbone_top.vhd
+-- Author     : Miguel Jimenez-Lopez
+-- Company    : Seven Solutions
+-- Created    : 2019-03-27
+-- Last update: 2019-03-27
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- DIO design with Etherbone capabilities.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 Seven Solutions
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2019-03-27  1.0      klyone          Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.dio_common_top_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity dio_etherbone_top is
+  generic (
+    g_dpram_initf : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
+    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
+    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
+    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
+    g_simulation : integer := 0
+  );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- Local oscillators
+    clk_20m_vcxo_i : in std_logic;                -- 20MHz VCXO clock
+
+    clk_125m_pllref_p_i : in std_logic;           -- 125 MHz PLL reference
+    clk_125m_pllref_n_i : in std_logic;
+
+    clk_125m_gtp_n_i : in std_logic;              -- 125 MHz GTP reference
+    clk_125m_gtp_p_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- GN4124 PCIe bridge signals
+    ---------------------------------------------------------------------------
+    -- From GN4124 Local bus
+    gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
+    -- PCIe to Local [Inbound Data] - RX
+    gn_p2l_clk_n  : in  std_logic;       -- Receiver Source Synchronous Clock-
+    gn_p2l_clk_p  : in  std_logic;       -- Receiver Source Synchronous Clock+
+    gn_p2l_rdy    : out std_logic;       -- Rx Buffer Full Flag
+    gn_p2l_dframe : in  std_logic;       -- Receive Frame
+    gn_p2l_valid  : in  std_logic;       -- Receive Data Valid
+    gn_p2l_data   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
+    -- Inbound Buffer Request/Status
+    gn_p_wr_req   : in  std_logic_vector(1 downto 0);  -- PCIe Write Request
+    gn_p_wr_rdy   : out std_logic_vector(1 downto 0);  -- PCIe Write Ready
+    gn_rx_error   : out std_logic;                     -- Receive Error
+    -- Local to Parallel [Outbound Data] - TX
+    gn_l2p_clkn   : out std_logic;       -- Transmitter Source Synchronous Clock-
+    gn_l2p_clkp   : out std_logic;       -- Transmitter Source Synchronous Clock+
+    gn_l2p_dframe : out std_logic;       -- Transmit Data Frame
+    gn_l2p_valid  : out std_logic;       -- Transmit Data Valid
+    gn_l2p_edb    : out std_logic;       -- Packet termination and discard
+    gn_l2p_data   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
+    -- Outbound Buffer Status
+    gn_l2p_rdy    : in std_logic;                     -- Tx Buffer Full Flag
+    gn_l_wr_rdy   : in std_logic_vector(1 downto 0);  -- Local-to-PCIe Write
+    gn_p_rd_d_rdy : in std_logic_vector(1 downto 0);  -- PCIe-to-Local Read Response Data Ready
+    gn_tx_error   : in std_logic;                     -- Transmit Error
+    gn_vc_rdy     : in std_logic_vector(1 downto 0);  -- Channel ready
+    -- General Purpose Interface
+    gn_gpio : inout std_logic_vector(1 downto 0);  -- gn_gpio[0] -> GN4124 GPIO8
+                                                   -- gn_gpio[1] -> GN4124 GPIO9
+    ---------------------------------------------------------------------------
+    -- SPI interface to DACs
+    ---------------------------------------------------------------------------
+
+    plldac_sclk_o     : out std_logic;
+    plldac_din_o      : out std_logic;
+    pll25dac_cs_n_o : out std_logic; --cs1
+    pll20dac_cs_n_o : out std_logic; --cs2
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver
+    ---------------------------------------------------------------------------
+
+    sfp_txp_o         : out   std_logic;
+    sfp_txn_o         : out   std_logic;
+    sfp_rxp_i         : in    std_logic;
+    sfp_rxn_i         : in    std_logic;
+    sfp_mod_def0_i    : in    std_logic;          -- sfp detect
+    sfp_mod_def1_b    : inout std_logic;          -- scl
+    sfp_mod_def2_b    : inout std_logic;          -- sda
+    sfp_rate_select_o : out   std_logic;
+    sfp_tx_fault_i    : in    std_logic;
+    sfp_tx_disable_o  : out   std_logic;
+    sfp_los_i         : in    std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+
+    onewire_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Miscellanous SPEC pins
+    ---------------------------------------------------------------------------
+    -- Red LED next to the SFP: blinking indicates that packets are being
+    -- transferred.
+    led_act_o   : out std_logic;
+    -- Green LED next to the SFP: indicates if the link is up.
+    led_link_o : out std_logic;
+
+    button1_i   : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Digital I/O FMC Pins
+    -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
+    -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
+    ---------------------------------------------------------------------------
+
+    -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
+    -- external reference input.
+    dio_clk_p_i : in std_logic;
+    dio_clk_n_i : in std_logic;
+
+    -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
+    -- the mezzanine front panel.
+    dio_n_i : in std_logic_vector(4 downto 0);
+    dio_p_i : in std_logic_vector(4 downto 0);
+
+    -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
+    -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
+    -- of I/O (N+1) on the front panel of the mezzanine
+    dio_n_o : out std_logic_vector(4 downto 0);
+    dio_p_o : out std_logic_vector(4 downto 0);
+
+    -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
+    -- panel is configured as an output.
+    dio_oe_n_o    : out std_logic_vector(4 downto 0);
+
+    -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
+    -- panel is 50-ohm terminated
+    dio_term_en_o : out std_logic_vector(4 downto 0);
+
+    -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
+    -- blink 1-PPS.
+    dio_led_top_o : out std_logic;
+    dio_led_bot_o : out std_logic;
+
+    -- DIO 1-wire bus
+    dio_onewire_b  : inout std_logic;
+    dio_sdn_n_o    : out   std_logic;
+    dio_sdn_ck_n_o : out   std_logic;
+
+    -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
+    -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
+    dio_scl_b : inout std_logic;
+    dio_sda_b : inout std_logic
+
+  );
+end entity dio_etherbone_top;
+
+architecture top of dio_etherbone_top is
+begin
+
+  cmp_dio_etherbone : dio_common_top
+  generic map (
+    g_dio_mode => DIO_ETHERBONE,
+    g_dpram_initf => g_dpram_initf,
+    g_simulation => g_simulation
+  )
+  port map (
+    clk_20m_vcxo_i => clk_20m_vcxo_i,
+    clk_125m_pllref_p_i => clk_125m_pllref_p_i,
+    clk_125m_pllref_n_i => clk_125m_pllref_n_i,
+    clk_125m_gtp_n_i => clk_125m_gtp_n_i,
+    clk_125m_gtp_p_i => clk_125m_gtp_p_i,
+    gn_rst_n => gn_rst_n,
+    gn_p2l_clk_n => gn_p2l_clk_n,
+    gn_p2l_clk_p => gn_p2l_clk_p,
+    gn_p2l_rdy => gn_p2l_rdy,
+    gn_p2l_dframe => gn_p2l_dframe,
+    gn_p2l_valid => gn_p2l_valid,
+    gn_p2l_data => gn_p2l_data,
+    gn_p_wr_req => gn_p_wr_req,
+    gn_p_wr_rdy => gn_p_wr_rdy,
+    gn_rx_error => gn_rx_error,
+    gn_l2p_clkn => gn_l2p_clkn,
+    gn_l2p_clkp => gn_l2p_clkp,
+    gn_l2p_dframe => gn_l2p_dframe,
+    gn_l2p_valid => gn_l2p_valid,
+    gn_l2p_edb => gn_l2p_edb,
+    gn_l2p_data => gn_l2p_data,
+    gn_l2p_rdy => gn_l2p_rdy,
+    gn_l_wr_rdy => gn_l_wr_rdy,
+    gn_p_rd_d_rdy => gn_p_rd_d_rdy,
+    gn_tx_error => gn_tx_error,
+    gn_vc_rdy => gn_vc_rdy,
+    gn_gpio => gn_gpio,
+    plldac_sclk_o => plldac_sclk_o,
+    plldac_din_o => plldac_din_o,
+    pll25dac_cs_n_o => pll25dac_cs_n_o,
+    pll20dac_cs_n_o => pll20dac_cs_n_o,
+    sfp_txp_o => sfp_txp_o,
+    sfp_txn_o => sfp_txn_o,
+    sfp_rxp_i => sfp_rxp_i,
+    sfp_rxn_i => sfp_rxn_i,
+    sfp_mod_def0_i => sfp_mod_def0_i,
+    sfp_mod_def1_b => sfp_mod_def1_b,
+    sfp_mod_def2_b => sfp_mod_def2_b,
+    sfp_rate_select_o => sfp_rate_select_o,
+    sfp_tx_fault_i => sfp_tx_fault_i,
+    sfp_tx_disable_o => sfp_tx_disable_o,
+    sfp_los_i => sfp_los_i,
+    onewire_b => onewire_b,
+    uart_rxd_i => uart_rxd_i,
+    uart_txd_o => uart_txd_o,
+    flash_sclk_o => flash_sclk_o,
+    flash_ncs_o => flash_ncs_o,
+    flash_mosi_o => flash_mosi_o,
+    flash_miso_i => flash_miso_i,
+    led_act_o => led_act_o,
+    led_link_o => led_link_o,
+    button1_i => button1_i,
+    dio_clk_p_i => dio_clk_p_i,
+    dio_clk_n_i => dio_clk_n_i,
+    dio_n_i => dio_n_i,
+    dio_p_i => dio_p_i,
+    dio_n_o => dio_n_o,
+    dio_p_o => dio_p_o,
+    dio_oe_n_o => dio_oe_n_o,
+    dio_term_en_o => dio_term_en_o,
+    dio_led_top_o => dio_led_top_o,
+    dio_led_bot_o => dio_led_bot_o,
+    dio_onewire_b => dio_onewire_b,
+    dio_sdn_n_o => dio_sdn_n_o,
+    dio_sdn_ck_n_o => dio_sdn_ck_n_o,
+    dio_scl_b => dio_scl_b,
+    dio_sda_b => dio_sda_b
+  );
+
+end architecture top;
--- a/hdl/top/dio-ext-nic-etherbone/Manifest.py
+++ b/hdl/top/dio-ext-nic-etherbone/Manifest.py
+files = ["dio_ext_nic_etherbone_top.vhd", "dio_ext_nic_etherbone_top.ucf"]
+
+modules = { "local" : [ "../../" ] }
--- a/hdl/top/dio-ext-nic-etherbone/dio_ext_nic_etherbone_top.ucf
+++ b/hdl/top/dio-ext-nic-etherbone/dio_ext_nic_etherbone_top.ucf
+#bank 0
+NET "clk_20m_vcxo_i" LOC = H12;
+NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
+
+NET "clk_125m_pllref_n_i" LOC = F10;
+NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
+NET "clk_125m_pllref_p_i" LOC = G9;
+NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
+
+NET "clk_125m_gtp_n_i" LOC = D11;
+NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
+NET "clk_125m_gtp_p_i" LOC = C11;
+NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
+
+###########################################################################
+## GN4124 PCIe bridge signals
+###########################################################################
+NET "gn_rst_n"       LOC = N20;
+NET "gn_rst_n"       IOSTANDARD = "LVCMOS18";
+NET "gn_p2l_clk_n"   LOC = M19;
+NET "gn_p2l_clk_n"   IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_clk_p"   LOC = M20;
+NET "gn_p2l_clk_p"   IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_rdy"     LOC = J16;
+NET "gn_p2l_rdy"     IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_dframe"  LOC = J22;
+NET "gn_p2l_dframe"  IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_valid"   LOC = L19;
+NET "gn_p2l_valid"   IOSTANDARD = "SSTL18_I";
+
+NET "gn_p2l_data[0]" LOC = K20;
+NET "gn_p2l_data[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[1]" LOC = H22;
+NET "gn_p2l_data[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[2]" LOC = H21;
+NET "gn_p2l_data[2]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[3]" LOC = L17;
+NET "gn_p2l_data[3]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[4]" LOC = K17;
+NET "gn_p2l_data[4]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[5]" LOC = G22;
+NET "gn_p2l_data[5]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[6]" LOC = G20;
+NET "gn_p2l_data[6]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[7]" LOC = K18;
+NET "gn_p2l_data[7]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[8]" LOC = K19;
+NET "gn_p2l_data[8]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[9]" LOC = H20;
+NET "gn_p2l_data[9]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[10]" LOC = J19;
+NET "gn_p2l_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[11]" LOC = E22;
+NET "gn_p2l_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[12]" LOC = E20;
+NET "gn_p2l_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[13]" LOC = F22;
+NET "gn_p2l_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[14]" LOC = F21;
+NET "gn_p2l_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[15]" LOC = H19;
+NET "gn_p2l_data[15]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_p_wr_req[0]" LOC = M22;
+NET "gn_p_wr_req[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_req[1]" LOC = M21;
+NET "gn_p_wr_req[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[0]" LOC = L15;
+NET "gn_p_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[1]" LOC = K16;
+NET "gn_p_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_rx_error"    LOC = J17;
+NET "gn_rx_error"    IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_clkn"    LOC = K22;
+NET "gn_l2p_clkn"    IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_clkp"    LOC = K21;
+NET "gn_l2p_clkp"    IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_dframe"  LOC = U22;
+NET "gn_l2p_dframe"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_valid"   LOC = T18;
+NET "gn_l2p_valid"   IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_edb"     LOC = U20;
+NET "gn_l2p_edb"     IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_data[0]"  LOC = P16;
+NET "gn_l2p_data[0]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[1]"  LOC = P21;
+NET "gn_l2p_data[1]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[2]"  LOC = P18;
+NET "gn_l2p_data[2]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[3]"  LOC = T20;
+NET "gn_l2p_data[3]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[4]"  LOC = V21;
+NET "gn_l2p_data[4]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[5]"  LOC = V19;
+NET "gn_l2p_data[5]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[6]"  LOC = W22;
+NET "gn_l2p_data[6]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[7]"  LOC = Y22;
+NET "gn_l2p_data[7]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[8]"  LOC = P22;
+NET "gn_l2p_data[8]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[9]"  LOC = R22;
+NET "gn_l2p_data[9]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[10]" LOC = T21;
+NET "gn_l2p_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[11]" LOC = T19;
+NET "gn_l2p_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[12]" LOC = V22;
+NET "gn_l2p_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[13]" LOC = V20;
+NET "gn_l2p_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[14]" LOC = W20;
+NET "gn_l2p_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[15]" LOC = Y21;
+NET "gn_l2p_data[15]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_rdy"       LOC = U19;
+NET "gn_l2p_rdy"       IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[0]"   LOC = R20;
+NET "gn_l_wr_rdy[0]"   IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[1]"   LOC = T22;
+NET "gn_l_wr_rdy[1]"   IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[0]" LOC = N16;
+NET "gn_p_rd_d_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[1]" LOC = P19;
+NET "gn_p_rd_d_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_tx_error"      LOC = M17;
+NET "gn_tx_error"      IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[0]"     LOC = B21;
+NET "gn_vc_rdy[0]"     IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[1]"     LOC = B22;
+NET "gn_vc_rdy[1]"     IOSTANDARD = "SSTL18_I";
+
+NET "gn_gpio[1]" LOC = U16;
+NET "gn_gpio[1]" IOSTANDARD = "LVCMOS25";
+NET "gn_gpio[0]" LOC = AB19;
+NET "gn_gpio[0]" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## SPI interface to DACs
+###########################################################################
+NET "plldac_sclk_o" LOC = A4;
+NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "plldac_din_o" LOC = C4;
+NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
+NET "pll25dac_cs_n_o" LOC = A3;
+NET "pll25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
+NET "pll20dac_cs_n_o" LOC = B3;
+NET "pll20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## SFP I/O for transceiver
+###########################################################################
+#NET "sfp_txp_o" IOSTANDARD = "LVDS_12";
+NET "sfp_txp_o" LOC= B16;
+#NET "sfp_txn_o" IOSTANDARD = "LVDS_12";
+NET "sfp_txn_o" LOC= A16;
+#NET "sfp_rxp_i" IOSTANDARD = "LVDS_12";
+NET "sfp_rxp_i" LOC= D15;
+#NET "sfp_rxn_i" IOSTANDARD = "LVDS_12";
+NET "sfp_rxn_i" LOC= C15;
+NET "sfp_mod_def0_i"    LOC = G15;
+NET "sfp_mod_def0_i"    IOSTANDARD = "LVCMOS25";
+NET "sfp_mod_def1_b"    LOC = C17;
+NET "sfp_mod_def1_b"    IOSTANDARD = "LVCMOS25";
+NET "sfp_mod_def2_b"    LOC = G16;
+NET "sfp_mod_def2_b"    IOSTANDARD = "LVCMOS25";
+NET "sfp_rate_select_o" LOC = H14;
+NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
+NET "sfp_tx_fault_i"    LOC = B18;
+NET "sfp_tx_fault_i"    IOSTANDARD = "LVCMOS25";
+NET "sfp_tx_disable_o"  LOC = F17;
+NET "sfp_tx_disable_o"  IOSTANDARD = "LVCMOS25";
+NET "sfp_los_i"         LOC = D18;
+NET "sfp_los_i"         IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## Onewire interface -> thermometer
+###########################################################################
+NET "onewire_b" LOC = D4;
+NET "onewire_b" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## UART
+###########################################################################
+NET "uart_rxd_i" LOC= A2;
+NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
+NET "uart_txd_o" LOC= B2;
+NET "uart_txd_o" IOSTANDARD=LVCMOS25;
+
+###########################################################################
+## Flash memory SPI interface
+###########################################################################
+NET "flash_ncs_o"  LOC = AA3;
+NET "flash_ncs_o"  IOSTANDARD = "LVCMOS25";
+NET "flash_sclk_o" LOC = Y20;
+NET "flash_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "flash_mosi_o" LOC = AB20;
+NET "flash_mosi_o" IOSTANDARD = "LVCMOS25";
+NET "flash_miso_i" LOC = AA20;
+NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## Miscellanous SPEC pins
+###########################################################################
+NET "led_act_o"  LOC = D5;
+NET "led_act_o"  IOSTANDARD = "LVCMOS25";
+NET "led_link_o" LOC = E5;
+NET "led_link_o" IOSTANDARD = "LVCMOS25";
+NET "button1_i"  LOC = C22;
+NET "button1_i"  IOSTANDARD = "LVCMOS18";
+
+###########################################################################
+##  Pin definitions for FmcDio5chttl
+###########################################################################
+NET "dio_clk_p_i" LOC=L20;
+NET "dio_clk_p_i" IOSTANDARD=LVDS_25;
+NET "dio_clk_n_i" LOC=L22;
+NET "dio_clk_n_i" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[4]" LOC =Y11;
+NET "dio_p_i[4]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[4]" LOC =AB11;
+NET "dio_n_i[4]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[3]" LOC =V7;
+NET "dio_p_i[3]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[3]" LOC =W8;
+NET "dio_n_i[3]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[2]" LOC =W12;
+NET "dio_p_i[2]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[2]" LOC =Y12;
+NET "dio_n_i[2]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[1]" LOC =R11;
+NET "dio_p_i[1]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[1]" LOC =T11;
+NET "dio_n_i[1]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[0]" LOC =C19;
+NET "dio_p_i[0]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[0]" LOC =A19;
+NET "dio_n_i[0]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[4]" LOC= T8; 
+NET "dio_n_o[4]" LOC= U8; 
+NET "dio_p_o[4]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[4]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[3]" LOC= U9; 
+NET "dio_n_o[3]" LOC= V9;
+NET "dio_p_o[3]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[3]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[2]" LOC=  R9;
+NET "dio_n_o[2]" LOC=  R8;
+NET "dio_p_o[2]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[2]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[1]" LOC=  Y16;
+NET "dio_n_o[1]" LOC=  W15;
+NET "dio_p_o[1]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[1]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[0]" LOC=  W17;
+NET "dio_n_o[0]" LOC=  Y18;
+NET "dio_p_o[0]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[0]" IOSTANDARD=LVDS_25;
+
+NET "dio_oe_n_o[4]" LOC= AA6;
+NET "dio_oe_n_o[3]" LOC= W10;
+NET "dio_oe_n_o[2]" LOC= W11;
+NET "dio_oe_n_o[1]" LOC= Y14;
+NET "dio_oe_n_o[0]" LOC= V17;
+NET "dio_oe_n_o[4]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[3]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[2]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[1]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[0]" IOSTANDARD=LVCMOS25;
+
+NET "dio_term_en_o[4]" LOC=AB7;
+NET "dio_term_en_o[3]" LOC=Y7;
+NET "dio_term_en_o[2]" LOC=AB6;
+NET "dio_term_en_o[1]" LOC=AB5;
+NET "dio_term_en_o[0]" LOC=W18;
+NET "dio_term_en_o[4]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[3]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[2]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[1]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[0]" IOSTANDARD=LVCMOS25;
+
+NET "dio_led_top_o" LOC= AA12;
+NET "dio_led_top_o" IOSTANDARD=LVCMOS25;
+NET "dio_led_bot_o" LOC= AB12;
+NET "dio_led_bot_o" IOSTANDARD=LVCMOS25;
+
+NET "dio_scl_b" LOC = F7;
+NET "dio_scl_b" IOSTANDARD = "LVCMOS25";
+NET "dio_sda_b" LOC = F8;
+NET "dio_sda_b" IOSTANDARD = "LVCMOS25";
+
+NET "dio_onewire_b" LOC=AB16;
+NET "dio_onewire_b" IOSTANDARD=LVCMOS25;
+
+NET "dio_sdn_n_o" LOC=  V11;
+NET "dio_sdn_n_o" IOSTANDARD=LVCMOS25;
+
+NET "dio_sdn_ck_n_o" LOC=  Y5;
+NET "dio_sdn_ck_n_o" IOSTANDARD=LVCMOS25;
+
+# GN4124
+NET "gn_p2l_clk_p" TNM_NET = "gn_p2l_clkp_grp";
+NET "gn_p2l_clk_n" TNM_NET = "gn_p2l_clkn_grp";
+TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
+NET "gn_rst_n" TIG;
+NET "cmp_gn4124_core/rst_*" TIG;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
+NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
+NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
+TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
+NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
+TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
+NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
+TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
+NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
+TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
+NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
+TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
+# 10MHz reference clock input
+NET "dio_clk_p_i" TNM_NET = dio_clk_p_i;
+TIMESPEC TS_dio_clk_p_i = PERIOD "dio_clk_p_i" 100 ns HIGH 50%;
+NET "dio_clk_n_i" TNM_NET = dio_clk_n_i;
+TIMESPEC TS_dio_clk_n_i = PERIOD "dio_clk_n_i" 100 ns HIGH 50%;
+
+# Needed only when DMTD samples 125m refclock (clock has to be fed to D input of
+# a flip-flop).
+# However, in case of SPEC we use g_divide_input_by_2 generic in the dmtd_with_deglitcher.
+# This re-generates 62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D
+# input of a flip-flop. This constraint would be needed e.g. for Kintex, where
+# refclock is 62.5MHz and we don't use g_divide_input_by_2.
+#PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE; 
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20
+NET "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
+TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
+# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; 
+##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
+
+TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
+
+# FIXME: It provokes an error in implementation stage
+# Force PPS output to always be placed as IOB register
+#INST "cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
--- a/hdl/top/dio-ext-nic-etherbone/dio_ext_nic_etherbone_top.vhd
+++ b/hdl/top/dio-ext-nic-etherbone/dio_ext_nic_etherbone_top.vhd
+-------------------------------------------------------------------------------
+-- Title      : DIO FMC project with NIC and Etherbone Support
+-- Project    : FMC DIO 5CH TTa
+-------------------------------------------------------------------------------
+-- File       : dio_ext_nic_etherbone.vhd
+-- Author     : Grzegorz Daniluk, Rafael Rodriguez, Javier Díaz, Miguel Jimenez
+-- Company    : Elproma, Seven Solutions, UGR
+-- Created    : 2012-02-08
+-- Last update: 2019-03-27
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- This design contains the old configuration for the WR-NIC project with DIO,
+-- Etherbone and NIC capabilities.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 Grzegorz Daniluk, Rafael Rodriguez, Javier Díaz
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-02-08  1.0      greg.d          Created
+-- 2012-02-20  1.1      greg.d          added GN4124 to wrsw_nic DMA connection
+-- 2012-03-10  1.2      rafa.r          added dio_core
+-- 2012-06-25  1.3      jdiaz           New dio_functionality
+-- 2012-07-06  1.4      jdiaz           Updating of files and integration test
+-- 2012-07-06  1.5      ben.r           Adding PPS to dio & reset
+-- 2019-03-27  1.6      klyone          Migrate to the WRPC 4.2. Use BSP module
+-------------------------------------------------------------------------------
+--
+-- Memory map:
+--  0x00000000: WRPC
+--     0x00000: WRPC I/D Memory
+--     0x20000: WRPC Peripheral interconnect
+--      +0x000: WRPC Minic
+--      +0x100: WRPC Endpoint
+--      +0x200: WRPC Softpll
+--      +0x300: WRPC PPS gen
+--      +0x400: WRPC Syscon
+--      +0x500: WRPC UART
+--      +0x600: WRPC OneWire
+--      +0x700: WRPC Auxillary space (Etherbone config, etc)
+--		+0x800: WRPC Diags
+--  0x00040000: WRSW NIC
+--  0x00060000: VIC
+--  0x00061000: TxTSU
+--  0x00062000: DIO
+--       0x000: DIO-ONEWIRE
+--       0x100: DIO-I2C
+--       0x200: DIO-GPIO
+--       0x300: DIO-TIMING REGISTERS
+--  0x00063000: SDB-BRIDGE --> MAGIC NUMBER
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_spec_pkg.all;
+use work.gn4124_core_pkg.all;
+use work.wrcore_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_nic_wrapper_pkg.all;
+use work.wr_dio_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity dio_ext_nic_etherbone_top is
+  generic (
+    g_etherbone_ext : boolean := true;
+    g_dpram_initf : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
+    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
+    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
+    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
+    g_simulation : integer := 0
+  );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- Local oscillators
+    clk_20m_vcxo_i : in std_logic;                -- 20MHz VCXO clock
+
+    clk_125m_pllref_p_i : in std_logic;           -- 125 MHz PLL reference
+    clk_125m_pllref_n_i : in std_logic;
+
+    clk_125m_gtp_n_i : in std_logic;              -- 125 MHz GTP reference
+    clk_125m_gtp_p_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- GN4124 PCIe bridge signals
+    ---------------------------------------------------------------------------
+    -- From GN4124 Local bus
+    gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
+    -- PCIe to Local [Inbound Data] - RX
+    gn_p2l_clk_n  : in  std_logic;       -- Receiver Source Synchronous Clock-
+    gn_p2l_clk_p  : in  std_logic;       -- Receiver Source Synchronous Clock+
+    gn_p2l_rdy    : out std_logic;       -- Rx Buffer Full Flag
+    gn_p2l_dframe : in  std_logic;       -- Receive Frame
+    gn_p2l_valid  : in  std_logic;       -- Receive Data Valid
+    gn_p2l_data   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
+    -- Inbound Buffer Request/Status
+    gn_p_wr_req   : in  std_logic_vector(1 downto 0);  -- PCIe Write Request
+    gn_p_wr_rdy   : out std_logic_vector(1 downto 0);  -- PCIe Write Ready
+    gn_rx_error   : out std_logic;                     -- Receive Error
+    -- Local to Parallel [Outbound Data] - TX
+    gn_l2p_clkn   : out std_logic;       -- Transmitter Source Synchronous Clock-
+    gn_l2p_clkp   : out std_logic;       -- Transmitter Source Synchronous Clock+
+    gn_l2p_dframe : out std_logic;       -- Transmit Data Frame
+    gn_l2p_valid  : out std_logic;       -- Transmit Data Valid
+    gn_l2p_edb    : out std_logic;       -- Packet termination and discard
+    gn_l2p_data   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
+    -- Outbound Buffer Status
+    gn_l2p_rdy    : in std_logic;                     -- Tx Buffer Full Flag
+    gn_l_wr_rdy   : in std_logic_vector(1 downto 0);  -- Local-to-PCIe Write
+    gn_p_rd_d_rdy : in std_logic_vector(1 downto 0);  -- PCIe-to-Local Read Response Data Ready
+    gn_tx_error   : in std_logic;                     -- Transmit Error
+    gn_vc_rdy     : in std_logic_vector(1 downto 0);  -- Channel ready
+    -- General Purpose Interface
+    gn_gpio : inout std_logic_vector(1 downto 0);  -- gn_gpio[0] -> GN4124 GPIO8
+                                                   -- gn_gpio[1] -> GN4124 GPIO9
+    ---------------------------------------------------------------------------
+    -- SPI interface to DACs
+    ---------------------------------------------------------------------------
+
+    plldac_sclk_o     : out std_logic;
+    plldac_din_o      : out std_logic;
+    pll25dac_cs_n_o : out std_logic; --cs1
+    pll20dac_cs_n_o : out std_logic; --cs2
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver
+    ---------------------------------------------------------------------------
+
+    sfp_txp_o         : out   std_logic;
+    sfp_txn_o         : out   std_logic;
+    sfp_rxp_i         : in    std_logic;
+    sfp_rxn_i         : in    std_logic;
+    sfp_mod_def0_i    : in    std_logic;          -- sfp detect
+    sfp_mod_def1_b    : inout std_logic;          -- scl
+    sfp_mod_def2_b    : inout std_logic;          -- sda
+    sfp_rate_select_o : out   std_logic;
+    sfp_tx_fault_i    : in    std_logic;
+    sfp_tx_disable_o  : out   std_logic;
+    sfp_los_i         : in    std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+
+    onewire_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Miscellanous SPEC pins
+    ---------------------------------------------------------------------------
+    -- Red LED next to the SFP: blinking indicates that packets are being
+    -- transferred.
+    led_act_o   : out std_logic;
+    -- Green LED next to the SFP: indicates if the link is up.
+    led_link_o : out std_logic;
+
+    button1_i   : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Digital I/O FMC Pins
+    -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
+    -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
+    ---------------------------------------------------------------------------
+
+    -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
+    -- external reference input.
+    dio_clk_p_i : in std_logic;
+    dio_clk_n_i : in std_logic;
+
+    -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
+    -- the mezzanine front panel.
+    dio_n_i : in std_logic_vector(4 downto 0);
+    dio_p_i : in std_logic_vector(4 downto 0);
+
+    -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
+    -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
+    -- of I/O (N+1) on the front panel of the mezzanine
+    dio_n_o : out std_logic_vector(4 downto 0);
+    dio_p_o : out std_logic_vector(4 downto 0);
+
+    -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
+    -- panel is configured as an output.
+    dio_oe_n_o    : out std_logic_vector(4 downto 0);
+
+    -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
+    -- panel is 50-ohm terminated
+    dio_term_en_o : out std_logic_vector(4 downto 0);
+
+    -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
+    -- blink 1-PPS.
+    dio_led_top_o : out std_logic;
+    dio_led_bot_o : out std_logic;
+
+    -- DIO 1-wire bus
+    dio_onewire_b  : inout std_logic;
+    dio_sdn_n_o    : out   std_logic;
+    dio_sdn_ck_n_o : out   std_logic;
+
+    -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
+    -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
+    dio_scl_b : inout std_logic;
+    dio_sda_b : inout std_logic
+
+  );
+end entity dio_ext_nic_etherbone_top;
+
+architecture top of dio_ext_nic_etherbone_top is
+
+  -----------------------------------------------------------------------------
+  -- Components
+  -----------------------------------------------------------------------------
+  component xwr_dio
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD
+      );
+    port (
+      clk_sys_i : in std_logic;
+      clk_ref_i : in std_logic;
+      rst_n_i   : in std_logic;
+
+      dio_clk_i      : in    std_logic;
+      dio_pps_i      : in    std_logic;
+      dio_in_i       : in    std_logic_vector(4 downto 0);
+      dio_out_o      : out   std_logic_vector(4 downto 0);
+      dio_oe_n_o     : out   std_logic_vector(4 downto 0);
+      dio_term_en_o  : out   std_logic_vector(4 downto 0);
+      dio_onewire_b  : inout std_logic;
+      dio_sdn_n_o    : out   std_logic;
+      dio_sdn_ck_n_o : out   std_logic;
+      dio_led_top_o  : out   std_logic;
+      dio_led_bot_o  : out   std_logic;
+
+      dio_scl_b : inout std_logic;
+      dio_sda_b : inout std_logic;
+      dio_ga_o  : out std_logic_vector(1 downto 0);
+
+      tm_time_valid_i : in std_logic;
+      tm_seconds_i        : in std_logic_vector(39 downto 0);
+      tm_cycles_i     : in std_logic_vector(27 downto 0);
+
+      TRIG0 : out std_logic_vector(31 downto 0);
+      TRIG1 : out std_logic_vector(31 downto 0);
+      TRIG2 : out std_logic_vector(31 downto 0);
+      TRIG3 : out std_logic_vector(31 downto 0);
+
+      slave_i                      : in  t_wishbone_slave_in;
+      slave_o                      : out t_wishbone_slave_out;
+      dio_int                      : out std_logic
+  );
+  end component; 
+
+  -----------------------------------------------------------------------------
+  -- Constants
+  -----------------------------------------------------------------------------
+  -- Number of interrupts
+  constant c_NUM_IRQS : integer := 3;
+
+  -- Interrupts IDs
+  constant c_IRQ_TXTSU : integer := 0;
+  constant c_IRQ_NIC : integer := 1;
+  constant c_IRQ_PPS : integer := 2;
+  constant c_IRQ_DIO : integer := 3;
+
+  -- Number of masters on the wishbone crossbar
+  constant c_NUM_WB_MASTERS : integer := 2;
+
+  -- Number of slaves on the primary wishbone crossbar
+  constant c_NUM_WB_SLAVES : integer := 5;
+
+  -- Primary Wishbone master(s) offsets
+  constant c_WB_MASTER_PCIE    : integer := 0;
+  constant c_WB_MASTER_ETHBONE : integer := 1;
+
+  -- Primary Wishbone slave(s) offsets
+  constant c_WB_SLAVE_WRC : integer := 0;
+  constant c_WB_SLAVE_NIC : integer := 1;
+  constant c_WB_SLAVE_VIC : integer := 2;
+  constant c_WB_SLAVE_TXTSU : integer := 3;
+  constant c_WB_SLAVE_DIO : integer := 4;
+
+  -- sdb header address on primary crossbar
+  constant c_SDB_ADDRESS : t_wishbone_address := x"00063000";
+
+  -- f_xwb_bridge_manual_sdb(size, sdb_addr)
+  -- Note: sdb_addr is the sdb records address relative to the bridge base address
+  constant c_wrc_bridge_sdb : t_sdb_bridge :=
+    f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
+	 
+  constant c_wr_dio_bridge_sdb : t_sdb_bridge :=
+    f_xwb_bridge_product_manual_sdb(x"00000fff", x"00000400", c_xwr_dio_sdb);
+
+  -- Primary wishbone crossbar layout
+  constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
+    c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"),  -- WRPC
+    c_WB_SLAVE_NIC => f_sdb_embed_device(c_xwr_nic_sdb , x"00040000"),     -- NIC
+    c_WB_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb , x"00060000"),  -- VIC (IRQ gen)
+    c_WB_SLAVE_TXTSU => f_sdb_embed_device(c_xwr_txtsu_sdb , x"00061000"),   -- TxTSU
+    c_WB_SLAVE_DIO => f_sdb_embed_bridge(c_wr_dio_bridge_sdb, x"00062000")   -- DIO
+     );
+
+  -- WB MUX identifiers
+  constant c_WB_MUX_NUM : integer := 2;
+
+  constant c_WB_MUX_ETHBONE : integer := 0;
+  constant c_WB_MUX_NIC : integer := 1;
+
+  constant c_WB_MUX_ETHBONE_CLASS : std_logic_vector(7 downto 0) := x"80"; -- EP PFilter Class 7
+  constant c_WB_MUX_NIC_CLASS : std_logic_vector(7 downto 0) := x"40"; -- EP PFilter Class 6
+
+  -- Tx TSU constants
+  constant c_TXTSU_NUM : integer := 1;
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- Wishbone buse(s) from masters attached to crossbar
+  signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
+  signal cnx_master_in  : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
+
+  -- Wishbone buse(s) to slaves attached to crossbar
+  signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
+  signal cnx_slave_in  : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
+
+  -- Gennum signals
+  signal gn_wbadr : std_logic_vector(31 downto 0);
+
+  -- clock and reset
+  signal clk_sys_62m5   : std_logic;
+  signal rst_sys_62m5_n : std_logic;
+  signal rst_ref_125m_n : std_logic;
+  signal clk_ref_125m   : std_logic;
+  signal clk_ref_div2   : std_logic;
+  signal clk_ext_10m    : std_logic;
+
+  -- I2C EEPROM
+  signal eeprom_sda_in  : std_logic;
+  signal eeprom_sda_out : std_logic;
+  signal eeprom_scl_in  : std_logic;
+  signal eeprom_scl_out : std_logic;
+
+  -- SFP
+  signal sfp_sda_in  : std_logic;
+  signal sfp_sda_out : std_logic;
+  signal sfp_scl_in  : std_logic;
+  signal sfp_scl_out : std_logic;
+
+  -- OneWire
+  signal onewire_data : std_logic;
+  signal onewire_oe   : std_logic;
+
+  -- LEDs and GPIO
+  signal wrc_abscal_txts_out : std_logic;
+  signal wrc_abscal_rxts_out : std_logic;
+  signal wrc_pps_out : std_logic;
+  signal wrc_pps_csync_out_ext : std_logic;
+  attribute IOB: string;
+  attribute IOB of wrc_pps_out: signal is "TRUE";
+  signal wrc_pps_csync     : std_logic;
+  signal wrc_pps_valid     : std_logic;
+  signal wrc_pps_valid_out_ext : std_logic;
+  signal wrc_pps_led       : std_logic;
+  signal wrc_pps_in        : std_logic;
+  signal svec_led          : std_logic_vector(15 downto 0);
+
+  -- DIO Mezzanine
+  signal dio_in  : std_logic_vector(4 downto 0);
+  signal dio_out : std_logic_vector(4 downto 0);
+
+  -- Timecode output
+  signal tm_time_valid : std_logic;
+  signal tm_seconds    : std_logic_vector(39 downto 0);
+  signal tm_cycles     : std_logic_vector(27 downto 0);
+
+  -- VIC
+  signal vic_irq       : std_logic;
+  signal vic_slave_irq : std_logic_vector(2 downto 0);
+
+  -- TxTSU
+  signal txtsu_timestamps : t_txtsu_timestamp;
+  signal txtsu_ts_ack : std_logic;
+
+ -- WRPC fabric
+  signal wrpc_src_out : t_wrf_source_out;
+  signal wrpc_src_in  : t_wrf_source_in;
+  signal wrpc_snk_out : t_wrf_sink_out;
+  signal wrpc_snk_in  : t_wrf_sink_in;
+
+  -- WB MUX
+  signal mux_src_out : t_wrf_source_out_array(1 downto 0);
+  signal mux_src_in  : t_wrf_source_in_array(1 downto 0);
+  signal mux_snk_out : t_wrf_sink_out_array(1 downto 0);
+  signal mux_snk_in  : t_wrf_sink_in_array(1 downto 0);
+  signal mux_class   : t_wrf_mux_class(1 downto 0);
+
+  -- WB AUX Interface
+  signal aux_master_o : t_wishbone_master_out;
+  signal aux_master_i : t_wishbone_master_in := cc_dummy_master_in;
+  
+  -- Interrupts
+  signal nic_int   : std_logic;
+  signal txtsu_int : std_logic;
+  signal dio_int   : std_logic;
+
+begin  -- architecture top
+
+  -----------------------------------------------------------------------------
+  -- Primary wishbone Crossbar (With GN4124 and Etherbone as Masters)
+  -----------------------------------------------------------------------------
+  GEN_ETHERBONE_AND_NIC_XBAR : if g_etherbone_ext generate
+    cmp_sdb_crossbar : xwb_sdb_crossbar
+      generic map (
+        g_num_masters => c_NUM_WB_MASTERS,
+        g_num_slaves  => c_NUM_WB_SLAVES,
+        g_registered  => TRUE,
+        g_wraparound  => TRUE,
+        g_layout      => c_WB_LAYOUT,
+        g_sdb_addr    => c_SDB_ADDRESS)
+      port map (
+        clk_sys_i => clk_sys_62m5,
+        rst_n_i   => rst_sys_62m5_n,
+        slave_i   => cnx_master_out,
+        slave_o   => cnx_master_in,
+        master_i  => cnx_slave_out,
+        master_o  => cnx_slave_in);
+  end generate GEN_ETHERBONE_AND_NIC_XBAR;
+  
+  -----------------------------------------------------------------------------
+  -- Primary wishbone Crossbar (Only GN4124 as Master)
+  -----------------------------------------------------------------------------
+  GEN_NIC_ALONE_XBAR : if not g_etherbone_ext generate
+    cmp_sdb_crossbar : xwb_sdb_crossbar
+      generic map (
+        g_num_masters => c_NUM_WB_MASTERS-1,
+        g_num_slaves  => c_NUM_WB_SLAVES,
+        g_registered  => TRUE,
+        g_wraparound  => TRUE,
+        g_layout      => c_WB_LAYOUT,
+        g_sdb_addr    => c_SDB_ADDRESS)
+      port map (
+        clk_sys_i => clk_sys_62m5,
+        rst_n_i   => rst_sys_62m5_n,
+        slave_i   => cnx_master_out(c_NUM_WB_MASTERS-2 downto 0),
+        slave_o   => cnx_master_in(c_NUM_WB_MASTERS-2 downto 0),
+        master_i  => cnx_slave_out,
+        master_o  => cnx_slave_in);
+  end generate GEN_NIC_ALONE_XBAR;
+  
+  -----------------------------------------------------------------------------
+  -- GN4124, PCIe bridge core
+  -----------------------------------------------------------------------------
+  cmp_gn4124_core : gn4124_core
+    port map (
+      ---------------------------------------------------------
+      -- Control and status
+      rst_n_a_i => gn_rst_n,
+      status_o  => open,
+
+      ---------------------------------------------------------
+      -- P2L Direction
+      --
+      -- Source Sync DDR related signals
+      p2l_clk_p_i  => gn_p2l_clk_p,
+      p2l_clk_n_i  => gn_p2l_clk_n,
+      p2l_data_i   => gn_p2l_data,
+      p2l_dframe_i => gn_p2l_dframe,
+      p2l_valid_i  => gn_p2l_valid,
+      -- P2L Control
+      p2l_rdy_o    => gn_p2l_rdy,
+      p_wr_req_i   => gn_p_wr_req,
+      p_wr_rdy_o   => gn_p_wr_rdy,
+      rx_error_o   => gn_rx_error,
+      vc_rdy_i     => gn_vc_rdy,
+
+      ---------------------------------------------------------
+      -- L2P Direction
+      --
+      -- Source Sync DDR related signals
+      l2p_clk_p_o  => gn_l2p_clkp,
+      l2p_clk_n_o  => gn_l2p_clkn,
+      l2p_data_o   => gn_l2p_data,
+      l2p_dframe_o => gn_l2p_dframe,
+      l2p_valid_o  => gn_l2p_valid,
+      -- L2P Control
+      l2p_edb_o    => gn_l2p_edb,
+      l2p_rdy_i    => gn_l2p_rdy,
+      l_wr_rdy_i   => gn_l_wr_rdy,
+      p_rd_d_rdy_i => gn_p_rd_d_rdy,
+      tx_error_i   => gn_tx_error,
+
+      ---------------------------------------------------------
+      -- Interrupt interface
+      dma_irq_o => open,
+      irq_p_i   => vic_irq,
+      irq_p_o   => gn_gpio(0),
+
+      ---------------------------------------------------------
+      -- DMA registers wishbone interface (slave classic)
+      dma_reg_clk_i => clk_sys_62m5,
+      dma_reg_adr_i => (others=>'0'),
+      dma_reg_dat_i => (others=>'0'),
+      dma_reg_sel_i => (others=>'0'),
+      dma_reg_stb_i => '0',
+      dma_reg_we_i  => '0',
+      dma_reg_cyc_i => '0',
+
+      ---------------------------------------------------------
+      -- CSR wishbone interface (master pipelined)
+      csr_clk_i   => clk_sys_62m5,
+      csr_adr_o   => gn_wbadr,
+      csr_dat_o   => cnx_master_out(c_WB_MASTER_PCIE).dat,
+      csr_sel_o   => cnx_master_out(c_WB_MASTER_PCIE).sel,
+      csr_stb_o   => cnx_master_out(c_WB_MASTER_PCIE).stb,
+      csr_we_o    => cnx_master_out(c_WB_MASTER_PCIE).we,
+      csr_cyc_o   => cnx_master_out(c_WB_MASTER_PCIE).cyc,
+      csr_dat_i   => cnx_master_in(c_WB_MASTER_PCIE).dat,
+      csr_ack_i   => cnx_master_in(c_WB_MASTER_PCIE).ack,
+      csr_stall_i => cnx_master_in(c_WB_MASTER_PCIE).stall,
+      csr_err_i   => cnx_master_in(c_WB_MASTER_PCIE).err,
+      csr_rty_i   => cnx_master_in(c_WB_MASTER_PCIE).rty,
+
+      ---------------------------------------------------------
+      -- L2P DMA Interface (Pipelined Wishbone master)
+      dma_clk_i   => clk_sys_62m5,
+      dma_dat_i   => (others=>'0'),
+      dma_ack_i   => '1',
+      dma_stall_i => '0',
+      dma_err_i   => '0',
+      dma_rty_i   => '0');
+
+  -- "translating" word addressing of Gennum module into byte addressing
+  cnx_master_out(c_WB_MASTER_PCIE).adr(1 downto 0)   <= (others => '0');
+  cnx_master_out(c_WB_MASTER_PCIE).adr(18 downto 2)  <= gn_wbadr(16 downto 0);
+  cnx_master_out(c_WB_MASTER_PCIE).adr(31 downto 19) <= (others => '0');
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core board package (WB Slave + WB AUX)
+  -----------------------------------------------------------------------------
+  cmp_xwrc_board_spec : xwrc_board_spec
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => TRUE,
+      g_dpram_initf               => g_dpram_initf,
+      g_fabric_iface              => PLAIN,
+      g_aux_sdb                   => c_etherbone_sdb)
+    port map (
+      areset_n_i          => button1_i,
+      areset_edge_n_i     => gn_rst_n,
+      clk_20m_vcxo_i      => clk_20m_vcxo_i,
+      clk_125m_pllref_p_i => clk_125m_pllref_p_i,
+      clk_125m_pllref_n_i => clk_125m_pllref_n_i,
+      clk_125m_gtp_n_i    => clk_125m_gtp_n_i,
+      clk_125m_gtp_p_i    => clk_125m_gtp_p_i,
+      clk_10m_ext_i       => clk_ext_10m,
+      clk_sys_62m5_o      => clk_sys_62m5,
+      clk_ref_125m_o      => clk_ref_125m,
+      rst_sys_62m5_n_o    => rst_sys_62m5_n,
+      rst_ref_125m_n_o    => rst_ref_125m_n,
+
+      plldac_sclk_o       => plldac_sclk_o,
+      plldac_din_o        => plldac_din_o,
+      pll25dac_cs_n_o     => pll25dac_cs_n_o,
+      pll20dac_cs_n_o     => pll20dac_cs_n_o,
+
+      sfp_txp_o           => sfp_txp_o,
+      sfp_txn_o           => sfp_txn_o,
+      sfp_rxp_i           => sfp_rxp_i,
+      sfp_rxn_i           => sfp_rxn_i,
+      sfp_det_i           => sfp_mod_def0_i,
+      sfp_sda_i           => sfp_sda_in,
+      sfp_sda_o           => sfp_sda_out,
+      sfp_scl_i           => sfp_scl_in,
+      sfp_scl_o           => sfp_scl_out,
+      sfp_rate_select_o   => sfp_rate_select_o,
+      sfp_tx_fault_i      => sfp_tx_fault_i,
+      sfp_tx_disable_o    => sfp_tx_disable_o,
+      sfp_los_i           => sfp_los_i,
+
+      eeprom_sda_i        => eeprom_sda_in,
+      eeprom_sda_o        => eeprom_sda_out,
+      eeprom_scl_i        => eeprom_scl_in,
+      eeprom_scl_o        => eeprom_scl_out,
+
+      onewire_i           => onewire_data,
+      onewire_oen_o       => onewire_oe,
+      -- Uart
+      uart_rxd_i          => uart_rxd_i,
+      uart_txd_o          => uart_txd_o,
+      -- SPI Flash
+      flash_sclk_o        => flash_sclk_o,
+      flash_ncs_o         => flash_ncs_o,
+      flash_mosi_o        => flash_mosi_o,
+      flash_miso_i        => flash_miso_i,
+
+      wb_slave_o          => cnx_slave_out(c_WB_SLAVE_WRC),
+      wb_slave_i          => cnx_slave_in(c_WB_SLAVE_WRC),
+
+      aux_master_o => aux_master_o,
+      aux_master_i => aux_master_i,
+      
+      abscal_txts_o       => wrc_abscal_txts_out,
+      abscal_rxts_o       => wrc_abscal_rxts_out,
+
+      timestamps_o => txtsu_timestamps,
+      timestamps_ack_i => txtsu_ts_ack,
+
+      wrf_src_o => wrpc_snk_in,
+      wrf_src_i => wrpc_snk_out,
+      wrf_snk_o => wrpc_src_in,
+      wrf_snk_i => wrpc_src_out,
+
+      pps_ext_i           => wrc_pps_in,
+      pps_p_o             => wrc_pps_out,
+      pps_csync_o         => wrc_pps_csync,
+      pps_valid_o         => wrc_pps_valid,
+      pps_led_o           => wrc_pps_led,
+      led_link_o          => led_link_o,
+      led_act_o           => led_act_o,
+
+      tm_time_valid_o      => tm_time_valid,
+      tm_tai_o             => tm_seconds,
+      tm_cycles_o          => tm_cycles);
+
+  -- Logic to extend pps_csync_o (125 MHz) in order to be detected
+  -- in clk_sys (62.5 MHz) domain.
+  U_Extend_pps_csync : gc_extend_pulse
+  generic map (
+    g_width => 3)
+  port map (
+    clk_i      => clk_ref_125m,
+    rst_n_i    => rst_ref_125m_n,
+    pulse_i    => wrc_pps_csync,
+    extended_o => wrc_pps_csync_out_ext);
+
+  -- Logic to extend pps_valid_o (125 MHz) in order to be detected
+  -- in clk_sys (62.5 MHz) domain.
+  U_Extend_pps_valid : gc_extend_pulse
+  generic map (
+    g_width => 3)
+  port map (
+    clk_i      => clk_ref_125m,
+    rst_n_i    => rst_ref_125m_n,
+    pulse_i    => wrc_pps_valid,
+    extended_o => wrc_pps_valid_out_ext);
+
+  -- Tristates for SFP EEPROM
+  sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
+  sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
+  sfp_scl_in     <= sfp_mod_def1_b;
+  sfp_sda_in     <= sfp_mod_def2_b;
+
+  -- tri-state onewire access
+  onewire_b    <= '0' when (onewire_oe = '1') else 'Z';
+  onewire_data <= onewire_b;
+
+  ------------------------------------------------------------------------------
+  -- Digital I/O FMC Mezzanine connections
+  ------------------------------------------------------------------------------
+  gen_dio_ibufs: for I in 0 to 4 generate
+    U_ibuf: IBUFDS
+      generic map (
+        DIFF_TERM => true)
+      port map (
+        O  => dio_in(i),
+        I  => dio_p_i(i),
+        IB => dio_n_i(i));
+  end generate gen_dio_ibufs;
+
+  gen_dio_obufs : for I in 1 to 4 generate
+    U_obuf : OBUFDS
+      port map (
+        I  => dio_out(i),
+        O  => dio_p_o(i),
+        OB => dio_n_o(i));
+  end generate gen_dio_obufs;
+
+  U_obuf_pps : OBUFDS
+    port map (
+      I  => wrc_pps_out,
+      O  => dio_p_o(0),
+      OB => dio_n_o(0));
+
+  -- EEPROM I2C tri-states
+  dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
+  eeprom_sda_in <= dio_sda_b;
+  dio_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
+  eeprom_scl_in <= dio_scl_b;
+
+  -- Div by 2 reference clock to LEMO connector
+  process(clk_ref_125m)
+  begin
+    if rising_edge(clk_ref_125m) then
+      clk_ref_div2 <= not clk_ref_div2;
+    end if;
+  end process;
+
+  cmp_ibugds_extref: IBUFGDS
+    generic map (
+      DIFF_TERM => true)
+    port map (
+      O  => clk_ext_10m,
+      I  => dio_clk_p_i,
+      IB => dio_clk_n_i);
+
+  wrc_pps_in    <= dio_in(3);
+
+  -------------------------------------------------------------------
+  -- NIC design logic
+  -------------------------------------------------------------------
+
+  -------------------------------------
+  -- VIC
+  -------------------------------------
+  U_VIC : xwb_vic
+    generic map(
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE,
+      g_num_interrupts      => c_NUM_IRQS)
+    port map(
+      clk_sys_i    => clk_sys_62m5,
+      rst_n_i      => rst_sys_62m5_n,
+      slave_i      => cnx_slave_in(c_WB_SLAVE_VIC),
+      slave_o      => cnx_slave_out(c_WB_SLAVE_VIC),
+      irqs_i       => vic_slave_irq,
+      irq_master_o => vic_irq
+      );
+  
+  vic_slave_irq(c_IRQ_TXTSU) <= txtsu_int;
+  vic_slave_irq(c_IRQ_NIC)   <= nic_int;
+  vic_slave_irq(c_IRQ_PPS)   <= wrc_pps_csync_out_ext;
+  vic_slave_irq(c_IRQ_DIO)   <= dio_int;
+
+  -------------------------------------
+  -- DIO
+  -------------------------------------
+  U_DIO_CORE : xwr_dio
+    generic map (
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE)
+
+    port map(
+      clk_sys_i => clk_sys_62m5,
+      clk_ref_i => clk_ref_125m,
+      rst_n_i   => rst_sys_62m5_n,
+      dio_clk_i => clk_ext_10m,
+      dio_pps_i	=> wrc_pps_out,
+      dio_in_i => dio_in,
+      dio_out_o => dio_out,
+      dio_oe_n_o => dio_oe_n_o,
+      dio_term_en_o  => dio_term_en_o,
+      dio_onewire_b  => dio_onewire_b,
+      dio_sdn_n_o    => dio_sdn_n_o,
+      dio_sdn_ck_n_o => dio_sdn_ck_n_o,
+      dio_led_top_o  => dio_led_top_o,
+      dio_led_bot_o  => dio_led_bot_o,
+      dio_ga_o => open,
+      dio_int => dio_int,
+      tm_time_valid_i => tm_time_valid,
+      tm_seconds_i => tm_seconds,
+      tm_cycles_i => tm_cycles,
+      slave_i => cnx_slave_in(c_WB_SLAVE_DIO),
+      slave_o => cnx_slave_out(c_WB_SLAVE_DIO)
+      );
+
+  -------------------------------------
+  -- WRSW TXTSU
+  -------------------------------------
+  U_TXTSU : xwr_tx_tsu
+    generic map(
+      g_num_ports           => c_TXTSU_NUM,
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE)
+    port map(
+      clk_sys_i           => clk_sys_62m5,
+      rst_n_i             => rst_sys_62m5_n,
+      timestamps_i(0)     => txtsu_timestamps,
+      timestamps_ack_o(0) => txtsu_ts_ack,
+      wb_i                => cnx_slave_in(c_WB_SLAVE_TXTSU),
+      wb_o                => cnx_slave_out(c_WB_SLAVE_TXTSU),
+      int_o               => txtsu_int
+      );
+
+  GEN_ETHERBONE_AND_NIC : if g_etherbone_ext generate
+    -------------------------------------
+    -- WB MUX
+    -------------------------------------
+    U_WBP_Mux : xwrf_mux
+      generic map(
+        g_muxed_ports => c_WB_MUX_NUM)
+      port map (
+        clk_sys_i   => clk_sys_62m5,
+        rst_n_i     => rst_sys_62m5_n,
+        ep_src_o    => wrpc_src_out,
+        ep_src_i    => wrpc_src_in,
+        ep_snk_o    => wrpc_snk_out,
+        ep_snk_i    => wrpc_snk_in,
+        mux_src_o   => mux_snk_in,
+        mux_src_i   => mux_snk_out,
+        mux_snk_o   => mux_src_in,
+        mux_snk_i   => mux_src_out,
+        mux_class_i => mux_class);
+
+    mux_class(c_WB_MUX_ETHBONE)  <= c_WB_MUX_ETHBONE_CLASS;
+    mux_class(c_WB_MUX_NIC)  <= c_WB_MUX_NIC_CLASS;
+
+    -------------------------------------
+    -- Etherbone core
+    -------------------------------------
+    Etherbone : eb_ethernet_slave
+      generic map (
+        g_sdb_address => x"0000000000063000")
+      port map (
+        clk_i       => clk_sys_62m5,
+        nRst_i      => rst_sys_62m5_n,
+        src_o       => mux_src_out(c_WB_MUX_ETHBONE),
+        src_i       => mux_src_in(c_WB_MUX_ETHBONE),
+        snk_o       => mux_snk_out(c_WB_MUX_ETHBONE),
+        snk_i       => mux_snk_in(c_WB_MUX_ETHBONE),
+        cfg_slave_o => aux_master_i,
+        cfg_slave_i => aux_master_o,
+        master_o    => cnx_master_out(c_WB_MASTER_ETHBONE),
+        master_i    => cnx_master_in(c_WB_MASTER_ETHBONE)
+        );
+
+    -------------------------------------
+    -- NIC (with Mux)
+    -------------------------------------
+    U_NIC : xwr_nic
+      generic map(
+        g_interface_mode      => PIPELINED,
+        g_address_granularity => BYTE,
+        g_src_cyc_on_stall    => true)
+      port map(
+        clk_sys_i => clk_sys_62m5,
+        rst_n_i   => rst_sys_62m5_n,
+      
+        snk_i => mux_snk_in(c_WB_MUX_NIC),
+        snk_o => mux_snk_out(c_WB_MUX_NIC),
+        src_i => mux_src_in(c_WB_MUX_NIC),
+        src_o => mux_src_out(c_WB_MUX_NIC),
+
+        rtu_dst_port_mask_o => open,
+        rtu_prio_o          => open,
+        rtu_drop_o          => open,
+        rtu_rsp_valid_o     => open,
+        rtu_rsp_ack_i       => '1',
+
+        wb_i => cnx_slave_in(c_WB_SLAVE_NIC),
+        wb_o => cnx_slave_out(c_WB_SLAVE_NIC),
+
+        int_o => nic_int,
+
+        pps_p_i     => wrc_pps_csync_out_ext,
+        pps_valid_i => wrc_pps_valid_out_ext
+        );
+  end generate GEN_ETHERBONE_AND_NIC;
+
+  GEN_NIC_ALONE : if not g_etherbone_ext generate
+    -- Put the WB AUX Interface in an IDLE state
+    aux_master_i <= cc_dummy_master_in;
+  
+    -------------------------------------
+    -- NIC (direct attach)
+    -------------------------------------
+    U_NIC : xwr_nic
+      generic map(
+        g_interface_mode      => PIPELINED,
+        g_address_granularity => BYTE,
+        g_src_cyc_on_stall    => true)
+      port map(
+        clk_sys_i => clk_sys_62m5,
+        rst_n_i   => rst_sys_62m5_n,
+      
+        snk_i => wrpc_snk_in,
+        snk_o => wrpc_snk_out,
+        src_i => wrpc_src_in,
+        src_o => wrpc_src_out,
+
+        rtu_dst_port_mask_o => open,
+        rtu_prio_o          => open,
+        rtu_drop_o          => open,
+        rtu_rsp_valid_o     => open,
+        rtu_rsp_ack_i       => '1',
+
+        wb_i => cnx_slave_in(c_WB_SLAVE_NIC),
+        wb_o => cnx_slave_out(c_WB_SLAVE_NIC),
+
+        int_o => nic_int,
+
+        pps_p_i     => wrc_pps_csync_out_ext,
+        pps_valid_i => wrc_pps_valid_out_ext
+        );
+  end generate GEN_NIC_ALONE;
+
+end architecture top;
--- a/hdl/top/dio-nic/Manifest.py
+++ b/hdl/top/dio-nic/Manifest.py
+files = ["dio_nic_top.vhd", "dio_nic_top.ucf"]
+
+modules = { "local" : [ "../dio-common", 
+                        "../../" ] }
--- a/hdl/top/dio-nic/dio_nic_top.ucf
+++ b/hdl/top/dio-nic/dio_nic_top.ucf
+#bank 0
+NET "clk_20m_vcxo_i" LOC = H12;
+NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
+
+NET "clk_125m_pllref_n_i" LOC = F10;
+NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
+NET "clk_125m_pllref_p_i" LOC = G9;
+NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
+
+NET "clk_125m_gtp_n_i" LOC = D11;
+NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
+NET "clk_125m_gtp_p_i" LOC = C11;
+NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
+
+###########################################################################
+## GN4124 PCIe bridge signals
+###########################################################################
+NET "gn_rst_n"       LOC = N20;
+NET "gn_rst_n"       IOSTANDARD = "LVCMOS18";
+NET "gn_p2l_clk_n"   LOC = M19;
+NET "gn_p2l_clk_n"   IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_clk_p"   LOC = M20;
+NET "gn_p2l_clk_p"   IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_rdy"     LOC = J16;
+NET "gn_p2l_rdy"     IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_dframe"  LOC = J22;
+NET "gn_p2l_dframe"  IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_valid"   LOC = L19;
+NET "gn_p2l_valid"   IOSTANDARD = "SSTL18_I";
+
+NET "gn_p2l_data[0]" LOC = K20;
+NET "gn_p2l_data[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[1]" LOC = H22;
+NET "gn_p2l_data[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[2]" LOC = H21;
+NET "gn_p2l_data[2]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[3]" LOC = L17;
+NET "gn_p2l_data[3]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[4]" LOC = K17;
+NET "gn_p2l_data[4]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[5]" LOC = G22;
+NET "gn_p2l_data[5]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[6]" LOC = G20;
+NET "gn_p2l_data[6]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[7]" LOC = K18;
+NET "gn_p2l_data[7]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[8]" LOC = K19;
+NET "gn_p2l_data[8]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[9]" LOC = H20;
+NET "gn_p2l_data[9]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[10]" LOC = J19;
+NET "gn_p2l_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[11]" LOC = E22;
+NET "gn_p2l_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[12]" LOC = E20;
+NET "gn_p2l_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[13]" LOC = F22;
+NET "gn_p2l_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[14]" LOC = F21;
+NET "gn_p2l_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[15]" LOC = H19;
+NET "gn_p2l_data[15]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_p_wr_req[0]" LOC = M22;
+NET "gn_p_wr_req[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_req[1]" LOC = M21;
+NET "gn_p_wr_req[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[0]" LOC = L15;
+NET "gn_p_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[1]" LOC = K16;
+NET "gn_p_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_rx_error"    LOC = J17;
+NET "gn_rx_error"    IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_clkn"    LOC = K22;
+NET "gn_l2p_clkn"    IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_clkp"    LOC = K21;
+NET "gn_l2p_clkp"    IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_dframe"  LOC = U22;
+NET "gn_l2p_dframe"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_valid"   LOC = T18;
+NET "gn_l2p_valid"   IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_edb"     LOC = U20;
+NET "gn_l2p_edb"     IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_data[0]"  LOC = P16;
+NET "gn_l2p_data[0]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[1]"  LOC = P21;
+NET "gn_l2p_data[1]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[2]"  LOC = P18;
+NET "gn_l2p_data[2]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[3]"  LOC = T20;
+NET "gn_l2p_data[3]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[4]"  LOC = V21;
+NET "gn_l2p_data[4]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[5]"  LOC = V19;
+NET "gn_l2p_data[5]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[6]"  LOC = W22;
+NET "gn_l2p_data[6]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[7]"  LOC = Y22;
+NET "gn_l2p_data[7]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[8]"  LOC = P22;
+NET "gn_l2p_data[8]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[9]"  LOC = R22;
+NET "gn_l2p_data[9]"  IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[10]" LOC = T21;
+NET "gn_l2p_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[11]" LOC = T19;
+NET "gn_l2p_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[12]" LOC = V22;
+NET "gn_l2p_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[13]" LOC = V20;
+NET "gn_l2p_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[14]" LOC = W20;
+NET "gn_l2p_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[15]" LOC = Y21;
+NET "gn_l2p_data[15]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_rdy"       LOC = U19;
+NET "gn_l2p_rdy"       IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[0]"   LOC = R20;
+NET "gn_l_wr_rdy[0]"   IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[1]"   LOC = T22;
+NET "gn_l_wr_rdy[1]"   IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[0]" LOC = N16;
+NET "gn_p_rd_d_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[1]" LOC = P19;
+NET "gn_p_rd_d_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_tx_error"      LOC = M17;
+NET "gn_tx_error"      IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[0]"     LOC = B21;
+NET "gn_vc_rdy[0]"     IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[1]"     LOC = B22;
+NET "gn_vc_rdy[1]"     IOSTANDARD = "SSTL18_I";
+
+NET "gn_gpio[1]" LOC = U16;
+NET "gn_gpio[1]" IOSTANDARD = "LVCMOS25";
+NET "gn_gpio[0]" LOC = AB19;
+NET "gn_gpio[0]" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## SPI interface to DACs
+###########################################################################
+NET "plldac_sclk_o" LOC = A4;
+NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "plldac_din_o" LOC = C4;
+NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
+NET "pll25dac_cs_n_o" LOC = A3;
+NET "pll25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
+NET "pll20dac_cs_n_o" LOC = B3;
+NET "pll20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## SFP I/O for transceiver
+###########################################################################
+#NET "sfp_txp_o" IOSTANDARD = "LVDS_12";
+NET "sfp_txp_o" LOC= B16;
+#NET "sfp_txn_o" IOSTANDARD = "LVDS_12";
+NET "sfp_txn_o" LOC= A16;
+#NET "sfp_rxp_i" IOSTANDARD = "LVDS_12";
+NET "sfp_rxp_i" LOC= D15;
+#NET "sfp_rxn_i" IOSTANDARD = "LVDS_12";
+NET "sfp_rxn_i" LOC= C15;
+NET "sfp_mod_def0_i"    LOC = G15;
+NET "sfp_mod_def0_i"    IOSTANDARD = "LVCMOS25";
+NET "sfp_mod_def1_b"    LOC = C17;
+NET "sfp_mod_def1_b"    IOSTANDARD = "LVCMOS25";
+NET "sfp_mod_def2_b"    LOC = G16;
+NET "sfp_mod_def2_b"    IOSTANDARD = "LVCMOS25";
+NET "sfp_rate_select_o" LOC = H14;
+NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
+NET "sfp_tx_fault_i"    LOC = B18;
+NET "sfp_tx_fault_i"    IOSTANDARD = "LVCMOS25";
+NET "sfp_tx_disable_o"  LOC = F17;
+NET "sfp_tx_disable_o"  IOSTANDARD = "LVCMOS25";
+NET "sfp_los_i"         LOC = D18;
+NET "sfp_los_i"         IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## Onewire interface -> thermometer
+###########################################################################
+NET "onewire_b" LOC = D4;
+NET "onewire_b" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## UART
+###########################################################################
+NET "uart_rxd_i" LOC= A2;
+NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
+NET "uart_txd_o" LOC= B2;
+NET "uart_txd_o" IOSTANDARD=LVCMOS25;
+
+###########################################################################
+## Flash memory SPI interface
+###########################################################################
+NET "flash_ncs_o"  LOC = AA3;
+NET "flash_ncs_o"  IOSTANDARD = "LVCMOS25";
+NET "flash_sclk_o" LOC = Y20;
+NET "flash_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "flash_mosi_o" LOC = AB20;
+NET "flash_mosi_o" IOSTANDARD = "LVCMOS25";
+NET "flash_miso_i" LOC = AA20;
+NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
+
+###########################################################################
+## Miscellanous SPEC pins
+###########################################################################
+NET "led_act_o"  LOC = D5;
+NET "led_act_o"  IOSTANDARD = "LVCMOS25";
+NET "led_link_o" LOC = E5;
+NET "led_link_o" IOSTANDARD = "LVCMOS25";
+NET "button1_i"  LOC = C22;
+NET "button1_i"  IOSTANDARD = "LVCMOS18";
+
+###########################################################################
+##  Pin definitions for FmcDio5chttl
+###########################################################################
+NET "dio_clk_p_i" LOC=L20;
+NET "dio_clk_p_i" IOSTANDARD=LVDS_25;
+NET "dio_clk_n_i" LOC=L22;
+NET "dio_clk_n_i" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[4]" LOC =Y11;
+NET "dio_p_i[4]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[4]" LOC =AB11;
+NET "dio_n_i[4]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[3]" LOC =V7;
+NET "dio_p_i[3]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[3]" LOC =W8;
+NET "dio_n_i[3]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[2]" LOC =W12;
+NET "dio_p_i[2]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[2]" LOC =Y12;
+NET "dio_n_i[2]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[1]" LOC =R11;
+NET "dio_p_i[1]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[1]" LOC =T11;
+NET "dio_n_i[1]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_i[0]" LOC =C19;
+NET "dio_p_i[0]" IOSTANDARD=LVDS_25;
+NET "dio_n_i[0]" LOC =A19;
+NET "dio_n_i[0]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[4]" LOC= T8; 
+NET "dio_n_o[4]" LOC= U8; 
+NET "dio_p_o[4]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[4]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[3]" LOC= U9; 
+NET "dio_n_o[3]" LOC= V9;
+NET "dio_p_o[3]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[3]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[2]" LOC=  R9;
+NET "dio_n_o[2]" LOC=  R8;
+NET "dio_p_o[2]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[2]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[1]" LOC=  Y16;
+NET "dio_n_o[1]" LOC=  W15;
+NET "dio_p_o[1]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[1]" IOSTANDARD=LVDS_25;
+
+NET "dio_p_o[0]" LOC=  W17;
+NET "dio_n_o[0]" LOC=  Y18;
+NET "dio_p_o[0]" IOSTANDARD=LVDS_25;
+NET "dio_n_o[0]" IOSTANDARD=LVDS_25;
+
+NET "dio_oe_n_o[4]" LOC= AA6;
+NET "dio_oe_n_o[3]" LOC= W10;
+NET "dio_oe_n_o[2]" LOC= W11;
+NET "dio_oe_n_o[1]" LOC= Y14;
+NET "dio_oe_n_o[0]" LOC= V17;
+NET "dio_oe_n_o[4]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[3]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[2]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[1]" IOSTANDARD=LVCMOS25;
+NET "dio_oe_n_o[0]" IOSTANDARD=LVCMOS25;
+
+NET "dio_term_en_o[4]" LOC=AB7;
+NET "dio_term_en_o[3]" LOC=Y7;
+NET "dio_term_en_o[2]" LOC=AB6;
+NET "dio_term_en_o[1]" LOC=AB5;
+NET "dio_term_en_o[0]" LOC=W18;
+NET "dio_term_en_o[4]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[3]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[2]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[1]" IOSTANDARD=LVCMOS25;
+NET "dio_term_en_o[0]" IOSTANDARD=LVCMOS25;
+
+NET "dio_led_top_o" LOC= AA12;
+NET "dio_led_top_o" IOSTANDARD=LVCMOS25;
+NET "dio_led_bot_o" LOC= AB12;
+NET "dio_led_bot_o" IOSTANDARD=LVCMOS25;
+
+NET "dio_scl_b" LOC = F7;
+NET "dio_scl_b" IOSTANDARD = "LVCMOS25";
+NET "dio_sda_b" LOC = F8;
+NET "dio_sda_b" IOSTANDARD = "LVCMOS25";
+
+NET "dio_onewire_b" LOC=AB16;
+NET "dio_onewire_b" IOSTANDARD=LVCMOS25;
+
+NET "dio_sdn_n_o" LOC=  V11;
+NET "dio_sdn_n_o" IOSTANDARD=LVCMOS25;
+
+NET "dio_sdn_ck_n_o" LOC=  Y5;
+NET "dio_sdn_ck_n_o" IOSTANDARD=LVCMOS25;
+
+# GN4124
+NET "gn_p2l_clk_p" TNM_NET = "gn_p2l_clkp_grp";
+NET "gn_p2l_clk_n" TNM_NET = "gn_p2l_clkn_grp";
+TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_dio_nic/cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
+NET "gn_rst_n" TIG;
+NET "cmp_dio_nic/cmp_gn4124_core/rst_*" TIG;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
+NET "cmp_dio_nic/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_dio_nic/cmp_gn4124_core/cmp_clk_in/P_clk;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
+NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
+TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
+NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
+TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
+NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
+TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
+NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
+TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
+NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
+TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
+# 10MHz reference clock input
+NET "dio_clk_p_i" TNM_NET = dio_clk_p_i;
+TIMESPEC TS_dio_clk_p_i = PERIOD "dio_clk_p_i" 100 ns HIGH 50%;
+NET "dio_clk_n_i" TNM_NET = dio_clk_n_i;
+TIMESPEC TS_dio_clk_n_i = PERIOD "dio_clk_n_i" 100 ns HIGH 50%;
+
+# Needed only when DMTD samples 125m refclock (clock has to be fed to D input of
+# a flip-flop).
+# However, in case of SPEC we use g_divide_input_by_2 generic in the dmtd_with_deglitcher.
+# This re-generates 62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D
+# input of a flip-flop. This constraint would be needed e.g. for Kintex, where
+# refclock is 62.5MHz and we don't use g_divide_input_by_2.
+#PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE; 
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20
+NET "cmp_dio_nic/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_dio_nic/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
+TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_dio_nic/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
+# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; 
+##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
+
+TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
+
+#INST "cmp_dio_nic/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
--- a/hdl/top/dio-nic/dio_nic_top.vhd
+++ b/hdl/top/dio-nic/dio_nic_top.vhd
+-------------------------------------------------------------------------------
+-- Title      : DIO design with NIC core.
+-- Project    : FMC DIO 5CH TTa
+-------------------------------------------------------------------------------
+-- File       : dio_nic_top.vhd
+-- Author     : Miguel Jimenez-Lopez
+-- Company    : Seven Solutions
+-- Created    : 2019-03-27
+-- Last update: 2019-03-27
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- DIO design with NIC capabilities.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 Seven Solutions
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2019-03-27  1.0      klyone          Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.dio_common_top_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity dio_nic_top is
+  generic (
+    g_dpram_initf : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
+    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
+    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
+    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
+    g_simulation : integer := 0
+  );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- Local oscillators
+    clk_20m_vcxo_i : in std_logic;                -- 20MHz VCXO clock
+
+    clk_125m_pllref_p_i : in std_logic;           -- 125 MHz PLL reference
+    clk_125m_pllref_n_i : in std_logic;
+
+    clk_125m_gtp_n_i : in std_logic;              -- 125 MHz GTP reference
+    clk_125m_gtp_p_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- GN4124 PCIe bridge signals
+    ---------------------------------------------------------------------------
+    -- From GN4124 Local bus
+    gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
+    -- PCIe to Local [Inbound Data] - RX
+    gn_p2l_clk_n  : in  std_logic;       -- Receiver Source Synchronous Clock-
+    gn_p2l_clk_p  : in  std_logic;       -- Receiver Source Synchronous Clock+
+    gn_p2l_rdy    : out std_logic;       -- Rx Buffer Full Flag
+    gn_p2l_dframe : in  std_logic;       -- Receive Frame
+    gn_p2l_valid  : in  std_logic;       -- Receive Data Valid
+    gn_p2l_data   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
+    -- Inbound Buffer Request/Status
+    gn_p_wr_req   : in  std_logic_vector(1 downto 0);  -- PCIe Write Request
+    gn_p_wr_rdy   : out std_logic_vector(1 downto 0);  -- PCIe Write Ready
+    gn_rx_error   : out std_logic;                     -- Receive Error
+    -- Local to Parallel [Outbound Data] - TX
+    gn_l2p_clkn   : out std_logic;       -- Transmitter Source Synchronous Clock-
+    gn_l2p_clkp   : out std_logic;       -- Transmitter Source Synchronous Clock+
+    gn_l2p_dframe : out std_logic;       -- Transmit Data Frame
+    gn_l2p_valid  : out std_logic;       -- Transmit Data Valid
+    gn_l2p_edb    : out std_logic;       -- Packet termination and discard
+    gn_l2p_data   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
+    -- Outbound Buffer Status
+    gn_l2p_rdy    : in std_logic;                     -- Tx Buffer Full Flag
+    gn_l_wr_rdy   : in std_logic_vector(1 downto 0);  -- Local-to-PCIe Write
+    gn_p_rd_d_rdy : in std_logic_vector(1 downto 0);  -- PCIe-to-Local Read Response Data Ready
+    gn_tx_error   : in std_logic;                     -- Transmit Error
+    gn_vc_rdy     : in std_logic_vector(1 downto 0);  -- Channel ready
+    -- General Purpose Interface
+    gn_gpio : inout std_logic_vector(1 downto 0);  -- gn_gpio[0] -> GN4124 GPIO8
+                                                   -- gn_gpio[1] -> GN4124 GPIO9
+    ---------------------------------------------------------------------------
+    -- SPI interface to DACs
+    ---------------------------------------------------------------------------
+
+    plldac_sclk_o     : out std_logic;
+    plldac_din_o      : out std_logic;
+    pll25dac_cs_n_o : out std_logic; --cs1
+    pll20dac_cs_n_o : out std_logic; --cs2
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver
+    ---------------------------------------------------------------------------
+
+    sfp_txp_o         : out   std_logic;
+    sfp_txn_o         : out   std_logic;
+    sfp_rxp_i         : in    std_logic;
+    sfp_rxn_i         : in    std_logic;
+    sfp_mod_def0_i    : in    std_logic;          -- sfp detect
+    sfp_mod_def1_b    : inout std_logic;          -- scl
+    sfp_mod_def2_b    : inout std_logic;          -- sda
+    sfp_rate_select_o : out   std_logic;
+    sfp_tx_fault_i    : in    std_logic;
+    sfp_tx_disable_o  : out   std_logic;
+    sfp_los_i         : in    std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+
+    onewire_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Miscellanous SPEC pins
+    ---------------------------------------------------------------------------
+    -- Red LED next to the SFP: blinking indicates that packets are being
+    -- transferred.
+    led_act_o   : out std_logic;
+    -- Green LED next to the SFP: indicates if the link is up.
+    led_link_o : out std_logic;
+
+    button1_i   : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Digital I/O FMC Pins
+    -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
+    -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
+    ---------------------------------------------------------------------------
+
+    -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
+    -- external reference input.
+    dio_clk_p_i : in std_logic;
+    dio_clk_n_i : in std_logic;
+
+    -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
+    -- the mezzanine front panel.
+    dio_n_i : in std_logic_vector(4 downto 0);
+    dio_p_i : in std_logic_vector(4 downto 0);
+
+    -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
+    -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
+    -- of I/O (N+1) on the front panel of the mezzanine
+    dio_n_o : out std_logic_vector(4 downto 0);
+    dio_p_o : out std_logic_vector(4 downto 0);
+
+    -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
+    -- panel is configured as an output.
+    dio_oe_n_o    : out std_logic_vector(4 downto 0);
+
+    -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
+    -- panel is 50-ohm terminated
+    dio_term_en_o : out std_logic_vector(4 downto 0);
+
+    -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
+    -- blink 1-PPS.
+    dio_led_top_o : out std_logic;
+    dio_led_bot_o : out std_logic;
+
+    -- DIO 1-wire bus
+    dio_onewire_b  : inout std_logic;
+    dio_sdn_n_o    : out   std_logic;
+    dio_sdn_ck_n_o : out   std_logic;
+
+    -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
+    -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
+    dio_scl_b : inout std_logic;
+    dio_sda_b : inout std_logic
+
+  );
+end entity dio_nic_top;
+
+architecture top of dio_nic_top is
+begin
+
+  cmp_dio_nic : dio_common_top
+  generic map (
+    g_dio_mode => DIO_NIC,
+    g_dpram_initf => g_dpram_initf,
+    g_simulation => g_simulation
+  )
+  port map (
+    clk_20m_vcxo_i => clk_20m_vcxo_i,
+    clk_125m_pllref_p_i => clk_125m_pllref_p_i,
+    clk_125m_pllref_n_i => clk_125m_pllref_n_i,
+    clk_125m_gtp_n_i => clk_125m_gtp_n_i,
+    clk_125m_gtp_p_i => clk_125m_gtp_p_i,
+    gn_rst_n => gn_rst_n,
+    gn_p2l_clk_n => gn_p2l_clk_n,
+    gn_p2l_clk_p => gn_p2l_clk_p,
+    gn_p2l_rdy => gn_p2l_rdy,
+    gn_p2l_dframe => gn_p2l_dframe,
+    gn_p2l_valid => gn_p2l_valid,
+    gn_p2l_data => gn_p2l_data,
+    gn_p_wr_req => gn_p_wr_req,
+    gn_p_wr_rdy => gn_p_wr_rdy,
+    gn_rx_error => gn_rx_error,
+    gn_l2p_clkn => gn_l2p_clkn,
+    gn_l2p_clkp => gn_l2p_clkp,
+    gn_l2p_dframe => gn_l2p_dframe,
+    gn_l2p_valid => gn_l2p_valid,
+    gn_l2p_edb => gn_l2p_edb,
+    gn_l2p_data => gn_l2p_data,
+    gn_l2p_rdy => gn_l2p_rdy,
+    gn_l_wr_rdy => gn_l_wr_rdy,
+    gn_p_rd_d_rdy => gn_p_rd_d_rdy,
+    gn_tx_error => gn_tx_error,
+    gn_vc_rdy => gn_vc_rdy,
+    gn_gpio => gn_gpio,
+    plldac_sclk_o => plldac_sclk_o,
+    plldac_din_o => plldac_din_o,
+    pll25dac_cs_n_o => pll25dac_cs_n_o,
+    pll20dac_cs_n_o => pll20dac_cs_n_o,
+    sfp_txp_o => sfp_txp_o,
+    sfp_txn_o => sfp_txn_o,
+    sfp_rxp_i => sfp_rxp_i,
+    sfp_rxn_i => sfp_rxn_i,
+    sfp_mod_def0_i => sfp_mod_def0_i,
+    sfp_mod_def1_b => sfp_mod_def1_b,
+    sfp_mod_def2_b => sfp_mod_def2_b,
+    sfp_rate_select_o => sfp_rate_select_o,
+    sfp_tx_fault_i => sfp_tx_fault_i,
+    sfp_tx_disable_o => sfp_tx_disable_o,
+    sfp_los_i => sfp_los_i,
+    onewire_b => onewire_b,
+    uart_rxd_i => uart_rxd_i,
+    uart_txd_o => uart_txd_o,
+    flash_sclk_o => flash_sclk_o,
+    flash_ncs_o => flash_ncs_o,
+    flash_mosi_o => flash_mosi_o,
+    flash_miso_i => flash_miso_i,
+    led_act_o => led_act_o,
+    led_link_o => led_link_o,
+    button1_i => button1_i,
+    dio_clk_p_i => dio_clk_p_i,
+    dio_clk_n_i => dio_clk_n_i,
+    dio_n_i => dio_n_i,
+    dio_p_i => dio_p_i,
+    dio_n_o => dio_n_o,
+    dio_p_o => dio_p_o,
+    dio_oe_n_o => dio_oe_n_o,
+    dio_term_en_o => dio_term_en_o,
+    dio_led_top_o => dio_led_top_o,
+    dio_led_bot_o => dio_led_bot_o,
+    dio_onewire_b => dio_onewire_b,
+    dio_sdn_n_o => dio_sdn_n_o,
+    dio_sdn_ck_n_o => dio_sdn_ck_n_o,
+    dio_scl_b => dio_scl_b,
+    dio_sda_b => dio_sda_b
+  );
+
+end architecture top;