hdl: Modify wr_dio testbench.

5b128f23 · Miguel Jimenez Lopez · 94739c27 · 5b128f23
Commit 5b128f23 authored Mar 28, 2019 by Miguel Jimenez Lopez
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main.sv hdl/testbench/wr_dio/main.sv +1 -1

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--- a/hdl/testbench/wr_dio/main.sv
+++ b/hdl/testbench/wr_dio/main.sv
@@ -31,7 +31,7 @@ module main;
   //assign  #10 clk_sys_dly  = clk_sys;
   //assign  #10ns  time_valid =1'b1;
  
-   wrsw_dio 
+   wr_dio 
      #(
        .g_interface_mode(PIPELINED),
        .g_address_granularity(WORD))