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FMC DIO 5ch TTL a
Commits
3dd7a56d
Commit
3dd7a56d
authored
Dec 04, 2019
by
Miguel Jimenez Lopez
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hdl: Fix copyright and license issues.
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eea7bfc8
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8 changed files
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152 additions
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16 deletions
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-16
wr_dio.vhd
hdl/modules/wr_dio/wr_dio.vhd
+19
-2
wr_dio_pkg.vhd
hdl/modules/wr_dio/wr_dio_pkg.vhd
+19
-2
xwr_dio.vhd
hdl/modules/wr_dio/xwr_dio.vhd
+19
-2
dio_common_top.vhd
hdl/top/dio-common/dio_common_top.vhd
+19
-2
dio_common_top_pkg.vhd
hdl/top/dio-common/dio_common_top_pkg.vhd
+19
-2
dio_etherbone_top.vhd
hdl/top/dio-etherbone/dio_etherbone_top.vhd
+19
-2
dio_ext_nic_etherbone_top.vhd
hdl/top/dio-ext-nic-etherbone/dio_ext_nic_etherbone_top.vhd
+19
-2
dio_nic_top.vhd
hdl/top/dio-nic/dio_nic_top.vhd
+19
-2
No files found.
hdl/modules/wr_dio/wr_dio.vhd
View file @
3dd7a56d
...
...
@@ -6,14 +6,31 @@
-- Author : Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-07-25
-- Last update: 2019-
08-27
-- Last update: 2019-
12-04
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Simulation file for the xwr_dio.vhd file
--
-------------------------------------------------------------------------------
-- TODO:
-- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
hdl/modules/wr_dio/wr_dio_pkg.vhd
View file @
3dd7a56d
...
...
@@ -6,7 +6,7 @@
-- Author : Javier Díaz
-- Company : Seven Solutions, UGR
-- Created : 2012-07-18
-- Last update: 2019-
08-27
-- Last update: 2019-
12-04
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -14,7 +14,24 @@
-- Standard data bus (SDB) definitions for White Rabbit Network Interface Card (WR NIC=
-- #
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Javier Díaz
-- Copyright (c) 2012 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
hdl/modules/wr_dio/xwr_dio.vhd
View file @
3dd7a56d
...
...
@@ -6,7 +6,7 @@
-- Author : Rafael Rodriguez, Javier Daz
-- Company : Seven Solutions
-- Created : 2012-03-03
-- Last update: 2019-
08-27
-- Last update: 2019-
12-04
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -17,7 +17,24 @@
-- to schedule the generation of a pulse at a given future seconds time, or to generate
-- it immediately.
-------------------------------------------------------------------------------
-- TODO: Include wb adapter
-- Copyright 2019, CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
hdl/top/dio-common/dio_common_top.vhd
View file @
3dd7a56d
...
...
@@ -6,14 +6,31 @@
-- Author : Miguel Jimenez-Lopez
-- Company : Seven Solutions
-- Created : 2019-03-27
-- Last update: 2019-
08-27
-- Last update: 2019-
12-04
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- DIO design with NIC or Etherbone capabilities.
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Seven Solutions
-- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
hdl/top/dio-common/dio_common_top_pkg.vhd
View file @
3dd7a56d
...
...
@@ -6,14 +6,31 @@
-- Author : Miguel Jimenez-Lopez
-- Company : Seven Solutions
-- Created : 2019-03-27
-- Last update: 2019-
08-27
-- Last update: 2019-
12-04
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- DIO common package with NIC or Etherbone capabilities.
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Seven Solutions
-- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
hdl/top/dio-etherbone/dio_etherbone_top.vhd
View file @
3dd7a56d
...
...
@@ -6,14 +6,31 @@
-- Author : Miguel Jimenez-Lopez
-- Company : Seven Solutions
-- Created : 2019-03-27
-- Last update: 2019-
08-27
-- Last update: 2019-
12-04
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- DIO design with Etherbone capabilities.
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Seven Solutions
-- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
hdl/top/dio-ext-nic-etherbone/dio_ext_nic_etherbone_top.vhd
View file @
3dd7a56d
...
...
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk, Rafael Rodriguez, Javier Daz, Miguel Jimenez
-- Company : Elproma, Seven Solutions, UGR
-- Created : 2012-02-08
-- Last update: 2019-
08-28
-- Last update: 2019-
12-04
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -18,7 +18,24 @@
-- to wr-nic-v2.1 design. It remains in the git repository for historical and
-- traceability reasons.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Grzegorz Daniluk, Rafael Rodriguez, Javier Daz
-- Copyright (c) 2012 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
hdl/top/dio-nic/dio_nic_top.vhd
View file @
3dd7a56d
...
...
@@ -6,14 +6,31 @@
-- Author : Miguel Jimenez-Lopez
-- Company : Seven Solutions
-- Created : 2019-03-27
-- Last update: 2019-
08-27
-- Last update: 2019-
12-04
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- DIO design with NIC capabilities.
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Seven Solutions
-- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
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