Skip to content

F
FMC DIO 5ch TTL a
Commit 1da5cbfa authored by Javier Díaz's avatar Javier Díaz Committed by Miguel Jimenez Lopez
Browse files
Options

new register for controlling pulse_length and trigger ready interrupts

parent 6c4814e0
Hide whitespace changes
Inline Side-by-side
Showing with 3993 additions and 1247 deletions
modules/wrsw_dio/Manifest.py
View file @ 1da5cbfa
files = ["wrsw_dio_wb.vhd",
"wrsw_dio.vhd",
"dummy_time.vhd" ]
"wrsw_dio.vhd",
"pulse_gen_pl.vhd",
"immed_pulse_counter.vhd",
"dummy_time.vhd" ]
modules/wrsw_dio/immed_pulse_counter.vhd 0 → 100644
View file @ 1da5cbfa
-------------------------------------------------------------------------------
-- Entity: immed_pulse counter
-- File: immed_pulse counter.vhd
-- Description: a simple synchronous output based on strobe inputs that produces a N-ticks
-- length pulse.
-- Author: Javier Díaz (jdiaz@atc.ugr.es)
-- Date: 9 July 2012
-- Version: 0.01
-- Properties:
-- TBD
-- Todo:
-- TBD
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-- -----------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details. You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it from
-- http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity immed_pulse_counter is
generic (
-- reference clock frequency
pulse_length_width : integer := 28
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic; -- asynchronous system reset
pulse_start_i : in std_logic; -- strobe for pulse generation
pulse_length_i : in std_logic_vector(pulse_length_width-1 downto 0);
pulse_output_o : out std_logic
);
end immed_pulse_counter;
architecture rtl of immed_pulse_counter is
-- Internal registers to hold pulse duration
signal counter : unsigned (pulse_length_width-1 downto 0);
-- Signals for states
type counter_state is (WAIT_ST, COUNTING);
signal state : counter_state;
-- Aux
constant zeros : std_logic_vector(pulse_length_width-1 downto 0) := (others=>'0');
begin -- architecture rtl
state_process : process(clk_i, rst_n_i)
begin
if (rst_n_i='0') then
counter <=(others=>'0');
state <=WAIT_ST;
elsif rising_edge(clk_i) then
case state is
when WAIT_ST =>
if pulse_start_i='1' and pulse_length_i/=zeros then
state <=COUNTING;
counter <=unsigned(pulse_length_i)-1;
else
state<=WAIT_ST;
end if;
when COUNTING =>
if (counter=0) then
state <= WAIT_ST;
else
state <= COUNTING;
counter<=counter-1;
end if;
when others =>
state<=WAIT_ST;
end case;
end if;
end process;
output_process:process(counter, state)
begin
if (rst_n_i='0') then
pulse_output_o <='0';
else
case state is
when WAIT_ST =>
pulse_output_o <='0';
when COUNTING =>
pulse_output_o <='1';
when others =>
pulse_output_o <='0';
end case;
end if;
end process;
end architecture rtl;
modules/wrsw_dio/pulse_gen_pl.vhd 0 → 100644
View file @ 1da5cbfa
-------------------------------------------------------------------------------
-- Entity: pulse_gen_pl
-- File: pulse_gen_pl.vhd
-- Description: a pulse generator which produces a N-ticks length pulse in its
-- output when the time passed to it through a vector equals a
-- pre-programmed time.
-- Author: Javier Díaz (jdiaz@atc.ugr.es)
-- Based on the pulse_gen code of Javier Serrano (Javier.Serrano@cern.ch)
-- Date: 6 July 2012
-- Version: 0.02
-- Properties:
-- 1) After arming the trigger, new trigger values are not possible during for 13 clk_sys
-- ticks (208 ns for a 62,5 MHz clock, trig_ready_o<='0') --> not MESURABLE BY PC-SOFTWARE.
-- 2) Minimum of 7 clk_refs ticks are needed between trigger_time and its activation
-- (trig_valid_p1 = 1)
-- Trigger values can be overwritten when trig_ready_o without generate current assigment output
-- Todo: Substitute ready_for_trig process by a state machine.
-- Factor out synchronizer in a separate reusable block.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-- -----------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details. You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it from
-- http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen_pl is
generic (
-- reference clock frequency
g_ref_clk_rate : integer := 125000000);
port (
clk_ref_i : in std_logic; -- timing reference clock
clk_sys_i : in std_logic; -- data output reference clock
rst_n_i : in std_logic; -- system reset
pulse_o : out std_logic; -- pulse output
-------------------------------------------------------------------------------
-- Timing input (from WRPC), clk_ref_i domain
------------------------------------------------------------------------------
-- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't
-- produce pulses and keep trig_ready_o line permamaently active)
tm_time_valid_i : in std_logic;
-- number of seconds
tm_utc_i : in std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles_i : in std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Time tag output (clk_sys_i domain)
---------------------------------------------------------------------------
-- 1: input is ready to accept next trigger time tag
trig_ready_o : out std_logic;
-- time at which the pulse will be produced + a single-cycle strobe to
-- latch it in
trig_utc_i : in std_logic_vector(39 downto 0);
trig_cycles_i : in std_logic_vector(27 downto 0);
trig_valid_p1_i : in std_logic;
pulse_length_i : in std_logic_vector(27 downto 0)
);
end pulse_gen_pl;
architecture rtl of pulse_gen_pl is
-- Internal registers to hold trigger time and pulse duration
signal trig_utc, trig_utc_ref : std_logic_vector(39 downto 0);
signal trig_cycles, trig_cycles_ref : std_logic_vector(27 downto 0);
signal pulse_length, pulse_length_ref : std_logic_vector(27 downto 0);
-- Signals for the synchronizer
signal trig_valid_sys_d1, trig_valid_sys_d2 : std_logic;
signal rst_from_sync, rst_from_sync_d1 : std_logic;
signal trig_valid_ref : std_logic_vector(2 downto 0);
signal trig_valid_back : std_logic_vector(2 downto 0);
signal trig_valid_ref_p1 : std_logic;
-- Aux
constant zeros : std_logic_vector(27 downto 0) := (others=>'0');
signal counter : unsigned (27 downto 0);
begin -- architecture rtl
-- Get trigger time into internal registers
trig_regs: process (clk_sys_i) is
begin -- process trig_regs
if clk_sys_i'event and clk_sys_i = '1' then
if rst_n_i='0' then
trig_utc <= (others=>'0');
trig_cycles <= (others=>'0');
pulse_length <= (others=>'0');
elsif trig_valid_p1_i='1' then
if trig_cycles_i=zeros then
-- Delay 1 sys_ref tick time trigger to match pulse generation at exact time
-- (otherwise 1 clock cycle delay is presented)
trig_utc <= std_logic_vector(unsigned(trig_utc_i)-to_unsigned(1,trig_utc'length));
trig_cycles <= (others=>'1');
else
trig_utc <= trig_utc_i;
trig_cycles <= std_logic_vector(unsigned(trig_cycles_i)-to_unsigned(1,trig_cycles'length));
end if;
pulse_length <= pulse_length_i;
end if;
end if;
end process trig_regs;
-- Synchronizer to pass UTC register data to the reference clock domain
-- This synchronizer is made with the following four processes
-- First one FF with async reset, still in the clk_sys_i domain
sync_first_ff: process (clk_sys_i, rst_n_i, rst_from_sync)
begin
if rst_n_i='0' or rst_from_sync='1' then
trig_valid_sys_d1 <= '0';
elsif clk_sys_i'event and clk_sys_i='1' then
if trig_valid_p1_i='1' then
trig_valid_sys_d1 <= '1';
end if;
end if;
end process sync_first_ff;
-- OK this is just for the UTC and cycle registers to have time to settle
-- in the pathological case of a very fast ref clock and very long
-- combinational delays in the UTC and cycle registers
delay_sys: process (clk_sys_i)
begin
if clk_sys_i'event and clk_sys_i='1' then
trig_valid_sys_d2 <= trig_valid_sys_d1;
end if;
end process delay_sys;
-- Then three FFs to take the strobe safely into the clk_ref_i domain
sync_ref: process (clk_ref_i)
begin
if clk_ref_i'event and clk_ref_i='1' then
trig_valid_ref <= trig_valid_ref(1 downto 0) & trig_valid_sys_d2;
trig_valid_ref_p1 <= trig_valid_ref(1) and not trig_valid_ref(2);
end if;
end process sync_ref;
-- And then back into the clk_sys_i domain
sync_sys: process (clk_sys_i)
begin
if clk_sys_i'event and clk_sys_i='1' then
trig_valid_back <= trig_valid_back(1 downto 0) & trig_valid_ref(2);
rst_from_sync <= trig_valid_back(2);
rst_from_sync_d1 <= rst_from_sync;
end if;
end process sync_sys;
-- Now get the trig registers into the clk_ref_i domain
trig_regs_ref: process (clk_ref_i)
begin
if clk_ref_i'event and clk_ref_i='1' then
if trig_valid_ref_p1='1' then
trig_utc_ref <= trig_utc;
trig_cycles_ref <= trig_cycles;
pulse_length_ref <= pulse_length;
end if;
end if;
end process trig_regs_ref;
-- Notify we're ready to receive another trigger time write
-- Having the reset set trig_ready_o to '1' is a kludge.
-- A proper state machine would be better.
ready_for_trig: process (rst_n_i, clk_sys_i)
begin
if rst_n_i='0' then
trig_ready_o <= '1';
elsif clk_sys_i'event and clk_sys_i='1' then
if trig_valid_p1_i='1' then
trig_ready_o <= '0';
elsif rst_from_sync_d1='1' and rst_from_sync='0' then
-- falling edge of reset_from_sync
trig_ready_o <= '1';
end if;
end if;
end process ready_for_trig;
-- Produce output
-- Note rst_n_i is used as an async reset because it comes from the
-- clk_sys_i domain. Not the most elegant but it ensures no glitches
-- in the output after startup.
-- This block actually creates a pulse pulse_length ticks when the programmed
-- time matches the current time.
gen_out: process (rst_n_i, clk_ref_i)
begin
if rst_n_i='0' then
pulse_o <= '0';
elsif clk_ref_i'event and clk_ref_i='1' then
if tm_time_valid_i ='0' then
pulse_o <= '0';
elsif tm_utc_i=trig_utc_ref and tm_cycles_i=trig_cycles_ref and pulse_length_ref/=zeros then
pulse_o <= '1';
counter <=unsigned(pulse_length_ref)-1;
elsif counter/=0 then
counter<=counter-1;
else
pulse_o <= '0';
end if;
end if;
end process gen_out;
end architecture rtl;
modules/wrsw_dio/wrsw_dio.vhd
View file @ 1da5cbfa
......@@ -96,7 +96,7 @@ architecture rtl of wrsw_dio is
-- output when the seconds time passed to it through a vector equals a
-- pre-programmed seconds time.
-------------------------------------------------------------------------------
component pulse_gen is
component pulse_gen_pl is
generic (
g_ref_clk_rate : integer := 125000000
);
......@@ -126,7 +126,8 @@ architecture rtl of wrsw_dio is
-- latch it in
trig_utc_i : in std_logic_vector(39 downto 0);
trig_cycles_i : in std_logic_vector(27 downto 0);
trig_valid_p1_i : in std_logic
trig_valid_p1_i : in std_logic;
pulse_length_i : in std_logic_vector(27 downto 0)
);
end component;
......@@ -166,6 +167,23 @@ architecture rtl of wrsw_dio is
);
end component;
component immed_pulse_counter is
generic (
-- reference clock frequency
pulse_length_width : integer := 28
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic; -- asynchronous system reset
pulse_start_i : in std_logic; -- strobe for pulse generation
pulse_length_i : in std_logic_vector(pulse_length_width-1 downto 0);
pulse_output_o : out std_logic
);
end component;
component wrsw_dio_wb is
port (
rst_n_i : in std_logic;
......@@ -181,111 +199,126 @@ architecture rtl of wrsw_dio is
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_asyn_i : in std_logic;
-- FIFO write request
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_0_i : in std_logic;
-- FIFO write request
-- FIFO write request
dio_tsf1_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_1_i : in std_logic;
-- FIFO write request
-- FIFO write request
dio_tsf2_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_2_i : in std_logic;
-- FIFO write request
-- FIFO write request
dio_tsf3_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_3_i : in std_logic;
-- FIFO write request
-- FIFO write request
dio_tsf4_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_4_i : in std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'outmode' in reg: 'FMC-DIO output configuration register. '
dio_out_mode_o : out std_logic_vector(4 downto 0);
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch1_o : out std_logic;
dio_latch_time_ch1_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch2_o : out std_logic;
dio_latch_time_ch2_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch3_o : out std_logic;
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO seconds-based trigger is ready to accept a new trigger generation request'
dio_latch_time_ch4_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO time trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(4 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_4_o : out std_logic
);
irq_trigger_ready_0_i : in std_logic;
irq_trigger_ready_1_i : in std_logic;
irq_trigger_ready_2_i : in std_logic;
irq_trigger_ready_3_i : in std_logic;
irq_trigger_ready_4_i : in std_logic;
-- Port for std_logic_vector field: 'number of ticks field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse length'
dio_prog0_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse length'
dio_prog1_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse length'
dio_prog2_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse length'
dio_prog3_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse length'
dio_prog4_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_pulse_imm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_pulse_imm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_pulse_imm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_pulse_imm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_pulse_imm_4_o : out std_logic
);
end component;
......@@ -308,24 +341,26 @@ architecture rtl of wrsw_dio is
signal sda_pad_in, sda_pad_out, sda_pad_oen : std_logic;
-- Pulse generator trigger registers signals
type t_seconds_array is array (4 downto 0) of std_logic_vector (39 downto 0);
type t_cycles_array is array (4 downto 0) of std_logic_vector (27 downto 0);
type t_seconds_array is array (4 downto 0) of std_logic_vector (39 downto 0);
type t_cycles_array is array (4 downto 0) of std_logic_vector (27 downto 0);
type t_pulselength_array is array (4 downto 0) of std_logic_vector (27 downto 0);
signal trig_seconds : t_seconds_array;
signal trig_cycles : t_cycles_array;
signal trig_valid_p1 : std_logic_vector (4 downto 0);
signal trig_ready : std_logic_vector (4 downto 0);
signal tag_seconds : t_seconds_array;
signal tag_seconds : t_seconds_array;
signal tag_cycles : t_cycles_array;
signal tag_valid_p1 : std_logic_vector (4 downto 0);
signal pulse_length : t_pulselength_array;
-- FIFO signals
signal dio_tsf_wr_req : std_logic_vector (4 downto 0);
signal dio_tsf_wr_full : std_logic_vector (4 downto 0);
signal dio_tsf_wr_empty : std_logic_vector (4 downto 0);
signal dio_tsf_tag_seconds : t_seconds_array;
signal dio_tsf_tag_seconds : t_seconds_array;
signal dio_tsf_tag_cycles : t_cycles_array;
-- Fifos no-empty interrupts
......@@ -353,10 +388,11 @@ architecture rtl of wrsw_dio is
signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
-- DIO related signals
signal dio_monost : std_logic_vector(4 downto 0);
signal dio_prog : std_logic_vector(4 downto 0);
signal dio_puls_inmed : std_logic_vector(4 downto 0);
signal dio_out_mode : std_logic_vector(4 downto 0);
signal dio_pulse : std_logic_vector(4 downto 0);
signal dio_pulse_prog : std_logic_vector(4 downto 0);
signal dio_pulse_immed : std_logic_vector(4 downto 0);
signal dio_pulse_immed_stb : std_logic_vector(4 downto 0);
signal dio_out_mode : std_logic_vector(4 downto 0);
-------------------------------------------------------------------------------
-- rtl
......@@ -376,13 +412,13 @@ begin
-- GEN AND STAMPER
------------------------------------------------------------------------------
gen_pulse_modules : for i in 0 to 4 generate
U_pulse_gen : pulse_gen
U_pulse_gen : pulse_gen_pl
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_o => dio_prog(i),
pulse_o => dio_pulse_prog(i),
-- DEBUG
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_utc,--tm_utc_i,
......@@ -395,7 +431,9 @@ begin
trig_utc_i => trig_seconds(i),
trig_cycles_i => trig_cycles(i),
trig_valid_p1_i => trig_valid_p1(i));
trig_valid_p1_i => trig_valid_p1(i),
pulse_length_i => pulse_length(i)
);
U_pulse_stamper : pulse_stamper
......@@ -512,11 +550,24 @@ begin
master_o => cbar_master_out
);
immediate_output_with_pulse_length: for i in 0 to 4 generate
immediate_output_component: immed_pulse_counter
generic map (
pulse_length_width => 28
)
port map(
clk_i => clk_ref_i,
rst_n_i => rst_n_i,
pulse_start_i => dio_pulse_immed_stb(i),
pulse_length_i => pulse_length(i),
pulse_output_o => dio_pulse_immed(i)
);
end generate immediate_output_with_pulse_length;
gen_pio_assignment: for i in 0 to 4 generate
gpio_in(4*i) <= dio_in_i(i);
dio_monost(i) <= '1' when dio_puls_inmed(i) = '1' else dio_prog(i);
dio_out_o(i) <= dio_monost(i) when dio_out_mode(i) ='1' else gpio_out(4*i);
dio_pulse(i) <= '1' when dio_pulse_immed(i) = '1' else dio_pulse_prog(i);
dio_out_o(i) <= dio_pulse(i) when dio_out_mode(i) ='1' else gpio_out(4*i);
dio_oe_n_o(i) <= gpio_out(4*i+1);
dio_term_en_o(i) <= gpio_out(4*i+2);
end generate gen_pio_assignment;
......@@ -616,12 +667,24 @@ begin
dio_latch_time_ch4_o => trig_valid_p1(4),
dio_trig_rdy_i => trig_ready,
dio_puls_inmed_pul_inm_0_o => dio_puls_inmed(0),
dio_puls_inmed_pul_inm_1_o => dio_puls_inmed(1),
dio_puls_inmed_pul_inm_2_o => dio_puls_inmed(2),
dio_puls_inmed_pul_inm_3_o => dio_puls_inmed(3),
dio_puls_inmed_pul_inm_4_o => dio_puls_inmed(4)
irq_trigger_ready_0_i => trig_ready(0),
irq_trigger_ready_1_i => trig_ready(1),
irq_trigger_ready_2_i => trig_ready(2),
irq_trigger_ready_3_i => trig_ready(3),
irq_trigger_ready_4_i => trig_ready(4),
dio_prog0_pulse_length_o=> pulse_length(0),
dio_prog1_pulse_length_o=> pulse_length(1),
dio_prog2_pulse_length_o=> pulse_length(2),
dio_prog3_pulse_length_o=> pulse_length(3),
dio_prog4_pulse_length_o=> pulse_length(4),
dio_pulse_imm_0_o => dio_pulse_immed_stb(0),
dio_pulse_imm_1_o => dio_pulse_immed_stb(1),
dio_pulse_imm_2_o => dio_pulse_immed_stb(2),
dio_pulse_imm_3_o => dio_pulse_immed_stb(3),
dio_pulse_imm_4_o => dio_pulse_immed_stb(4)
);
-- seconds timestamped FIFO-no-empty interrupts
......@@ -655,7 +718,7 @@ begin
-- TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0);
-- TRIG1(0) <= cbar_master_in(3).int;
-- TRIG2 <= tm_utc(31 downto 0);
-- TRIG3(2 downto 0) <= dio_in_i(0) & dio_out(0) & dio_puls_inmed(0);
-- TRIG3(2 downto 0) <= dio_in_i(0) & dio_out(0) & dio_pulse_immed(0);
--TRIG3(4 downto 0) <= dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
......
modules/wrsw_dio/wrsw_dio.wb
View file @ 1da5cbfa
......@@ -6,9 +6,9 @@ peripheral {
hdl_entity="wrsw_dio_wb";
---------------------------------------
-- FIFOS FOR INPUT EVENT TIME STAMPING
---------------------------------------
----------------------------------------------------
-- FIFOS & INTERRUPTS FOR INPUT EVENT TIME STAMPING
----------------------------------------------------
-- CHANNEL 0 INPUT FIFO
......@@ -499,11 +499,14 @@ peripheral {
};
};
-----------------------------------------
-- OUTPUT CONFIGURATION/CONTROL REGISTERS
-----------------------------------------
-- Monostable/Programmable output or GPIO selection
-- Programmable output or GPIO selection
reg {
name = "FMC-DIO output configuration register. ";
description = "It allows to choose a Monostable/programmable output or a standard GPIO output.";
description = "It allows to choose a programmable output or a standard GPIO output.";
prefix = "out";
field {
......@@ -557,7 +560,7 @@ peripheral {
-- seconds trigger ready value. Readable-writable the bus, writable from the device.
reg {
name = "FMC-DIO seconds-based trigger is ready to accept a new trigger generation request";
name = "FMC-DIO time trigger is ready to accept a new trigger generation request";
description = "ready state, waiting new trigger commands for dio output.";
prefix = "trig";
......@@ -572,45 +575,167 @@ peripheral {
};
};
-- DIO CHANNEL 0 trigger ready interrupt
irq {
name = "Channel 0 trigger ready interrupt";
description = "Interrupt active when time-programmable output channels accept new time trigger command.";
prefix = "trigger_ready_0";
trigger = LEVEL_1;
};
-- DIO CHANNEL 1 trigger ready interrupt
irq {
name = "Channel 1 trigger ready interrupt";
description = "Interrupt active when time-programmable output channels accept new time trigger command.";
prefix = "trigger_ready_1";
trigger = LEVEL_1;
};
-- DIO CHANNEL 2 trigger ready interrupt
irq {
name = "Channel 2 trigger ready interrupt";
description = "Interrupt active when time-programmable output channels accept new time trigger command.";
prefix = "trigger_ready_2";
trigger = LEVEL_1;
};
-- DIO CHANNEL 3 trigger ready interrupt
irq {
name = "Channel 3 trigger ready interrupt";
description = "Interrupt active when time-programmable output channels accept new time trigger command.";
prefix = "trigger_ready_3";
trigger = LEVEL_1;
};
-- DIO CHANNEL 4 trigger ready interrupt
irq {
name = "Channel 4 trigger ready interrupt";
description = "Interrupt active when time-programmable output channels accept new time trigger command.";
prefix = "trigger_ready_4";
trigger = LEVEL_1;
};
-- DIO CHANNEL 0: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 0 Programmable/immediate output pulse length";
description = "Number of clk_ref clock ticks that output will be active";
prefix = "prog0_pulse";
field {
name = "number of ticks field for channel 0";
description = "ticks number";
prefix = "length";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 1: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 1 Programmable/immediate output pulse length";
description = "Number of clk_ref clock ticks that output will be active";
prefix = "prog1_pulse";
field {
name = "number of ticks field for channel 1";
description = "ticks number";
prefix = "length";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 2: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 2 Programmable/immediate output pulse length";
description = "Number of clk_ref clock ticks that output will be active";
prefix = "prog2_pulse";
field {
name = "number of ticks field for channel 2";
description = "ticks number";
prefix = "length";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 3: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 3 Programmable/immediate output pulse length";
description = "Number of clk_ref clock ticks that output will be active";
prefix = "prog3_pulse";
field {
name = "number of ticks field for channel 3";
description = "ticks number";
prefix = "length";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 4: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 4 Programmable/immediate output pulse length";
description = "Number of clk_ref clock ticks that output will be active";
prefix = "prog4_pulse";
field {
name = "number of ticks field for channel 4";
description = "ticks number";
prefix = "length";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-----------------------------------------
-- IMMEDIATE OUTPUT REGISTERS
-----------------------------------------
-- Pulse generator.
reg {
name = "Pulse generate immediately";
description = "It is used to generate a pulse immediately";
prefix = "puls_inmed";
prefix = "pulse";
field {
name = "pulse_gen_now_0";
description = "It generates a pulse";
prefix = "pul_inm_0";
prefix = "imm_0";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_1";
description = "It generates a pulse";
prefix = "pul_inm_1";
prefix = "imm_1";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_2";
description = "It generates a pulse";
prefix = "pul_inm_2";
prefix = "imm_2";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_3";
description = "It generates a pulse";
prefix = "pul_inm_3";
prefix = "imm_3";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_4";
description = "It generates a pulse";
prefix = "pul_inm_4";
prefix = "imm_4";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
......
modules/wrsw_dio/wrsw_dio_wb.htm
View file @ 1da5cbfa
This source diff could not be displayed because it is too large. You can view the blob instead.
modules/wrsw_dio/wrsw_dio_wb.vhd
View file @ 1da5cbfa
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrsw_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_dio.wb
-- Created : Fri Jun 29 10:14:46 2012
-- Created : Mon Jul 9 16:40:54 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dio.wb
......@@ -122,18 +122,33 @@ entity wrsw_dio_wb is
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO seconds-based trigger is ready to accept a new trigger generation request'
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO time trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(4 downto 0);
irq_trigger_ready_0_i : in std_logic;
irq_trigger_ready_1_i : in std_logic;
irq_trigger_ready_2_i : in std_logic;
irq_trigger_ready_3_i : in std_logic;
irq_trigger_ready_4_i : in std_logic;
-- Port for std_logic_vector field: 'number of ticks field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse length'
dio_prog0_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse length'
dio_prog1_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse length'
dio_prog2_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse length'
dio_prog3_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse length'
dio_prog4_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_0_o : out std_logic;
dio_pulse_imm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_1_o : out std_logic;
dio_pulse_imm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_2_o : out std_logic;
dio_pulse_imm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_3_o : out std_logic;
dio_pulse_imm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_4_o : out std_logic
dio_pulse_imm_4_o : out std_logic
);
end wrsw_dio_wb;
......@@ -190,39 +205,44 @@ signal dio_latch_time_ch3_dly0 : std_logic ;
signal dio_latch_time_ch3_int : std_logic ;
signal dio_latch_time_ch4_dly0 : std_logic ;
signal dio_latch_time_ch4_int : std_logic ;
signal dio_puls_inmed_pul_inm_0_int : std_logic ;
signal dio_puls_inmed_pul_inm_0_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_1_int : std_logic ;
signal dio_puls_inmed_pul_inm_1_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_1_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_1_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_1_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_2_int : std_logic ;
signal dio_puls_inmed_pul_inm_2_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_2_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_2_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_2_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_3_int : std_logic ;
signal dio_puls_inmed_pul_inm_3_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_3_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_3_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_3_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_4_int : std_logic ;
signal dio_puls_inmed_pul_inm_4_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_4_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_4_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_4_sync2 : std_logic ;
signal eic_idr_int : std_logic_vector(4 downto 0);
signal dio_prog0_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog1_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog2_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog3_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog4_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_pulse_imm_0_int : std_logic ;
signal dio_pulse_imm_0_int_delay : std_logic ;
signal dio_pulse_imm_0_sync0 : std_logic ;
signal dio_pulse_imm_0_sync1 : std_logic ;
signal dio_pulse_imm_0_sync2 : std_logic ;
signal dio_pulse_imm_1_int : std_logic ;
signal dio_pulse_imm_1_int_delay : std_logic ;
signal dio_pulse_imm_1_sync0 : std_logic ;
signal dio_pulse_imm_1_sync1 : std_logic ;
signal dio_pulse_imm_1_sync2 : std_logic ;
signal dio_pulse_imm_2_int : std_logic ;
signal dio_pulse_imm_2_int_delay : std_logic ;
signal dio_pulse_imm_2_sync0 : std_logic ;
signal dio_pulse_imm_2_sync1 : std_logic ;
signal dio_pulse_imm_2_sync2 : std_logic ;
signal dio_pulse_imm_3_int : std_logic ;
signal dio_pulse_imm_3_int_delay : std_logic ;
signal dio_pulse_imm_3_sync0 : std_logic ;
signal dio_pulse_imm_3_sync1 : std_logic ;
signal dio_pulse_imm_3_sync2 : std_logic ;
signal dio_pulse_imm_4_int : std_logic ;
signal dio_pulse_imm_4_int_delay : std_logic ;
signal dio_pulse_imm_4_sync0 : std_logic ;
signal dio_pulse_imm_4_sync1 : std_logic ;
signal dio_pulse_imm_4_sync2 : std_logic ;
signal eic_idr_int : std_logic_vector(9 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(4 downto 0);
signal eic_ier_int : std_logic_vector(9 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(4 downto 0);
signal eic_isr_clear_int : std_logic_vector(4 downto 0);
signal eic_isr_status_int : std_logic_vector(4 downto 0);
signal eic_irq_ack_int : std_logic_vector(4 downto 0);
signal eic_imr_int : std_logic_vector(9 downto 0);
signal eic_isr_clear_int : std_logic_vector(9 downto 0);
signal eic_isr_status_int : std_logic_vector(9 downto 0);
signal eic_irq_ack_int : std_logic_vector(9 downto 0);
signal eic_isr_write_int : std_logic ;
signal dio_tsf0_full_int : std_logic ;
signal dio_tsf0_empty_int : std_logic ;
......@@ -239,7 +259,7 @@ signal dio_tsf3_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf4_full_int : std_logic ;
signal dio_tsf4_empty_int : std_logic ;
signal dio_tsf4_usedw_int : std_logic_vector(7 downto 0);
signal irq_inputs_vector_int : std_logic_vector(4 downto 0);
signal irq_inputs_vector_int : std_logic_vector(9 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -288,16 +308,21 @@ begin
dio_latch_time_ch2_int <= '0';
dio_latch_time_ch3_int <= '0';
dio_latch_time_ch4_int <= '0';
dio_puls_inmed_pul_inm_0_int <= '0';
dio_puls_inmed_pul_inm_0_int_delay <= '0';
dio_puls_inmed_pul_inm_1_int <= '0';
dio_puls_inmed_pul_inm_1_int_delay <= '0';
dio_puls_inmed_pul_inm_2_int <= '0';
dio_puls_inmed_pul_inm_2_int_delay <= '0';
dio_puls_inmed_pul_inm_3_int <= '0';
dio_puls_inmed_pul_inm_3_int_delay <= '0';
dio_puls_inmed_pul_inm_4_int <= '0';
dio_puls_inmed_pul_inm_4_int_delay <= '0';
dio_prog0_pulse_length_int <= "0000000000000000000000000000";
dio_prog1_pulse_length_int <= "0000000000000000000000000000";
dio_prog2_pulse_length_int <= "0000000000000000000000000000";
dio_prog3_pulse_length_int <= "0000000000000000000000000000";
dio_prog4_pulse_length_int <= "0000000000000000000000000000";
dio_pulse_imm_0_int <= '0';
dio_pulse_imm_0_int_delay <= '0';
dio_pulse_imm_1_int <= '0';
dio_pulse_imm_1_int_delay <= '0';
dio_pulse_imm_2_int <= '0';
dio_pulse_imm_2_int_delay <= '0';
dio_pulse_imm_3_int <= '0';
dio_pulse_imm_3_int_delay <= '0';
dio_pulse_imm_4_int <= '0';
dio_pulse_imm_4_int_delay <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -322,16 +347,16 @@ begin
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
dio_puls_inmed_pul_inm_0_int <= dio_puls_inmed_pul_inm_0_int_delay;
dio_puls_inmed_pul_inm_0_int_delay <= '0';
dio_puls_inmed_pul_inm_1_int <= dio_puls_inmed_pul_inm_1_int_delay;
dio_puls_inmed_pul_inm_1_int_delay <= '0';
dio_puls_inmed_pul_inm_2_int <= dio_puls_inmed_pul_inm_2_int_delay;
dio_puls_inmed_pul_inm_2_int_delay <= '0';
dio_puls_inmed_pul_inm_3_int <= dio_puls_inmed_pul_inm_3_int_delay;
dio_puls_inmed_pul_inm_3_int_delay <= '0';
dio_puls_inmed_pul_inm_4_int <= dio_puls_inmed_pul_inm_4_int_delay;
dio_puls_inmed_pul_inm_4_int_delay <= '0';
dio_pulse_imm_0_int <= dio_pulse_imm_0_int_delay;
dio_pulse_imm_0_int_delay <= '0';
dio_pulse_imm_1_int <= dio_pulse_imm_1_int_delay;
dio_pulse_imm_1_int_delay <= '0';
dio_pulse_imm_2_int <= dio_pulse_imm_2_int_delay;
dio_pulse_imm_2_int_delay <= '0';
dio_pulse_imm_3_int <= dio_pulse_imm_3_int_delay;
dio_pulse_imm_3_int_delay <= '0';
dio_pulse_imm_4_int <= dio_pulse_imm_4_int_delay;
dio_pulse_imm_4_int_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -697,16 +722,71 @@ begin
ack_in_progress <= '1';
when "010010" =>
if (wb_we_i = '1') then
dio_puls_inmed_pul_inm_0_int <= wrdata_reg(0);
dio_puls_inmed_pul_inm_0_int_delay <= wrdata_reg(0);
dio_puls_inmed_pul_inm_1_int <= wrdata_reg(1);
dio_puls_inmed_pul_inm_1_int_delay <= wrdata_reg(1);
dio_puls_inmed_pul_inm_2_int <= wrdata_reg(2);
dio_puls_inmed_pul_inm_2_int_delay <= wrdata_reg(2);
dio_puls_inmed_pul_inm_3_int <= wrdata_reg(3);
dio_puls_inmed_pul_inm_3_int_delay <= wrdata_reg(3);
dio_puls_inmed_pul_inm_4_int <= wrdata_reg(4);
dio_puls_inmed_pul_inm_4_int_delay <= wrdata_reg(4);
dio_prog0_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog0_pulse_length_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010011" =>
if (wb_we_i = '1') then
dio_prog1_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog1_pulse_length_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010100" =>
if (wb_we_i = '1') then
dio_prog2_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog2_pulse_length_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
if (wb_we_i = '1') then
dio_prog3_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog3_pulse_length_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
if (wb_we_i = '1') then
dio_prog4_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog4_pulse_length_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
if (wb_we_i = '1') then
dio_pulse_imm_0_int <= wrdata_reg(0);
dio_pulse_imm_0_int_delay <= wrdata_reg(0);
dio_pulse_imm_1_int <= wrdata_reg(1);
dio_pulse_imm_1_int_delay <= wrdata_reg(1);
dio_pulse_imm_2_int <= wrdata_reg(2);
dio_pulse_imm_2_int_delay <= wrdata_reg(2);
dio_pulse_imm_3_int <= wrdata_reg(3);
dio_pulse_imm_3_int_delay <= wrdata_reg(3);
dio_pulse_imm_4_int <= wrdata_reg(4);
dio_pulse_imm_4_int_delay <= wrdata_reg(4);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
......@@ -826,12 +906,7 @@ begin
when "011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= eic_imr_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(9 downto 0) <= eic_imr_int(9 downto 0);
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
......@@ -860,12 +935,7 @@ begin
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(4 downto 0) <= eic_isr_status_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(9 downto 0) <= eic_isr_status_int(9 downto 0);
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
......@@ -1526,19 +1596,29 @@ begin
-- trig_rdy field
-- number of ticks field for channel 0
dio_prog0_pulse_length_o <= dio_prog0_pulse_length_int;
-- number of ticks field for channel 1
dio_prog1_pulse_length_o <= dio_prog1_pulse_length_int;
-- number of ticks field for channel 2
dio_prog2_pulse_length_o <= dio_prog2_pulse_length_int;
-- number of ticks field for channel 3
dio_prog3_pulse_length_o <= dio_prog3_pulse_length_int;
-- number of ticks field for channel 4
dio_prog4_pulse_length_o <= dio_prog4_pulse_length_int;
-- pulse_gen_now_0
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_0_o <= '0';
dio_puls_inmed_pul_inm_0_sync0 <= '0';
dio_puls_inmed_pul_inm_0_sync1 <= '0';
dio_puls_inmed_pul_inm_0_sync2 <= '0';
dio_pulse_imm_0_o <= '0';
dio_pulse_imm_0_sync0 <= '0';
dio_pulse_imm_0_sync1 <= '0';
dio_pulse_imm_0_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_0_sync0 <= dio_puls_inmed_pul_inm_0_int;
dio_puls_inmed_pul_inm_0_sync1 <= dio_puls_inmed_pul_inm_0_sync0;
dio_puls_inmed_pul_inm_0_sync2 <= dio_puls_inmed_pul_inm_0_sync1;
dio_puls_inmed_pul_inm_0_o <= dio_puls_inmed_pul_inm_0_sync2 and (not dio_puls_inmed_pul_inm_0_sync1);
dio_pulse_imm_0_sync0 <= dio_pulse_imm_0_int;
dio_pulse_imm_0_sync1 <= dio_pulse_imm_0_sync0;
dio_pulse_imm_0_sync2 <= dio_pulse_imm_0_sync1;
dio_pulse_imm_0_o <= dio_pulse_imm_0_sync2 and (not dio_pulse_imm_0_sync1);
end if;
end process;
......@@ -1547,15 +1627,15 @@ begin
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_1_o <= '0';
dio_puls_inmed_pul_inm_1_sync0 <= '0';
dio_puls_inmed_pul_inm_1_sync1 <= '0';
dio_puls_inmed_pul_inm_1_sync2 <= '0';
dio_pulse_imm_1_o <= '0';
dio_pulse_imm_1_sync0 <= '0';
dio_pulse_imm_1_sync1 <= '0';
dio_pulse_imm_1_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_1_sync0 <= dio_puls_inmed_pul_inm_1_int;
dio_puls_inmed_pul_inm_1_sync1 <= dio_puls_inmed_pul_inm_1_sync0;
dio_puls_inmed_pul_inm_1_sync2 <= dio_puls_inmed_pul_inm_1_sync1;
dio_puls_inmed_pul_inm_1_o <= dio_puls_inmed_pul_inm_1_sync2 and (not dio_puls_inmed_pul_inm_1_sync1);
dio_pulse_imm_1_sync0 <= dio_pulse_imm_1_int;
dio_pulse_imm_1_sync1 <= dio_pulse_imm_1_sync0;
dio_pulse_imm_1_sync2 <= dio_pulse_imm_1_sync1;
dio_pulse_imm_1_o <= dio_pulse_imm_1_sync2 and (not dio_pulse_imm_1_sync1);
end if;
end process;
......@@ -1564,15 +1644,15 @@ begin
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_2_o <= '0';
dio_puls_inmed_pul_inm_2_sync0 <= '0';
dio_puls_inmed_pul_inm_2_sync1 <= '0';
dio_puls_inmed_pul_inm_2_sync2 <= '0';
dio_pulse_imm_2_o <= '0';
dio_pulse_imm_2_sync0 <= '0';
dio_pulse_imm_2_sync1 <= '0';
dio_pulse_imm_2_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_2_sync0 <= dio_puls_inmed_pul_inm_2_int;
dio_puls_inmed_pul_inm_2_sync1 <= dio_puls_inmed_pul_inm_2_sync0;
dio_puls_inmed_pul_inm_2_sync2 <= dio_puls_inmed_pul_inm_2_sync1;
dio_puls_inmed_pul_inm_2_o <= dio_puls_inmed_pul_inm_2_sync2 and (not dio_puls_inmed_pul_inm_2_sync1);
dio_pulse_imm_2_sync0 <= dio_pulse_imm_2_int;
dio_pulse_imm_2_sync1 <= dio_pulse_imm_2_sync0;
dio_pulse_imm_2_sync2 <= dio_pulse_imm_2_sync1;
dio_pulse_imm_2_o <= dio_pulse_imm_2_sync2 and (not dio_pulse_imm_2_sync1);
end if;
end process;
......@@ -1581,15 +1661,15 @@ begin
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_3_o <= '0';
dio_puls_inmed_pul_inm_3_sync0 <= '0';
dio_puls_inmed_pul_inm_3_sync1 <= '0';
dio_puls_inmed_pul_inm_3_sync2 <= '0';
dio_pulse_imm_3_o <= '0';
dio_pulse_imm_3_sync0 <= '0';
dio_pulse_imm_3_sync1 <= '0';
dio_pulse_imm_3_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_3_sync0 <= dio_puls_inmed_pul_inm_3_int;
dio_puls_inmed_pul_inm_3_sync1 <= dio_puls_inmed_pul_inm_3_sync0;
dio_puls_inmed_pul_inm_3_sync2 <= dio_puls_inmed_pul_inm_3_sync1;
dio_puls_inmed_pul_inm_3_o <= dio_puls_inmed_pul_inm_3_sync2 and (not dio_puls_inmed_pul_inm_3_sync1);
dio_pulse_imm_3_sync0 <= dio_pulse_imm_3_int;
dio_pulse_imm_3_sync1 <= dio_pulse_imm_3_sync0;
dio_pulse_imm_3_sync2 <= dio_pulse_imm_3_sync1;
dio_pulse_imm_3_o <= dio_pulse_imm_3_sync2 and (not dio_pulse_imm_3_sync1);
end if;
end process;
......@@ -1598,39 +1678,39 @@ begin
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_4_o <= '0';
dio_puls_inmed_pul_inm_4_sync0 <= '0';
dio_puls_inmed_pul_inm_4_sync1 <= '0';
dio_puls_inmed_pul_inm_4_sync2 <= '0';
dio_pulse_imm_4_o <= '0';
dio_pulse_imm_4_sync0 <= '0';
dio_pulse_imm_4_sync1 <= '0';
dio_pulse_imm_4_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_4_sync0 <= dio_puls_inmed_pul_inm_4_int;
dio_puls_inmed_pul_inm_4_sync1 <= dio_puls_inmed_pul_inm_4_sync0;
dio_puls_inmed_pul_inm_4_sync2 <= dio_puls_inmed_pul_inm_4_sync1;
dio_puls_inmed_pul_inm_4_o <= dio_puls_inmed_pul_inm_4_sync2 and (not dio_puls_inmed_pul_inm_4_sync1);
dio_pulse_imm_4_sync0 <= dio_pulse_imm_4_int;
dio_pulse_imm_4_sync1 <= dio_pulse_imm_4_sync0;
dio_pulse_imm_4_sync2 <= dio_pulse_imm_4_sync1;
dio_pulse_imm_4_o <= dio_pulse_imm_4_sync2 and (not dio_pulse_imm_4_sync1);
end if;
end process;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(4 downto 0) <= wrdata_reg(4 downto 0);
eic_idr_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(4 downto 0) <= wrdata_reg(4 downto 0);
eic_ier_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(4 downto 0) <= wrdata_reg(4 downto 0);
eic_isr_clear_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 5,
g_num_interrupts => 10,
g_irq00_mode => 3,
g_irq01_mode => 3,
g_irq02_mode => 3,
g_irq03_mode => 3,
g_irq04_mode => 3,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq05_mode => 3,
g_irq06_mode => 3,
g_irq07_mode => 3,
g_irq08_mode => 3,
g_irq09_mode => 3,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
......@@ -1675,6 +1755,11 @@ begin
irq_inputs_vector_int(2) <= irq_nempty_2_i;
irq_inputs_vector_int(3) <= irq_nempty_3_i;
irq_inputs_vector_int(4) <= irq_nempty_4_i;
irq_inputs_vector_int(5) <= irq_trigger_ready_0_i;
irq_inputs_vector_int(6) <= irq_trigger_ready_1_i;
irq_inputs_vector_int(7) <= irq_trigger_ready_2_i;
irq_inputs_vector_int(8) <= irq_trigger_ready_3_i;
irq_inputs_vector_int(9) <= irq_trigger_ready_4_i;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 0
process (clk_sys_i, rst_n_i)
begin
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment