dio: try to correct PPS output.

We have remove all connections (input and output) of first channel to the DIO. In the future we might re-add the input connection...

dio: try to correct PPS output.
We have remove all connections (input and output) of first channel to the DIO. In the future we might re-add the input connection...
0d7dc503 · Benoit Rat · Miguel Jimenez Lopez · 5bbf887a · 0d7dc503 · 0d7dc503
Commit 0d7dc503 authored Oct 28, 2013 by Benoit Rat Committed by Miguel Jimenez Lopez Apr 03, 2019
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wrsw_dio.vhd modules/wrsw_dio/wrsw_dio.vhd +3 -3

xwrsw_dio.vhd modules/wrsw_dio/xwrsw_dio.vhd +7 -3

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--- a/modules/wrsw_dio/wrsw_dio.vhd
+++ b/modules/wrsw_dio/wrsw_dio.vhd
@@ -40,7 +40,7 @@ entity wrsw_dio is
    rst_n_i          : in  std_logic;
    dio_clk_i        : in std_logic;
-    dio_pps_i        : in std_logic;
+   -- dio_pps_i        : in std_logic;
    dio_in_i         : in std_logic_vector(4 downto 0);
    dio_out_o        : out std_logic_vector(4 downto 0);
    dio_oe_n_o       : out std_logic_vector(4 downto 0);
@@ -97,7 +97,7 @@ architecture rtl of wrsw_dio is
      rst_n_i   : in std_logic;
      dio_clk_i      : in    std_logic;
-      dio_pps_i      : in    std_logic;
+  --    dio_pps_i      : in    std_logic;
      dio_in_i       : in    std_logic_vector(4 downto 0);
      dio_out_o      : out   std_logic_vector(4 downto 0);
      dio_oe_n_o     : out   std_logic_vector(4 downto 0);
@@ -142,7 +142,7 @@ U_WRAPPER_DIO : xwrsw_dio
      rst_n_i   => rst_n_i,
      dio_clk_i      => dio_clk_i,
-      dio_pps_i      => dio_pps_i,
+     -- dio_pps_i      => dio_pps_i,
      dio_in_i       => dio_in_i,
      dio_out_o      => dio_out_o,
      dio_oe_n_o     => dio_oe_n_o,

--- a/modules/wrsw_dio/xwrsw_dio.vhd
+++ b/modules/wrsw_dio/xwrsw_dio.vhd
@@ -52,7 +52,7 @@ entity xwrsw_dio is
    rst_n_i          : in  std_logic;
    dio_clk_i        : in std_logic;
-	dio_pps_i        : in std_logic;
+	--dio_pps_i        : in std_logic;
    dio_in_i         : in std_logic_vector(4 downto 0);
    dio_out_o        : out std_logic_vector(4 downto 0);
    dio_oe_n_o       : out std_logic_vector(4 downto 0);
@@ -621,11 +621,15 @@ begin
 	 select dio_out_o(i) <=
 		gpio_out(c_IOMODE_NB*i) when "00", --GPIO out as also 4 bits per channel
 		dio_pulse(i) when "01",
-		dio_pps_i when "10",
+		--dio_pps_i when "10",
 		'1' when others;	--Error output will stay at one (similar as GPIO set to one)
  end generate gen_pio_assignment;
-  dio_led_bot_o  <= gpio_out(28);
+  dio_led_bot_o  <=  dio_iomode_reg(c_IOMODE_NB*0+3) OR 
+							dio_iomode_reg(c_IOMODE_NB*1+3) OR
+							dio_iomode_reg(c_IOMODE_NB*2+3) OR
+							dio_iomode_reg(c_IOMODE_NB*3+3) OR
+							dio_iomode_reg(c_IOMODE_NB*4+3);
  dio_led_top_o  <= gpio_out(27);
  --gpio_in(29)    <= dio_clk_i;