ReviewFineDelayFMC10112010
Schematics layout review held on 10 November 2010
Present: N. Voumard, P. Alvarez Sanchez, M. Cattin, E.van der Bij
Files used for the
review:
https://www.ohwr.org/project/fmc-delay-1ns-8cha/tree/7/trunk/circuit_board/fmc-delay-1ns-8cha/Schematics
General*
- No DRC check crosses on unused inputs and outputs are not systematically placed.
Page 1*
- 50 Ohm input termination should not use a jumper as this will not be accessible. Make it programmable via the FMC connector.
- TRIGSEL should not use a jumper as this will not be accessible. Make it programmable via the FMC connector.
Page 6*
- The input level is not TTL (as specified), but is LVTTL. Now when entering a 5V signal, the diodes will continuously conduct, while not being protected in any way. The fuse will not trigger (or even worse, it maybe even will switch off) and there is no resistor limiting the current.
- Can the input fuse handle the bandwidth and short pulses? It is a device made for power use, not signal use. Or, dependent how it behaves it may heat up and increase resistance dependent on the input signal it receives and therefore may introduce a phase delay.
- What is the footprint of the fuse? Can it be replaced by a simple resistor when needed?
- The inputs of the input multiplexer IC17 (FET switch) are wrongly connected (signal 1D- can only go to unconnected D- output).
- Consider to use a single ended type multiplexer with output buffer (the one now used is a FET switch) so that the output level is well defined.
- The 47 Ohm input termination is in 1206 package and likely is too small to dissipate if a continuous high level is used. Check the fast ADC card , R129, 56 Ohm in 2512 package. See also ADC issue.
- Symbol MC100EPT20DTG (IC5) has the flash in the wrong direction on the input pin 7.
- Symbol 74AC74M (e.g. IC14) has CLR and PR texts rotated and overlapping.
Erik van der Bij - 10 November 2010