Preliminary specs
- 1 ns resolution.
- 10 us - 500 us range.
- 1 input.
- 8 individually controllable outputs.
- Input and outputs are LVDS, all in a single LVDS connector. Level translation will be performed in a separate active patch panel.
- Delay circuit reacts on input rising edge. Minimum input pulse width: 100 ns.
- Output pulse width is programmable in steps of system clock ticks (~125 MHz) with a 16-bit register per output channel.