Project Status
Date |
Event |
22-04-2010 |
Start working on project |
Preliminary specs
- 1 ns resolution or better.
- 10 us - 500 us range or better.
- 1 input, selectable between front panel and FMC connector.
- 8 individually controllable outputs.
- Input and outputs are LVDS, all in a single parallel LVDS connector.
Level translation will be performed in a separate active patch
panel.
- Delay circuit reacts on input rising edge. Minimum input pulse
width: 100 ns.
- Output pulse width is programmable in steps of system clock ticks
(~125 MHz) with a 16-bit register per output channel.
- Jitter will be measured by probing the positive pins of two output
channels which have been programmed with the same delay. The sigma
of the distribution of delay measurements between the rising edges
of any two channels should not exceed 100 ps. This should hold for
any programmed delay withing the nominal range.