Project Status
Date |
Event |
22-04-2010 |
Start working on project |
Preliminary specs
- 1 ns resolution or better.
- 10 us - 500 us range or better. (Greg - you ment 10ns?)
- 1 input, selectable between front panel and FMC connector.
- 8 individually controllable outputs.
- Input and outputs are LVDS, all in a single parallel LVDS connector.
Level translation will be performed in a separate active patch
panel.
- Delay circuit reacts on input rising edge. Minimum input pulse
width: 100 ns.
- Output pulse width is programmable in steps of system clock ticks
(~125 MHz) with a 16-bit register per output channel.
- Any requirements about the jitter?