Preliminary functional system specifications
- 1 ns resolution or better.
- Accuracy: /- (500 ps timebase stability).
- 200 ns - 120 s range or better.
- 1 input, selectable between front panel and FMC connector. This
input is shared by all output channels.
- Input electrical standard will be TTL, with optional 50 Ohm
termination. The default power-up state is high impedance. A LED
will signal termination status.
- External input needs to be protected against +15V pulses with a
pulse width of at least 10us @ 50Hz (with protection diodes if
possible).
- Need to withstand a continuous short-circuit on all the outputs at
the same time.
- Output standard: 50 Ohm TTL drivers (with 2V/ns or faster rising
edges). At power-up the default output state is low, with no
glitches.
- SMC connectors for input and outputs. LEMO variant should also be
explored if mechanically possible.
- 4 individually controllable outputs, with independent delay, width
and enable/disable.
- Delay circuit reacts on input rising edge. Minimum input pulse
width: 100 ns.
- Output pulse width is programmable in steps of system clock ticks
(~125 MHz) with a 16-bit register per output channel.
- Jitter will be measured by probing two output channels which have
been programmed with the same delay. The sigma of the distribution
of delay measurements between the rising edges of any two channels
should not exceed 100 ps. This should hold for any programmed delay
within the whole delay range.
- A circular buffer will contain time tags for at least the last 100
input and output pulses. These time tags will at first be rough UTC
(counter initialized by SW) giving ~ms accuracy. Later, with a
WR-enabled solution, they can be much more accurate.
Preliminary ideas for the technical specifications
- Baseline solution: TDC at the inputs followed by coarse count in the
FPGA and fine delay chips at the outputs. To be considered for
improving jitter: monolithic FFs in the FMC, before the fine delay
chips. Continuous calibration of fine delay chips might be needed to
compensate for Process-Voltage-Temperature (PVT) effects.
Project Status
Date |
Event |
22-04-2010 |
Start working on project |
30-04-2010 |
First meeting with N. Voumard to fine-tune functional specs |
20-05-2010 |
Second functional specs meeting with the ABT team |