Setup time violation on FPGA_TDC_START
PTS tests of a recent batch of Fine Delays show that some boards have a 'raw' (uncalibrated) in->out delay of 914 ns, while some others have 922 ns. There's a clear 8 ns jump here.
We've identified it's caused by setup time violation of the FPGA TDC start signal, which causes the FPGA's internal time base counter to be shifted by 8ns. A programmable IODELAY has been added to the firmware to mitigate this issue (branch tom-iodelay in git).
Things still to do (so that we don't forget):
- program the IODELAY in the device driver
- detect 922ns-calibrated boards in the driver and subtract the extra 8ns
- SPEC/SPEXI versions of the IODELAY-fixed VHDL
- release the bitstreams & drivers.