Enabling the WR mode after a WR link failure causes a "jump" in the card's time base, as the WR synchronization is re-done from scratch.

If the local time has not diverged too much (too much = a programmable threshold), realign local time to WR with SoftPLL phase shifter only, without touching PPS generator counters. This also applies to other WR-enabled cards (TDC, ADC).